JPH08272681A - Microprocessor with cache reconstitutible at instruction level - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor which has reconstructible caches on an instruction level. SOLUTION: This microprocessor contains a product-sum operation unit (MAU) 305 to execute a high speed signal processing operation. When a product- sum operation (MAC) instruction is executed, 1st and 2nd caches 301 and 302 directly supply 1st and 2nd operands (x and y) to the MAU 305. When a normal instruction is executed, multiplexers 310 and 311 are included which select data from either the 1st or 2nd cache 301 or 302. Translation lookaside buffer is included which has a page entry table that contains an additional 'reconstruction' bit and a 'way' bit to control writing data to the caches. Thus, this microprocessor can use a conventional set associative (set association) cache to simultaneously access plural operands.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having means for reconfiguring a set associative cache for operations with increased bandwidth.

[0002]

BACKGROUND OF THE INVENTION Many conventional microprocessors
It has a register file with multiple ports, so it is possible to provide the execution unit (EU) with the two operands contained in the register each cycle. The register file is contained on the same integrated circuit as an arithmetic logic unit (ALU) and is a very fast means of providing the desired data. For example, referring to FIG. 1, a typical prior art microprocessor 100 has a first address (address 0) in a first register file 102 and a second address in a second register file 103. It includes an instruction register 101 that supplies (address 1). The register files 102 and 103 illustratively have 32 entries of 32 bits each. The first register file 102 supplies the first operand to the first operand register 104, and the second register file 103
The second operand is supplied to the second operand register 105. The registers 104 and 105 supply the arithmetic logic (arithmetic) unit (ALU) 106 with the first and second operands, and the arithmetic logic (arithmetic) unit (ALU) 106 illustratively sums of products. Operation (MA
Various arithmetic operations may be performed, including C). The result is
Saved in result register 107, via line 108,
It can be written back to the register file. In an alternative embodiment, a single dual port register file (not shown) is used instead of the two files 102, 103. In that case, the two read ports are in the register file,
It will allow simultaneous access to any two entries.

[0003]

However, there are many cases where it is necessary to supply two operands contained in a memory that is not in a register on the chip.
An example thereof is a product-sum operation instruction, which is one of the basic principles of signal processing. The two memory operands, if available, are typically contained in a data cache on chip or, optionally, in an external cache to the microprocessor chip. In either case, supplying two operands to the execution unit (EU) each cycle means dual porting the data cache. A typical instruction is MAC x, y, a0. Here, MAC is a shorthand notation for an instruction called multiply-add operation, and the operation specified by this is a0 = a0
It becomes + (x ^* y). Typically, x and y would belong to a particular array in memory, where x could be located in the coefficient array and y in the data array.

Referring to FIG. 2, two of the memories on the chip
An example of a microprocessor 200 having two banks is shown. The instruction register 201 supplies the first and second addresses (address 0, address 1) to the bank 0 (202) and the bank 1 (203) of the cache, where each bank is, for example, The size may be 1 kilobyte. The data is written to the cache via the write line 213. The first operand is the read output read from bank 0 (202) and selected by multiplexer 204. Then, the first operand is latched (temporarily held) in the operand register 1 (205). Similarly, the second operand is bank 1 (20
3) The read output read from 3) and selected by the multiplexer 206. Then, the second operand is latched (temporarily held) in the operand register 2 (207). Optionally, the operands are sent by the multiplexers 204 and 206 to the external memory bus 212.
Can be selected from In addition, the operands are provided to the ALU / MAC unit 208 from the operand register, where the operands are multiplied together,
It is added to the previous result accessed from the accumulator file via path 214. The result is supplied to the result register 209 and stored in the accumulator file 210. Such a technique has a product-sum operation function in the conventional microprocessor architecture, but there is a disadvantage in such an approach. For example,
Since the memory on the chip is configured as RAM rather than cache, it is only available to selected applications. All data addresses in memory must be determined when the application program is developed.
As such, conventional microprocessor applications do not allow for flexible use of memory here. In addition, it is difficult to run applications from different vendors.

[0005]

The inventor has invented a data processor and a data processing system having a cache with n ways (types) of association. In this cache, the first operand (x)
Is located in the first part of the cache and the second operand (y) is located in the second part of the cache. Output of the first and second parts of the cache (x,
y) is supplied to a functional unit such as a product-sum operation unit when a given instruction format such as a product-sum operation instruction is executed. The multiplexer is connected to the outputs of the first and second parts of the cache. Therefore, when the cache is to be accessed as a conventional set associative cache to execute different types of instructions, operands can be fetched from either site. It is possible. To control writing to the cache, the translation lookaside buffer may contain a page table entry with a reconstruction area,
Other control methods may optionally be used.

[0006]

Detailed Description This detailed description is reconfigurable set associative.
It relates to a microprocessor that uses a cache. When an instruction that requires a high data bandwidth is executed, in the first arrangement the cache will send one operand and in the second arrangement multiple operands (x, y) to the arithmetic processor at the same time. Supply. As used herein, the term "simultaneously" can include (one or more) clock cycles,
It means that in a cycle on the same machine. An example of such an instruction is a multiply-add operation instruction. In this way, fast multiply-accumulate operations can be implemented, for example, in a general purpose microprocessor. Caches are typically n ways (form)
Set associative cache, and the present technology also allows the cache to be used as a cache with a plurality of direct mappings. Reconfiguration from an n-way (formal) set associative cache to a directly mapped cache and vice versa can be performed on a per instruction basis. As used herein, the cache portion is also referred to as "cashway 0,""cashway1," or, more generally, "cashway n," where n is a positive integer. To be done.

Referring to FIG. 3, an exemplary embodiment of the present invention includes cache sites 301 and 302,
A two-way (form) set associative cache is shown. The data output of the cache parts 301 and 302 is sent via the data lines 303 and 304, respectively, to the product-sum operation unit (mul).
tiply-accumulate unit (MAU) 305.
In addition to the x and y data inputs, MAU 305 receives an accumulator input from line 308 from accumulator file 312. MA
The U 305 includes a multiplier 306 and an accumulator 307, which have various designs, including those known in the art, as far as the invention is concerned. I will get it. When the operation is in progress and the multiply-accumulate operation instruction is being executed, the operand x accessed from the cache part 301 via the multiplexer 310 and the operand y accessed from the cache part 302 via the multiplexer 311. , The MAU 305 is instructed to perform the multiply-accumulate function. However, when another form of instruction is about to be executed that does not require simultaneous operands from the cache, the multiplexer 311 will provide the desired data to the cache location 301, cache location 302, or external location. The output is selectively selected from the memory bus 312.

It should be noted that the exemplary embodiment is for a two-way (form) set associative (set associative) cache. However, the present invention can be implemented for any n-way (formal) set-associative cache, where n is any positive integer. In the following discussion, N is illustratively even (and n = 2, by way of example), but alternatively n can be odd. Generally, this point is n inputs (from each cache site).
Can be implemented using a multiplexer having n is 2
When greater than, the n possible placement strategies for accessing the two operands are determined by the particular implementation, any of which may be used in the present invention. Furthermore, when the cache is configured as a conventional n-way (formal) set associative (set associative) cache, the replacement algorithm for that cache may use any technique as far as the invention is concerned. Can be realized.

As is known in the art, memory management page tables are used to translate virtual addresses into physical addresses and also to control cache operations. The page table is stored in a translation lookaside buffer (TLB), which translates virtual memory addresses into physical memory addresses. The TLB also contains control information about the memory page and whether a given page is cacheable. Referring to FIG. 4, an exemplary page table entry includes a physical address “tag” (in bits 12 to 31) in region 41. The tag indicates the most significant bit of the address and determines if the desired address is located in the cache, in which case the cache "hit" is the LHIT in FIG.
320 or RHIT 321. The "index" part of the address (not shown)
Indicates the least significant bit, and the pointer (322,
323) in a manner well known in the art to direct the desired location of a given cache site (301, 302, respectively). The area 42 can include, for example, unused bits, and the area 45 can include:
The data in a memory page typically includes a "grant" bit that controls whether it is writable, valid, cacheable, or accessible to the user, for example. As far as the invention is concerned, these areas can be in any order. Referring to FIG. 5, the TLB contains exemplary page table entries along with virtual tag 501 as physical tag 502 and control bits 503. Such an approach also translates virtual addresses into physical addresses in accordance with principles known in the art.

In order to implement the techniques of the present invention, as described above, additional control bit (s) (s) may be added:
It may be included in the memory management page table. For example, region 43 may include even or odd "way" (form) bits that indicate how the data should be written into the cache, as described further below. Region 44 may include "reconstruction" bits. When the reconfiguration bit is 0, the cache has a conventional 2
It is treated as a way (form) set associative (set associative) cache. That is,
Data is written to cache way 301 and cache way 302 using the selected cache entry replacement scheme. On the other hand, when the reconfiguration bit is 1, the two-way (form) set associative cache is treated as two directly mapped caches. Then, if the way bit of area 43 is 0, the data is directed to be written to an even way (form) cache site, and optionally, if the way bit of area 43 is 1. Will be written to the odd way (form) cache site. The data is placed in the appropriate cache location in this manner for use by the MAU as x and y operands for executing multiply-add operations or other special types of instructions. Operating system (O
In the presence of S), the user program could instruct the OS to set the "reconfiguration bit" and the "way bit" by way of a special function call. In this manner, the data processing system including both the data processor and the operating system can effectively use the technique of the present invention.

By convention, the left operand (ie x in the above example) is fetched (fetched) from way 0 and the right operand (ie y in the above example) is from an odd way. Fetched (retrieved). However, other conventions are possible.
Furthermore, since it is used with the present invention, another technique for controlling the writing of data to the cache part is also conceivable. For example, the instruction to load the cache may unambiguously specify where in the cache the data should be written. To accomplish this, way bit (s) (313) may be included in the instruction register of FIG. In that case, the memory management unit and TLB may not be needed. Also, the placement of x and y data need not be split into even and odd way caches, but can be placed within the cache in some convenient way. That is, as will be apparent to those skilled in the art, multiple operands can be fetched (fetched) from the cache at the same time for various operations performed by the functional units. Please note.

The data processor of the present invention is typically of the type conventionally referred to as a "microprocessor", but it is contemplated that other purposes and types are contemplated and they are also It is included here. For example, digital signal processors with enhanced functionality for instructions other than MAC may also benefit from the present technology.

[0013]

According to the present invention, set-associative (set-associative) caches and set-associative (set-associative) caches that can be mutually reconfigured on a per instruction basis can be mutually reconfigured. Associative) A microprocessor utilizing a cache was realized. This allows more flexible use of memory in microprocessor applications. For example, for the product-sum operation (MAC) which is a typical signal processing, a high-speed product-sum operation is
For example, it can be implemented in a general-purpose microprocessor.

[Brief description of drawings]

FIG. 1 shows a prior art microprocessor having two register files that store operands.

FIG. 2 shows a prior art microprocessor having a random access memory (RAM) on a chip containing multiple banks for storing operands.

FIG. 3 illustrates an exemplary embodiment of a microprocessor according to the present invention.

FIG. 4 illustrates an exemplary page table entry in accordance with the present invention.

FIG. 5 may be used in the practice of the invention,
3 illustrates an exemplary translation index buffer.

DESCRIPTION OF SYMBOLS Microprocessor according to the prior art 101 Instruction register 102 First register file 103 Second register file 104 First operand register 105 Second operand register 106 Arithmetic logic (arithmetic) unit (ALU) 107 Result Register 108 Line 200 Prior Art Microprocessor 201 Instruction Register 202 (RAM) Bank 0 203 (RAM) Bank 1 204 Multiplexer 205 Operand Register 1 206 Multiplexer 207 Operand Register 2 208 ALU / MAC (Arithmetic Logic / Sum of Sum) Unit 209 Result register 210 Accumulator (accumulator) file 211 Operand access control logic 212 External memory bus 213 Write line 30 Cash way 0 302 Cash way 1 303, 304 Data line 305 Multiply-accumulate unit (MAU) 306 Multiplier (multiplier) 307 Accumulator (accumulator) 308 Line 310, 311 Multiplexer 312 External memory bus 313 Control bit (way bit) ) 314 Instruction register 316 Multiplexer 317, 318 Conversion lookaside buffer 319 Multiplexer 320 LHIT 321 RHIT 322, 323 Pointer 324 Access control 325 First signal path 327 Second signal path 41 Physical tag 42 Unused (area) 43 way ( Format) Bit 44 Reconstruction Bit 45 Grant Bit 500 Translation Index Buffer 501 Virtual Tag 502 Physical Tag 503 Control Bit

Claims (6)

[Claims] 1. An instruction register (314), wherein n is an integer of 2 or more, and a first cache part (30)
1) and a second cache part (302), an n-way set associative cache, and an operation on the first and second operands (x, y) when the instruction is executed. Functional unit to perform (305)
A first signal path (325) from the first cache site that supplies the first operand (x) to the functional unit; and when a special form of instruction is executed, the first signal path And a second signal path (327) from the second cache site that supplies the second operand (y) to the functional unit at the same time as the operand of Selecting data from either the first or the second cache part,
A data processor comprising: a multiplexer (310, 311). 2. A translation lookaside buffer (500) having a page table entry (FIG. 4) containing a reconstruction area (44), which controls how data is written to the cache. The data processor of claim 1, wherein: 3. The page table entry is further written to a cache where a first set of data is direct mapped for even ways and a second set of data is direct mapped for odd ways. The way area (4
3) The data processor of claim 2, including: 4. The control bit (31), wherein the instruction register controls writing of data to the cache part.
3) The data processor of claim 1, including: 5. The data processor of claim 1, wherein the special form of instruction comprises a multiply-accumulate operation instruction. 6. The data processor of claim 1, wherein the functional unit is a product-sum operation unit.