JPH08272393A - Decoder for audio signal belonging to compressed and coded audio video stream - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoder for sound signals belonging to sound and image stream encoded by ISO/IEC11172 standard. SOLUTION: This decoder comprises an output unit UP and the output unit is controlled by a first and a second clock signals depending on a desiring sampling rate and connected with a means SAV to manage desiring synchronism of sound and image. The managing means SAV starts sending out output data by comparing a first timing signal SCR expressing the system clock signal with a second timing signal PTS expressing the correct time of the data output, generates independently two clock signals CLK24, CLK22, and corrects a signal corresponding to a desiring sampling rate by a feed-back circuit containing a digital filter FD.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a processing system for digitized audio and video signals, in particular ISO /
The present invention relates to a decoder for an audio signal belonging to a digital audio / video stream coded according to the IEC 11172 (or ISO / MPEG-1) standard. For ease of description, in the following, "MP
It is called "EG standard" or "MPEG stream".

[0002]

2. Description of the Related Art The MPEG standard is a standard for outputting compressed and encoded audio and video data, and enables data exchange between compatible terminals.
And to provide a standardized decoding method. This standard is provided for the structure of compressed and encoded data for packet transmission. Its structure is hierarchical, so that at higher levels (system layer), so-called audiovisual "packs" start with a pack start code and a pack end code.
The transmission of the (pack) sequence is required. This sequence ends with the transmission of the sequence end code (ISO 11172 end code). The next level down (pack layer) determines the structure of the pack, each of which contains a start code followed by timing information, a so-called system header, and some audiovisual packets for one or more channels. Stipulate. Each packet is
It contains a header with service information and the actual data. When the decoding is done, the different types of packets in the pack are demultiplexed and separated by using the service information in the pack (start code, synchronization information and system header) and in the packet header. Decrypted.

In the case of a speech signal, which is one of the objects of the present invention, the data inserted in the packet is constructed in a speech frame containing a fixed number of samples.
The coding is sub-band coding, and the bit allocation to different sub-bands is decided based on an appropriate human perception model. During the decoding phase, in addition to recovering the original audio signal, it is also necessary to solve the problem of synchronization with the simultaneously transmitted image. According to this standard, audio data can be sampled at a certain number of rates, especially 32kHz, 44.1kHz, and 48kHz, and that the 44.1kHz rate is common to the other two rates and does not have a practical multiple. Making the problem particularly difficult.

[0004]

A commercially available MPEG audio decoder directly generates a clock signal corresponding to a sampling rate of 32 kHz and 48 kHz, and uses an accumulator to generate a second clock related to a 44.1 kHz sampling rate from the latter signal. Get the signal. The accumulator loads a small user-programmable value each time the counter that generates this clock signal has finished counting, and increments the count by one when the stored value exceeds one. This solution is unsatisfactory because the correction is very sharp and unacceptable in the output digital-to-analog converter, especially if the digital-to-analog converter is of high quality. Moreover, the known device provides any means for recovering a possible phase shift between the timing indication associated with the data stream (based on the clock signal generated by the encoder) and the clock signal generated by the decoder. It does not include.

[0005]

According to the speech decoder of the present invention, the modification of the second clock signal is also directly managed by the decoder smoothly without using an external device, and the timing related to the data stream is also provided. Means are provided for recovering any possible phase shift between the instruction and the clock signal generated by the decoder.

[0006]

The features of the invention are set forth in the following claims. For more clarity, reference is made to the accompanying drawings. As can be seen from FIG. 1, a decoder DMP for decoding an audio / video stream encoded according to the MPEG standard comprises in principle a system decoder DS, which system decoder (eg, remote SA These streams are received from the encoder and demultiplexed into an audio stream and a video stream. These audio and video streams are sent to the respective decoders DA, DV in their encoded form as outlined by connections 1 and 2. The system decoder DS is DA, DV, as represented by connection 3.
Also gives timing information to. Decoder DMP is the controller
Connected to the CN, this controller CN can also program and manage the various components of the DMP (connection 4) and perform the functions of the DS. However, for simplicity, the figures depict the decoding system and programming / management components as separate units. The decoded stream is then sent to the audio and video terminals TA, TV.

Speech decoder DA forming the main part of the present invention
Can decode monaural or stereo audio signals compressed in the format defined by the so-called audio layers I and II of this standard. Decoder DA is an integrated circuit component,
Receive the encoded audio stream and the configuration data via a parallel bus. This parallel bus can be configured by the user as an 8-bit bus or a 16-bit bus, in order to favor data. The decoder transmits state information to the controller via this same bus. The decoded audio signal has several sampling rates, especially 32kH
It is transmitted in the z, 44.1kHz, 48kHz PCM serial format. In addition to performing the decoding function, the DA also manages recovery from possible error conditions in the data stream and also manages synchronization of the transmitted audio signal with its associated video signal. The entire device can also be reset to an initial state via the command word. The structure of DA is shown in more detail in FIG. In order to facilitate understanding of the present invention, the structure of the MPEG pack will be briefly described with reference to FIG. 2 before describing the structure.

[0008] The MPEG audio / video pack includes service information (here, it is represented by the entire pack layer header (Pack Layer Header, PLH) and system header (System Header, SH), and the system header can be selected). It includes packet sequences PKT1, PKT2, ..., PKTn. Each packet has a packet header PHD, as shown for PKT1.
And a predetermined number of data bytes PDA. For voice packets, the packet header PHD contains: (A) 3-byte PSC that constitutes the packet start code. This is used to identify packet synchronization. (A) A 1-byte SID that encodes the identity of the stream to which the packet belongs. (C) A 2-byte PL that encodes the packet length. (D) Variable number of bytes HDA. Some of the bytes are at a sampling rate of 44.1kHz, or when the data is in free format (ie, at a bit rate different from the standard and at a rate lower than the maximum rate allowed by the encoding mode adopted). Stuffing bytes used when the transmission takes place), the other bytes contain service information not of interest to the invention. (E) A group of bytes T containing possible timing indications
S. Possible timing indications are no indication, output time stamp PTS, or output time stamp and decoding time stamp DTS. The number of these bytes depends on the transmitted timing indication, and in a more preferred implementation of the invention, the time stamp DTS is present in the data stream but not used.

The packet data bytes are inserted in a fixed length frame (so-called coding layer I is composed of 384 samples, and coding layer II is composed of 1152, that is, 384 × 3 samples). Only one frame FRi is shown in the figure. The frame contains: (A) Encoding level, audio stream type (stereo / monaural), bit rate, sampling rate,
A header (FHD) consisting of a sync word SYW and a control word CW specifying the emphasis (if any), a bit allocation table for the subbands, and the scale factor information. (B) Audio sample AUS. (C) Error detection word CRC and auxiliary data AND defined by the user such as a subtitle for video. It should be noted that the structure of the frame is independent of the structure of the packet, and the frame can spread into consecutive packets. In this case, if TS (Fig. 2) is stamp PTS
If included, the later packet is related to the first frame that started with the previous packet.

FIG. 3 is a functional block diagram of a decoder according to the present invention. For simplicity, the various input and output signals of the components and the signals exchanged between the various units are not drawn. In the figure, the signals of interest to the invention are more apparent. Decoder DA is system interface IS
Via bus 5 (corresponding to the set of connections 1 and 4 in FIG. 1). The system interface is a conventional microprocessor interface that manages the interaction of the decoder with the outside world and programs the decoder. The IS receives voice packets and synchronization information (particularly the system clock signal SCLK) from the DS (Fig. 1) and programming information from the CN. IS also
It informs the controller CN about the state of other circuits in the decoder. The interaction with the outside world via bus 5 takes place entirely using conventional protocols.

Via programming registers included in the IS, the IS can control: (A) Input / output data format (i) Output data oversampling factor (data can be sent at baseband, i.e. without oversampling, or can be oversampled by a factor of 2, 4, 8). U) Input audio data stream selection (E) Audio data output enable / disabling (E) The parameters and data format of audio / video synchronization management circuit described below are in this decoder. The interrupt signal INTR can be generated in response to the event transmitted by the circuit of. Among these events are the following: (1) Recognition of the PTS stamp in the input data flow (2) Synchronization error (3) Output data output start (4) Locking to input data stream synchronization (5) Phase shift recovery not possible, that is, output unit and / or
Or error condition of synchronous search / inspection unit

Other information that can be accessed from the outside is as follows. (1) The last decoded control word of the frame (2) The value of the last PTS stamp extracted from the data stream (3) The indication of the state of some internal circuits IS is an input buffer via connection 10. It sends the audio data to be decoded to the memory M1 and also provides, via connection 11, a so-called "system clock reference" SCR to the device SAV which manages the audiovisual synchronization. This system clock reference SCR is calculated by an internal counter controlled by the system clock signal SCLK,
It is used to generate and modify the audiovisual sync signal. The interface IS also provides control signals to the other units of the device, but a detailed description thereof will not be necessary. The interface IS receives from them state information that should be used externally. Line 12 schematically represents a connection for exchanging command signals and status information between the IS and other units.

The memory M1 compensates for variations in the input data rate and supplies the data in a format determined by the downstream unit. The memory M1 sends the voice data to the voice packet parser AS via connection 13. The voice packet parser AS recognizes the structures belonging to the "voice packet" layer of this standard and derives from them important information for the decoding process. In other words, the AS has to recognize the service byte contained in the packet. Since the structure and sequence of these bytes are defined by this standard, the structure of the logical network for such recognition has already been defined by this standard, and therefore a detailed description of AS is not necessary. The AS sends "net" data (ie, without service information) on connection 14, which data is sent downstream only after the output timestamp PTS is detected. Until then, these data are discarded as they cannot be associated with the output time. The output time stamp PTS is also provided to the audiovisual synchronization management circuit SAV (connection 15) and its presence signal is also emitted along the encoding chain in synchronism with the data it references.

In the event of an event that prevents the correct recognition of the service byte sequence, such as an error in the packet structure or in the stream identifier, the AS will generate a signal used to stop sending the output data stream,
Send to the synchronous search / inspection circuit RS via connection 16. Data is
It is sent from the AS to the audio stream decoder DFA, where the required operations of the "audio" layer of the standard are performed. In particular, DFA
Recognizes the sync word present at the beginning of each speech frame. The frame header is decoded and information about the decoding process (control words, allocation table, sample scale factor table) is extracted from such header. If the header is protected, its integrity is checked. The audio data contained in the frame is decompressed, requantified and rescaled. Then, the conversion from the frequency domain to the time domain and the windowing defined in this standard are performed. Note that any auxiliary data present in the frame after the audio data is discarded. For its operation, the DFA is connected to a working memory, not shown. No further details regarding decryption will be necessary. See the text of this standard for details, especially Part 3 of the text (ISO / IEC 1117
You can see it by looking at 2-3), and there is a flowchart of the decoding operation.

The DFA informs the sync search / check unit RS about the acquisition or loss of frame sync (connection 17),
Correspondingly, it receives information that manages the progress of the decoding operation. The data decoded by the DFA is sent to the output buffer M2, which is composed of pages, for example, via the connection 18 in a manner dependent on the coding layer and the type of audio stream. The data is sent from M2 to the output unit UP via connection 19. The output unit UP manages the serialization and output of the decoded audio samples via connection 21. Serial data depends on the programming of the component,
It may be sent in baseband or factor 2, 4, or 8 oversampled in "two's complement" or "offset binary" format. The unit UP also generates the signal BCLK (described in connection with FIG. 8) indicating the sampling time of the output data. From programming information
UP sends a "mute" frame when the IS-derived signal is present on connection 12 or for a period set by unit RS which supplies the required information via connection 22 (silence function ). Synchronous search / inspection unit RS
Manages the search for synchronization in the input data stream and its recovery if there is an error or interrupt in the stream. Based on the information provided by AS and DFA, the correct distance between consecutive sync words is checked. If it is free form data, unit RS also checks the length of the frame being used. The unit RS sends to the outside via the interface IS the identification of the synchronization and any possible synchronization errors. The operation of RS is described in more detail in connection with FIG.

The audio / video synchronization management unit SAV performs the following operations. (1) Data output is started by comparing the system clock reference SCR with the device internal time. The internal time of this device is AS
Indirectly estimated from the time of data output associated with the indicator PTS given by. The output start command is given to UP via connection 24. (2) Timing signals (CLK2
4) occurs. This signal is provided to these different circuits via connection 20a. (3) Appropriate feedback circuit FD including a digital filter to minimize the difference between SCR and internal time.
To control the data output rate. Any discrepancies between the SCR and the internal time beyond the operating range of the digital filter will stop filtering and be signaled to the controller via IS. The output timing signal is provided to UP via connection 20. Where connection 20a
Is part of connection 20.

By keeping the output frequency and the internal time locked to the corresponding system values, synchronization between the transmitted audio data and the associated picture is guaranteed. For its operation SAV needs the information contained in the control word CW,
The information is provided to SAV by DFA via connection 23. The block SAV essentially consists of two parts: a correction unit FD and a unit GT which actually generates the timing signal. The latter unit GT is outside the integrated circuit DA surrounded by the chain line. To simplify the figure, the signal SCLK
The connections and connections that carry CLK24 and CLK24 are drawn to the boundaries of the integrated circuit, not to all the units that use those signals. Also, for the sake of simplicity, the signals for memory addressing and the signals for instructions are not shown because they are not interesting to the present invention.

The structure of the block SAV will be described in more detail with reference to FIGS. As already mentioned, books at a first rate of 48 or 32 kHz (in the present invention derived from a frequency of 24.576 MHz) or a second rate of 44.1 kHz (derived from a frequency of 22.5958 MHz). Audio data according to the standard can be sampled. Two clock signals CL generated in the block GT depending on the sampling rate used
Data output is controlled by either K24 or CLK22. Block GT is a pair of digital-analog converter DA
Together with C1, DAC2 and a pair of voltage controlled oscillators VCO1, VCO2 which generate two signals CLK24, CLK22, they basically form a digital phase locked loop. The signal CLK24 also constitutes the timing signal to the other units in the DA, and therefore
The signal is provided to those units regardless of the sampling rate of the output data. However, only when the output data sampling rate is 32 or 48 kHz, FD
CLK24 inspection and modification by

According to the instruction of the system clock signal SCLK,
The input counter CN1 counts the signal SCR given by IS and sends the count value to the positive input of the subtractor ST1. The subtractor ST1 outputs the output time stamp value from this count value.
Subtract PTS. This output time stamp value PTS is provided by the parser AS (FIG. 3) via connection 15 and is held in register R1. ST1 receives at another subtraction input a signal DIFFB representing a fixed numerical value (actually a signal representing a unit value). This signal DIFFB is the difference SCR-
It compensates for the fact that PTS is calculated with a delay of one SCLK period, so that the various signals that arrive unsynchronized and are necessary for operation can be locked to SCLK by this circuit. The output of ST1 is provided to digital filter FN via connection 27. The digital filter FN defines its zero point, pole, gain, and output data format as a system interface IS.
It can be programmed via (Fig. 3). If the difference SCR-PT
If S 1 is within the preset limits, the filter FN produces an output start signal on output 24 and a correction signal on a group of connections of connection 26. This correction signal depends on the selected output frequency and is used by two digital-to-analog converters.
Converted to an analog signal by either DAC1 or DAC2,
It is used to drive the oscillator VCO1 or VCO2, respectively. FN
Sends a command to select one of the transducers on the other group of connections of connection 26. When the output unit UP recognizes the time stamp PTS, UP is connected via connection 25.
Allow the FN to send out a correction signal. When the data output rate is 44.1 kHz, and therefore when the signal CLK24 should not be modified, the converter DAC1 may, for example, have a value corresponding to the center value of the allowed range of the difference SCR-PTS (hereinafter referred to as "center value of the filter band"). The value set during the initialization stage of the device, such as ".

In FIG. 5, the digital filter FN includes an operating unit UOF (that is, a unit for performing a filter conversion function), a logical network LC1 for controlling the operating unit, and a logical network LC2 for managing external signals. Is shown. Both logical networks are made up of finite state machines. The operating unit UOF includes a multiplier ML1, which receives the difference signal DIFF from ST1 (FIG. 4) and which provides a gain G over connection 12a of connection 12.
And outputs the signal DIFFG by multiplying the difference signal DIFF by. The gain G can take a finite number of discrete values (e.g. 2, 4, 8) and the multiplier ML1 is preferably realized by shifting combinatory logic. The signal DIFFG is added to the signal RP which is the output signal of the divider DV1 by the adder SM1. The divider DV1 divides the output signal of the filter memory register RM by the value P of the pole (which is present on the connection 12b of the connections 12). This pole can also take a finite number of discrete values, and the divider DV1 is also advantageously implemented by shifting combinatorial logic. The output signal of RM is also connected in the second divider DV2, which is similar to DV1, to the connection 12
Divide by the filter zero value, Z, present in c. Then the output signal of DV2 is subtracted from the output signal of SM1 in the subtractor ST2 and the filtered signal OUT
Is output.

The filtered signal OUT is stored in the output register RU. Output register RU is the converter DAC
The value VF to be loaded into the connection 26 is supplied to connection 26a of connection 26. The most significant bit of signal VF is combined with signal VFOB in exclusive OR gate PX. Signal VFOB is provided by the controller via interface IS and connection 12e and indicates the data output format. That is, if VFOB = 1,
It is an Osset binary format, and if VFOB = 0, it is a two's complement format. Furthermore, during the initialization phase, the VF value corresponding to the center value of the filter band is set in the filter output register RU. The load instruction to the memory register and the output register is represented by the signal CK sent by LC1. The exact time relationship between different events is of no interest to the present invention.

FIG. 6 is a state diagram of LC1. The following stages can be recognized in the operation cycle of the filter. (1) Reset DAC1, DAC2 and VCO1, VCO2. (2) Wait for timing reference SCR, PTS. (3) Synchronize with SCLK and check that the difference between SCR and PTS is within the preset range. (4) Generate an output start signal (START). (5) Wait for PTS from the output unit. (6) Actually filter.

Furthermore, especially the initial state of the filter VCO_
At RST, the logic network LC1 is one of the converters and its corresponding oscillator (eg DAL1, VCO1, signal IVSE
Select L = 1) and subtract value 1 from the difference between SCR and PTS (DIF
FB = 1), DAC1 and VCO1 are reset VCO_RST1
Move to Upon reset, LC1 requests LC2 (WRVFOUT = 1) to write the center value of the filter band stored in RU (Fig. 5) to the converter. LC1 sends a signal to confirm that reset has been performed (WRVFRDY = 1).
LC1 remains in state VCO_RST1 until received from 2. After that, LC1 is in the reset state VC of DAC2 and VCO2.
Move to O_RST2 (IVSEL = 0). The operation performed on VCO_RST2 is the same as that performed on VOC_RST1. When a new confirmation signal arrives from LC2, LC1 goes to the SCR, PTR waiting state (state VCO_WAITSP). In this state,
The converter and the oscillator corresponding to the desired sampling frequency (information contained in the control word CW) are enabled by setting IVSEL to the appropriate value and a flag (SFLAG, PFLAG) indicating a valid SCR and a valid PTS. Is awaited.
These flags are the same unit that supplies the SCR and PTS via connections 11b and 15b of connections 11 and 15 (hence,
IS and AS) and their respective registers (SFLAG_R, PF
LAG_R). If both a valid SCR and a valid PTS are recognized (SFLAG_R & PFLAG_R = 1), LC1 goes into synchronization with the system clock and checking the difference between SCR and PTS.

In the first state (VCO_SCLK1) at this stage, SC
The pulse of LK is awaited, and when that pulse arrives, the state VC
Go to O_STCHK, where the difference between SCR and PTS is checked. For the system to function properly, PTS-e1
The condition ≤ SCR <PTS should be verified,
The filter can recover even in situations where PTS ≤ SCR ≤ PTS + e2. If SCR >> PTS (ie if SC
R-PTS> e2), the error state VCO_ESTART is entered, where the error signal ERROR is the interface IS.
(Fig. 3), SFLG_R is set to zero. signal
ERROR is sent on connection 12d (FIG. 5) of connection 12. The error condition can be exited by external intervention, eg the arrival of a new SCR.

If SCR <PTS or SCR ≤ PTS + ε
If 2, enter the generation stage of signal START. Especially if S
If CR <PTS, the logical network LC1 is in state VCO
Move to START. This state enables the data output and pre-synchronizes the filter and the output unit UP (Fig. 3). Logical network LC1 has SCR = PTS and S
When CLK = 1, the state is changed. That is, STAR to UP
The T signal is generated and sent on output 24 (FIG. 5), causing LC1 to go to state VCO_FILT. This state represents a normal filtering cycle. That is, a filtering cycle is performed here and no modification is required, so it is generally an idle cycle. Then LC1 moves to state VCO_WPTS and waits for the next PTS. If PTS ≤ SCR ≤ PTS + ε
If 2, the signal START is immediately generated and LC1 goes directly to state VCO_WPTS. Here DIFFB is set to 0,
UP when it is time to perform filtering (PTSPU = 1)
LC1 waits to communicate with, i.e. UP via connection 25
Wait for the PTS signal.

When this signal arrives, LC1 is in state VCO--
Move to FILT. Three situations can occur here: (A) The difference between SCR and PTS takes a value within the range ε (ε = ε1 + ε2) that can be restored by the filter. Filtering is performed by loading the calculated value DIFFG + RP, OUT into the memory register RM (Fig. 5) and the output register of the filter respectively, and LC1 is in the state VCO.
Return to _WPTS. (B) If SCR << PTS (ie, SCR <PTS-ε1), the signal START is set to 0, thereby stopping the output of output data and LC1 returning to the state VCO_START. (C) If SCR >> PTS, an error signal is generated and LC1 returns to the wait state VCO_WPTS.

The logical network LC2 is basically a connection 26b.
The following three signals are sent out (FIG. 5). That is, the signal VFSEL for selecting the converter DAC1 or DAC2 based on the instruction IVSEL given by LC1, the signal VFCSN for enabling the converter, and the output 26a of the register RU based on the instruction WRVFOUT sent by LC1. Is a signal VFWRN that commands the loading of the selected transducer with the value VF present in.
LC2 supplies the signal WRVFR to LC1 when the operation is completed. It is easy for those skilled in the art to implement a logical network that performs these operations.

FIG. 7 is a state diagram of the synchronous search / inspection unit RS. From the figures given, it is easy for a person skilled in the art to realize a logical network that operates according to the figures.
For simplicity, only the conditions that determine certain transitions are shown in the figure. The actions taken at various states or during transitions are described in the attached Appendix I. It does not describe transitions that do not cause any action, as in Appendix II described below. As in the appendix, the symbol! , &, | Indicate logical conditions NOT, AND, OR, respectively. unit
The RS is a logical network that manages a group of counters and basically performs the following operations. (1) For a free-form stream, determine the number of bytes contained in the frame being processed. (In fixed format, the number of bytes is written in each frame header.) (2) Verify that the distance between two consecutive sync words is correct. (Ie verify that synchronization has been achieved and maintained.) (3) Calculate the number of frames that have elapsed between the start of the stream and the synchronization lock operation (ie the number of frames that should not be sent to the output unit). To do.

The initial state RST is the reset state of all registers and counters in RS. These registers and counters include: (1) BIT_REG: Register that stores the count of the number of bits in 1 byte (2) BYTE_CNT: Counter of the number of bytes in the frame (3) FLAG_REG: Register that stores a flag that indicates the end of counting the number of bytes (4) GLOB_CNT : Counter of the number of words after PTS (5) LDNMUTES_REG: Register that stores a flag that indicates the end of counting the number of bytes that should be suppressed (6) NBYTES_REG: Register that stores the number of bytes in the frame (7) NMUTES_REG: Suppressed Register that stores the count of the number of bytes that should be stored (8) SYNC_REG: Register that stores the flag for synchronization recognition (9) SYNCLOST_REG: Register that stores the loss-of-sync flag All of the above registers / counters except GLOB_CNT,
Although resetting is to set the value to 0, in GLOB_CNT, in consideration of the fact that some counting cycles are lost in the initial operation stage of the device, a negative value is set so that the counting actually starts after the stamp PTS is reached. Number of (eg -2)
Set.

If there is an error or packet loss of synchronization (signal PSYNCL) signaled by AS (FIG. 3), status RS
T can be reached from all other states of the device (transition 0). When this transition occurs, the loss of sync flag is set to 1 and stored in SYNCLOST_REG. This device is in the state RST
From START to state START and recognize sync word (SYNC_IN)
Wait for In this state, the counter GLOB_CNT starts counting bytes after PTS. If the PTS arrives before SYNC_IN, the state START is associated with this new PTS and the global counter GLOB_CNT is reset to the value -2. This operation is repeated in the subsequent states. When SYNC_IN arrives, move to the next state (HEADER),
There, a valid frame header (signal LDHEAD given by DFA) is awaited. In this transition (transition 3), the counter BYTE_CNT is reset and the bit count value NBITS in that byte is recorded in BIT_REG in order to recognize the synchronization at the bit level in the next frame. In state HEADER, the counter GLOB_CNT is treated as described above, and in addition the bit BSTART is counted, which signals the start of a byte and increments the byte counter BYTE_CNT.

When LDHEAD arrives, RS leaves state HEADER and goes to state FINDFMT, where the frame format is checked. In the course of the transition, the decoded logic output HD_DEC_LOGIC (CW) of the control word CW is loaded into the register NBYTES_REG. If such an output value is 0, the output is a number indicating a free-form frame (f_f in the figure), and if its value is different from 0, then such output is the corresponding number of bytes in the frame. Is. If the frame is a fixed frame

[Equation 1] , Or in the case of a free-form frame when the frame length is known, i.e. when it is synchronously locked at the bit level indicated by a_s_in in the figure,
RS leaves state FINDFMT and moves to sync check state SYNCCHK (transition 8). Pad bytes PADBYTES for free format
Fewer BYTE_CNT values are loaded into NBYTES_REG and BYTE_CNT is set to zero. Bit BSTART should only be counted in subsequent frames, so if bit BSTART is reached then state ENDFMT may be entered.
In the process of this transition, the operation described above with respect to BYTE_CNT is performed. In state ENDFMT, the counter BYTE_CNT is incremented.

State SYNCCHK is the normal operating state of this logical network. In this state, the end of the byte count in the frame (e_o__) with the arrival of the sync byte of the next frame (signal SYNC_IN given by DFA).
c) is awaited. When e _ o _ c arrives, a register (FLAG _ RE) is only charged to remember such events.
The value 1 is loaded into G). If both e_o_c and SYNC_IN are reached, the sync lock activation (S
YNCOUT = 1) is shown. If this is the first lock actuation, RS proceeds to state NMUTES where the number of silent frames to be sent is determined and sent to the output unit (connection 22 in FIG. 3). Obviously, this number is obtained by dividing the value counted by GLOB_CNT by the number of bytes in the frame. If it is not the first lock actuation (SYNC_REG = 1), the device remains in state SYNCCHK (transition 10a).

If the bit BSTART arrives while the logical network is cycling through state SYNCHCK, state EN
Move to DCHK. This transition does not require any other conditions. if
If e_o_c (end of count) has arrived but SYNC_IN has not arrived, it means that the upstream unit that supplies data is in use, and this device remains in state SYNCCHK (transition 10b). . By the first SYNC_IN being reached (route to NMUTES) or SYNC_IN not being reached but new bytes

[Equation 2] Is reached, this state changes. If this second case happens, synchronization will be lost. If the sync lock has already been done in the previous frame,
The device moves to state RST and registers the event in the register SYNCLOST_RE
Remember in G. Otherwise, move to state START.

FIG. 8 shows the structure of the output unit UP (FIG. 3). It includes a data output register RPD for serial transmission of output data, a logic network LC3 for managing this unit, and a logic network LC4 for generating control signals to LC3. The operating time of the circuit in the UP depends on the data sampling rate, the signal CLK22 or CLK24
Is determined by Register RPD is a shift register that operates as a parallel-to-serial converter (eg, has 16 positions if the data is sent in 16-bit words). Depending on the oversampling factor, the data must be output only once, or 2, 4, or 8 times, so the register is advantageously cyclic and must be reloaded each time. Avoid not becoming.

The logical network LC3 controls the loading of data into the RPD and the sending of these data by the RPD to the connection 21a of the connections 21, based on the signals received from LC4. In addition, it also sends a command WS to change the channel at the end of each word sent, on line 21b, based on the signal received from LC4, to connect the indicated signal BCLK at the correct moment when the downstream unit takes output data. Send to. If the silence signal MUTE provided by IS via connection 12f of connection 12 is active, or for the number of frames determined by the signal NMUTES present on connection 22, LC3 will replace data. For example, an instruction is given to send a silent frame consisting of a median value.

The logic network LC4 obtains the signals LD, SHIFT and TWS from the count value of the 7-bit down counter DCNT. These signals allow the management network LC3 to command the loading of data into the register RPD, the shifting of data, and the switching of output channels. Output data oversampling factor (signal OSFAC. Set during the programming phase.
It is given by IS and can take the values 1, 2, 4, or 8. ), These signals are generated. In particular, (A) When oversampling with a factor of 8,
128 bits are sent out (one of all counting steps of DCNT), a) the signal SHIFT is active throughout the counting cycle of DCNT (from 127 to 0), and b) when DCNT reaches the value 1, That is, if the instructions TWS and LD are generated following the last bit (with respect to the output signal) and (B) oversampling by a factor of 4,
64 bits are sent (one of all other counting steps of DCNT), a) signal SHIFT is activated at all other steps of counting DCNT, b) last bit to be sent According to, that is,
When DCNT reaches the value 2, instruction TWS is issued, and c) When LDCNT reaches the value 1, instruction LD is issued.

The same principle is adopted for the case of oversampling factors 2 and 1. That is, shifting is performed every 4 (8) steps of counting DCNT, TWS is sent out according to the next of the last bit (and thus when DCNT counts 4 or 8 respectively), and DCNT is LD is always generated when 1 is reached. The signal sent by LC4 in case of oversampling factor 8 or 4 is shown in FIG.
It is also shown in Figures A and 9B. Figure 9 for completeness
A also indicates the bits sent by the signals WS and RPD. Those skilled in the art can easily implement the logical operation as described above. In fact, when the three most significant bits of the DCNT count are 0, an AND operation is performed between the OSFAC and the three least significant bits of the DCNT count to generate LD, and the OSFAC value and the four DCNT counts are Perform EX-OR operation between the least significant bits and TW
It is clear that generating S is sufficient. The management unit LC3 is a state machine that provides four operating states. These are WAIT, MUTE, SKIP, ACTIVE and their respective loading states (WLOAD, MLOAD, SLOA
D, LOAD).

The state WAIT is a state in which the start of output is awaited. In this state, the unit UP sends a silent signal corresponding to silence and waits for the loading instruction LD to arrive. When the loading command LD arrives, a check is made as to whether a silent signal (signal CH) is being sent out on the two channels and whether the START signal has arrived. If both START and CH are reached,
The logical network checks the availability of the number of silent frames NMUUTES that should be sent out and considers the elapsed time for PTS.
Recognize. This information is the signal LD transmitted on connection 22.
Communicated by the unit RS (Fig. 3) using NMUTES.
This connection 22 also conveys the value NMUUTES to UP. If LDNMUTES is present and the number NMUTES is different from 0, the device is in state MLOA.
Move to D, then to state MUTE, where a silent frame is sent out. This transition occurs if the data is in memory M3 (FIG. 3). This is the signal DRGN
Represented by T. If NMUUTES is 0, IS (Fig. 3)
Depending on whether or not the external silence signal MUTE given by is present, the apparatus goes to state WLOAD or LOAD. If the signal LDNMUTES is not present, the system goes (through SLOAD) to state SKIP. State SKIP is similar to WAIT,
It will be explained later. If no data is available

(Equation 3) , The same transition is made.

In state MUTE, transmitted frames are counted backwards until NMUTES equals zero. If no samples are available when these frames have been sent

[Equation 4] , UP goes from state MUTE to state SKIP (via SLOAD). If the sample is available, if an external silence signal
If MUTE is active, the device enters the wait state WAIT (WLOA
Return (through D), else go to state ACTIVE through state LOAD. In the ACTIVE state, if it is a stereo transmission and if the same data is loaded and transmitted on both channels for mono transmission, signal samples are transmitted by regularly switching between data loading and transmission for the left and right channels. . If there is insufficient data in this case, the device goes to state SKIP and if the signal MUTE becomes active, the device goes to state WAIT as already mentioned for state MUTE. Finally, the state SKIP
Is a synchronization maintenance state, and if there is not enough data to be sent, this device is in a state to move. In this state, silent frames are sent, but consider that each frame replaces data. Therefore, once data is available, the number of frames to be sent must be reduced in conclusion.

The above actions are also described in Appendix II, which contains a table of states and a list of actions to be taken for each state or transition. The state diagram is not shown graphically, as it cannot be understood in practice if the number of possible transitions from one state to another is large. Regarding the appendix itself, it is appropriate to emphasize the correlation with FIG. 8 and explain some operations. In particular, (1) term DA
TASR and ROL (DATASR) respectively indicate the register RPD and the cyclic bit shift in it, and (2) RDYMUTES is the above-mentioned value NMUT.
ES availability, (3) SKIP_CNT shows the counter of the number of samples used in the state SKIP, (4) SAMPLES
_CNT indicates a down counter for the number of samples of the frame transmitted on each channel. Each frame is layer I
It will be recalled that there are 384 samples for (as indicated by signal LAY12) and 1152 (ie 3 x 384) samples for layer II. Therefore, the counter is initialized to the value 383. Considering this, the condition for LAY12 at transitions 5,14,19,30 is 3
A block of 84 samples is counted twice in layer I stereo transmission, once in monaural transmission, and in layer II six and three times respectively, (1) OB
Is a signal indicating the format of the output data (corresponding to VFOB in FIG. 5), and (2) PTSF is a signal indicating that the transmitted data is related to the PTS stamp and thus the device SAV can start the function (M3 in FIG. 3). Related to the data given by.)
Is.

The preceding description has been given only by way of non-limiting example and changes and modifications can be made without departing from the scope of the invention.

[0042]

[Table 1]

[0043]

[Table 2]

[0044]

[Table 3]

[0045]

[Table 4]

[0046]

[Table 5]

[0047]

[Table 6]

[Brief description of drawings]

FIG. 1 is a schematic diagram of an MPEG decoder.

FIG. 2 is a structural diagram of packets and frames.

FIG. 3 is a functional block diagram of the speech decoder of the present invention.

FIG. 4 is a block diagram of an audio / video synchronization management circuit.

FIG. 5 is a block diagram of an audio / video synchronization management circuit.

FIG. 6A is a logical state diagram of an audio / video synchronization management circuit.

FIG. 6B is a logical state diagram of the audio / video synchronization management circuit.

FIG. 7 is a state diagram of a synchronous search / inspection circuit.

FIG. 8 is a block diagram of an output unit.

FIG. 9A is a time diagram of some signals generated by an output unit.

FIG. 9B is a time diagram of some signals generated by an output unit.

[Description of sign]

DMP MPEG standard coded audio / video stream decoder SA source (remote encoder) DS system decoder DA audio signal decoder DV video signal decoder CN controller TV video terminal TA audio terminal PLH pack layer header SH system header PKT1. ． ． PKTn packet sequence PHD packet header PDA packet data PSC packet start code (3 bytes) SID stream identification (1 byte) PL packet length (2 bytes) HDA for packing (variable length byte) TS timing indication (group of bytes) FRi frame FHD frame header SYW sync word CW control word AUS voice sample CRC error detection word AND auxiliary data M1 input buffer memory IS interface RS sync search / inspection unit AS voice packet parser FD correction unit (feedback circuit) DFA voice stream decoder M2 output buffer UP output unit GT timing signal generation unit SAV audio / video synchronization management unit CLK24 clock signal SCLK Lock signal CN1 Input counter ST1 Subtractor R1 register FN Digital filter DAC1 Digital-analog converter DAC2 Digital-analog converter VCO1 Voltage controlled oscillator VCO2 Voltage controlled oscillator SCR System clock reference (first timing signal) SCLK System clock signal PTS Output time Stamp (second timing signal) DIFF Difference signal CLK22 Clock signal UOF Operating unit ML1 Multiplier SM1 Adder RM Filter memory register DV1 Divider DV2 Divider ST2 Subtractor RU Output register PX Exclusive OR gate LC1 Logical network LC2 Logical network LC3 Logical network LC4 Logical network DCNT Down counter RPD Data output register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Andrea Huino Tetsuro Italy 10136 Settsuimo Torinese, Via Via Gobettii 3 (72) Inventor Maurizio Paolini Italy 15048 Valenzua (Aer), Via Trieste 11

Claims (4)

[Claims] 1. A decoder for an audio signal belonging to an audio / video stream digitally encoded according to the ISO / IEC 1172 standard.
(DA) such a voice signal is inserted in a packet containing a packet header and a data word, the packet header having a first group of service words, the data word being composed of voice signal samples, The samples are inserted into the frame, the frame includes a frame header with a preset number of voice samples and a second group of service words, the decoder (DA) is (1) voice packets and programming and synchronization. An external unit (DS, which manages information on the system layer of the above standard)
Interface means (IS) for receiving from (CN), (2) Receive the packet from the interface means (IS), recognize the normality of the configuration and the normality of the sequence of the service words of the first group, and include the data contained in the packet. When the output time stamp (PTS) of the packet is recognized in the service word of the first group, the parser (AS) of the voice packet, which sends those data to the subsequent unit, (3) the data of the packet from the parser (AS) Means for decoding an audio stream (DFA), which receives the content of a word and decodes it using a second group of service words, (4) a parser (AS) and an audio stream decoding means (DF)
Means (RS) for retrieving and checking the synchronization of the audio data based on the information given by A), (5) an output unit (UP) for giving the decoded data to the digital-analog conversion means It is possible to output data at different sampling rates derived from at least the first and second master frequencies, the first master frequency being the internal clock signal (C) for the components of the decoder (DA).
LK24) is also used to generate the above output unit
(UP), the decoder (DA) further includes means (SAV) for managing audiovisual synchronization, and the means (SAV) includes (A)
A first timing signal (SCR) provided by the interface means (IS) that determines the time for decoding and outputting the video signal
And a second timing signal (PTS), taken from the stream of audio samples and consisting of the same output time stamp, is begun to output the audio signal, and (a) the first
Or the sampling rate derived from the second master frequency respectively, the first or second for normal output of the audio signal.
A feedback circuit that independently generates clock signals (CLK24, CLK22), includes a digital filter (FN), and operates to minimize the difference between the first timing signal (SCR) and the second timing signal (PTS). The audio signal decoder (DA), characterized in that these clock signals are controlled by using the first clock signal for audio signal output to match the internal clock signal of the decoder (DA). 2. The means for managing audiovisual synchronization (SAV)
(1) means (ST1) for performing the comparison between the first and second timing signals (SCR, PTS) and giving a signal (DIFF) representing the difference between the signals, (2) with a low-pass filter Yes, the pole, zero and gain of which are digital filters (FN) programmable via the interface means (IS), if the value of the difference signal (DIFF) given by the comparison means (ST1) is The digital filter (FN), which filters this difference signal (DIFF) if it is within the set range, and which also gives an error signal when enabled by the data output unit (UP),
(3) First and second phase locked loops including first and second voltage controlled oscillators (VCO1, VCO2), respectively,
The voltage controlled oscillators (VCO1, VCO2) are controlled by the error signal via the respective digital-analog converters (DAC1, DAC2) and, depending on the desired sampling rate, the first or second data output. Clock signal (CLK24, CLK22)
The first and the second to respectively generate and send to the output unit (UP)
The decoder of claim 1 including a phase locked loop. 3. A digital filter (FN) converts an error signal corresponding to a median value of the preset range into a digital-analog converter (DAC) in an initialization step of a decoder (DA).
Decoder according to claim 1, characterized in that it is applied to (1, DAC2). 4. An output unit (UP) comprising: (1) a data output register (RPD) for serially transmitting decoded samples on a decoder output, (2) sample loading and said register (RPD). Synchronous signal (BCLK) to control delivery and for sample reading by user device
First logical network (CL3) for generating (3)
The first logic network generates signals (LD, SHIFT, TWS) for controlling data loading and shifting, and output channel switching based on the data oversampling factor included in the second group of service words. It is a second logical network (LC4) to be given to (LC3), and these signals (LD, SHIFT, TWS) are derived by processing the output signal of the counter (DCNT), and the counter (DCN)
Decoding according to claim 1, characterized in that the counting capacity of T) is equal to the capacity of the register (RPD) multiplied by the maximum value of the oversampling factor, the second logical network (LC4). vessel.