KR19980036075A - PCR Signal Generator in System Encoder - Google Patents

Abstract

The present invention relates to an apparatus for generating a PCR signal having a predetermined bit length, which is inserted into a transmission packet in a system encoder and referred to as a reference time for stream decoding. To this end, the present invention provides an apparatus for operating a system encoder. System clock generating means for generating a set system clock of several tens of MHz; A first counter initialized according to a reset signal from an external source and counting an extended bit of a predetermined length by increasing a bit count of a predetermined length by one according to a generated system clock; Compares the count value from the first counter with a reference value of a predetermined bit, and generates a carry signal when the count value and the reference value coincide with each other as a result of the comparison, and simultaneously performs PCR extension (PCR_ext) bit value of the counted bit. A comparator for generating a; A second counter initialized according to a reset signal from an external source and counting a generated carry signal to generate a PCR base (PCR_base) bit value of a predetermined bit; First logic means for outputting the generated PCR base (PCR_base) bit value in synchronization with the generated system clock; And a predetermined length preset by synthesizing the PCR clock (PCR_ext) bit value, the additional bit value of the predetermined length, and the PCR base (PCR_base) bit value by synchronizing with the system clock generated when the PCR request signal is input from the system encoder. Second logic means for generating a PCR signal.

Description

PCR Signal Generator in System Encoder

The present invention relates to a system encoder, and more particularly, to a program clock reference (hereinafter abbreviated as PCR) representing a time reference value for a program in a transport stream in an MPEG-2 system encoder. The present invention relates to a PCR signal generator in a system encoder.

As is known, the MPEG-2 transport stream is a kind of MPEG system stream, and the conventional technology for the MPEG system is as known in the MPEG-2 International Standard (IS), which is now defined as an international standard. 2 is the official name of ITU-T Rec.H.222.0 | ISO / IEC 13818.

Here, MPEG-2 is technically divided into three parts, that is, the system of the first part, the video of the second part, and the audio of the third part, and the first part is divided into system layer coding. Recommendations for the overall field. In this case, system layer coding (hereinafter, system coding) is suitable for transmission or storage by multiplexing not only an audio / video stream compressed by the data compression method of MPEG-1 or MPEG-2, but also user data as needed. It relates to a technique for formatting.

In this way, the process of receiving a plurality of bit streams from the system encoder at the transmitting side and formatting them into a series of streams is called a system encoder, and the formating from the system decoder at the receiving side is solved in the form of the original input stream. The process of producing is called system decoder. In addition, the rules for formatting the bit stream in the system encoder are called syntax, and the meaning of each part in the process of creating the syntax is called semantics.

Therefore, the MPEG system IS prescribes syntax and semantics, which are formatting rules. Therefore, when encoding in a system encoder on the transmitting side, a bit stream must be created according to these rules. It should be configured to be able to decode

In this case, the encoding in the system encoder not only combines and combines the audio / video streams, but also the buffer control in the system decoder and the synchronization of the decoded streams in the process of decoding the stream in the system decoder on the receiving side. It involves the process of inserting some parameters to play back in time.

There are two types of encoding methods in such a system encoder, a transport stream encoding and a program stream encoding, wherein the transport stream encoding is mainly used for transport and the program stream is mainly used for storage. The invention relates in particular to the generation of PCR signals in transport stream encoding.

1 is a schematic block diagram of a system stream generator for generating a packetized transport stream in an MPEG-2 system. As shown in the figure, the system stream generator comprises an audio encoder 102, an audio packetizer 104, a video encoder 106, a video packetizer 108, a PS multiplexer 110 and a TS multiplexer ( 112).

Referring to FIG. 1, the audio and video encoders 102 and 106 encode digital signals converted into audio and video signals at predetermined compression rates by applying separate encoding techniques suitable for their information characteristics. Although it may be assumed to be 1 or MPEG-2, MPEG-2 system encoding does not exclude streams encoded with encoders other than the MPEG family, so only H.261 video encoders, CCITT G.721 audio encoders, or specifically limited users. It can be a unique audio / video encoder that you use for the purpose.

At this time, the data encoded by these audio and video encoders 11 and 12 is called an elementary stream, and these audio and video elementary streams primarily refer to the respective audio and video packetizers 104 and 108. Each packet is packetized. The data that has undergone this process is called a packetized elementary stream (PES), and the packetizer that makes this PES packet is called a PES packetizer.

Thus, each audio PES packet and video PES packet produced by the audio packetizer 104 and the video packetizer 108, respectively, are provided to the PS multiplexer 110 and the TS multiplexer 112, respectively, resulting in the PS multiplexer. At 110, the PS stream is generated, and at the TS multiplexer 112, the TS stream is generated and output.

In other words, system encoding refers to a process of receiving an elementary stream and generating a PES packetizing and transport stream. In other words, the system coding process can be divided into two functions, namely, PES packet and TS / PS multiplexing.

The PES packetizer makes elementary streams into PES packets, and the TS / PS multiplexing process corresponds to a process of creating TS / PS packets from PES packets.

As such, the MPEG-2 system recommendation does not specify a special encoding process for decoding, and there is no separate provision for various application systems that may occur as needed.

Therefore, in the encoding system, the output stream needs to provide an accurate stream that meets the decoder specification defined by the MPEG-2 stream IS. In this encoding process, the method of configuring an encoder and the technology for making an efficient decoder are not standardized. not.

Meanwhile, as described above, when generating a TS / PS, a transport packet includes a PCR value indicating a time reference value for a program (a stream in which audio and video streams are multiplexed so that the decoder can decode them in synchronization with each other) in a transport stream. Is generated and inserted, and this PCR must be retransmitted to the system decoder within a few m seconds (e.g., 0.1 seconds), regardless of the audio / video start code. After stabilization, the actual elementary stream is decoded.

Therefore, in view of the above, it can be deemed that there is an urgent need for the emergence of a PCR generator capable of more accurately matching the system clock for stable decoding in a decoder system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide a PCR signal generator in a system encoder capable of minimizing a decoding time delay of an encoded elementary stream by using a system clock for generating a PCR signal. There is this.

In order to achieve the above object, the present invention generates a transmission packet by packetizing audio and video data coded at a predetermined compression rate by a packet unit of a predetermined length, and inserted into each generated transmission packet to provide a criterion for stream decoding. An apparatus for generating a PCR signal having a predetermined bit length referred to as time, comprising: system clock generating means for generating a predetermined tens of MHz system clock required for the operation of a system encoder; A first counter initialized according to a reset signal from an external source and counting an extended bit of a predetermined length by increasing a bit count of a predetermined length by one according to a system clock from the system clock generating means; Comparing a count value from the first counter with a reference value of a predetermined bit, and generating a carry signal when the input count value and the reference value match, as a result of the comparison, PCR extension of the predetermined bit counted (PCR_ext) A comparator for generating a bit value; A second counter initialized according to a reset signal from an external source and counting the generated carry signal to generate a PCR base (PCR_base) bit value of a predetermined bit; First logic means for outputting the generated PCR base (PCR_base) bit value of the predetermined bit in synchronization with the generated tens of MHz system clock; And synchronizing with the generated system clock when a PCR request signal is input from the system encoder, thereby adding a PCR extended (PCR_ext) bit value from the comparator, an additional bit value of a predetermined length, and the first logic means. Provided is a PCR signal generator in a second logic means system encoder for generating a PCR signal of a predetermined length by logically combining a PCR base (PCR_base) bit value.

1 is a schematic block diagram of a system stream generator for generating a packetized transport stream in an MPEG-2 system;

2 is a block diagram of a system encoder suitable for applying a PCR signal generator according to the present invention.

3 is a block diagram of a PCR signal generator in a system encoder according to a preferred embodiment of the present invention.

4 is a timing chart showing the relationship between a transport stream, PCR, clock, and time.

<Description of the code | symbol about the principal part of drawing>

202,208 A / D Converter 204 Audio Encoder

206,212: buffer 210: video encoder

214: system encoder 218: PCR generator

220: clock divider

302: system clock generator 304: first counter

306: comparator 308: second counter

310: first combinational logic 312: second combinational logic

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 shows a block diagram of a system encoder suitable for applying the PCR signal generator according to the present invention.

As shown in the figure, the system encoder includes two analog / digital (A / D) converters 202 and 208, an audio encoder 204, two buffers 206 and 212, a video encoder 210 and a system encoder 214. , A system clock generator 216, a PCR generator 218, and a clock divider 220.

Referring to FIG. 2, the audio encoder 204 and the video encoder 210 are substantially corresponding to the audio encoder 102 and the video encoder 106 of FIG. 1 as compared to FIG. 1 already described above, and the system Encoder 214, system clock generator 216, PCR generator 218, and clock divider 220 are the transport stream generation blocks of FIG. 1, i.e., audio packetizer 104, video packetizer 108, and The part corresponding to the TS multiplexer 112.

First, the A / D converter 202 converts an input audio signal into a digital signal, and converts an analog audio signal based on a sampling frequency according to a sampling clock fs a provided from a clock divider 220 to be described later. The digital audio signal is converted into a digital signal, and is encoded at a predetermined compression rate while referring to an audio frame sync (sync a) from the clock divider 220 described later through the audio encoder 204. The elementary stream output at encoder 204 is stored in buffer 206.

Similarly, the A / D converter 208 converts the input video signal into a digital signal and converts the analog video signal based on the sampling frequency according to the sampling clock fs v provided from the clock divider 220 described later. The digital video signal is converted into a digital signal, and is encoded at a predetermined compression rate while referring to the video frame sync (sync v) from the clock divider 220 described later through the video encoder 204. The elementary stream output at encoder 210 is stored in buffer 212.

Here, two buffers 206 and 212 are used for synchronizing between elementary streams when generating a transport stream TS for an audio signal and a video signal through packetizing.

Next, the system encoder 214 inserts the PCR generated by the PCR generator described later according to the present invention (i.e., inserts it into the header of the transmission packet) on a transport stream if necessary at a predetermined time. This means that there must be a reference time in order to decode the stream encoded by the decoder at the receiving side. This value is transmitted in the form of PCR data format, that is, the system encoder 214 transmits a PCR-inserted transport stream generated according to the present invention. Is output to a transmission channel not shown.

On the other hand, the system clock generator 216 in the dotted block generates a stable system clock of 27MHz to provide to the PCR generator 218 and the clock divider 220 to be described later, the system clock frequency generated at this time is the following equation 1 Must meet the conditions.

[Equation 1]

27 MHz-810 Hz ≤ system_clock_frequency ≤ 27 MHz + 810 Hz

Time change rate of system clock frequency ≤75 × 10 ^-3 Hz / sec

In the meaning of Equation 1, the system clock frequency allows an error of +,-810 Hz at 27 MHz, which corresponds to a range of +,-0.003% based on 27 MHz. In addition, even when operating in the range of this error, the clock change should not occur abruptly, which is prescribed by Equation 2 to be described later. This allows up to a change of 0.075 Hz in one second, which means that one clock shift out of 360 M clock if operated at a clock frequency of 27 MHz per second. In summary, Equation 1 defines the operating frequency range of the system clock and the rate of change of the operating frequency.

On the other hand, the PCR generator 218 in the dashed block is substantially a block directly related to the present invention, and the 27 MHz provided by the system clock generator 216 described above when there is a PCR request signal from the system encoder 214 described above. 48-bit PCR field data defined in the MPEG system are generated based on the system clock of the system and provided to the system encoder 214.

In this case, the PCR defined in the MPEG system represents a reference time value for a program in a transport stream, and this reference value is calculated as in Equation 2 described later. Here, a program is a set of program elements (elementary streams) having the same reference time. In general, a program means a stream in which audio streams and video streams are multiplexed and decoded to be synchronized with each other at a decoder.

[Formula 2]

PCR_base (i) = (System_Clock_Frequency × t (i) DIV300)% 2 ³³

PCR_ext (i) = (PCR_base (i) × t (i) DIV1)% 300

PCR (i) = PCR_base (i) × 300 + PCR_ext (i)

(DIV is a truncation operation that makes the remainder zero with an integer division operation, and% is a modulo operation that takes the remainder.)

In Equation 2, i denotes the i-th byte, and t (i) is the time when the i-th byte is input to the system target decoder, and this time value is defined as the system_clock_frequency satisfying the constraint of Equation (A). Create by sampling Here, the system target decoder refers to a virtual decoder model in the MPEG system, which is intended to be described based on a conceptual model in the process of defining a system standard.

In this process, the PCR consists of a 33-bit PCR_base expressed in 90KHz units (system clock_frequency / 300) and 9 bits of PCR_ext expressed in 27 MHz units (system_clock_frequency).

In addition, i in PCR (i) means the last byte of PCR_base data, and this PCR (i) indicates the time when the last byte of PCR_base data is input to the system target decoder as system_clock_frequency.

The format of PCR data defined in MPEG is 48 bits and is composed of three fields as follows.

program_clock_reference_base33 bit

reserved6 bits

program_clock_reference_extension9 bit

As described above, the PCR data is composed of 6 bytes. The reserved data of 6 bits is a meaningless value, and the program_clock_ reference_base has the same format as the SCR (System Clock Reference) representing the system clock in MPEG-1. In the MPEG-2 system, this configuration is for compatibility with MPEG-1.

On the other hand, since the time is sampled at the system clock frequency in the process of making a PCR generated according to the present invention and inserted into the header portion of the transmission packet, the time between each sample corresponds to the inverse of the sampling frequency. Since the sampled time value is represented by 42 bits, the meaning of an integer value of one unit represented by 42 bits corresponds to the sampling interval, and since 42 bits determine the operating range, the range of time that can be expressed as PCR is 0 seconds. * Is the maximum value (maximum integer that can be taken by PCR expressed in 42 bits) in seconds. However, when the PCR reaches the maximum value from 0, it is a modular operation that becomes 0 again. Therefore, the maximum value of this time will not need to be greatly conscious.

As can be seen from Equation 2 above, the PCR value is calculated as frequency * time, so the result is a unitless constant, where frequency is the system clock frequency and time is the first byte of time t (i). Means.

In addition, in Equation 2, t (i), that is, the time corresponding to the i-th byte, indicates the time corresponding to the i-th byte when the time of the 0th byte is 0 (that is, t (0) = 0). For example, if a transport_rate (transport rate of a transport stream) is a value expressed in byte / sec units, it corresponds to (1 / transport_rate) seconds. A timing chart showing a general relationship to these is shown in FIG. 4, which will be more clearly understood by referring to the transport stream portion and the time portion in FIG.

4, one clock length of a transport stream corresponds to (1 byte) seconds, which corresponds to 1 / transport_rate sec. At this time, in the transport stream, PCR (a) and PCR (b), as mentioned above, are composed of PCR_base, PCR_ext, and PCE_reserved, and PCR (a) is PCR_base of PCR (a), which is the a-th byte. PCR represents the t (a) which is the time when the last byte of the data portion PCR_base_field is input to the system target decoder. Similarly, PCR (b) can be considered in the same concept. In addition, the process represented by PCR consists of PCR_base which can be expressed in units of 90KHz and PCR_ext which represents 90KHz and the remaining time in 27MHz.

Thus, the difference between the time t (a) corresponding to the a th byte of the transport stream and the time t (b) corresponding to the b th byte is (ba) / transport_rate, which is shown in FIG. Likewise, it can be thought of as being divided into PCR_base * 300, which corresponds to PCR_base, and PCR_ext, which is the remainder. As a result, t (a) + (b-a) / transport_rate.

Meanwhile, in the above-described Equation 2, the PCR value is separately calculated by PCR_base and PCR_ext, where PCR_base is a value expressed in units of system_clock_frequncy / 300, PCR_ext is expressed in PCR_base and the remaining time is expressed in units of system_clock_frequncy (27MHz). Is a value. Therefore, if the PCR value is calculated in the unit of the system clock frequency, it is PCR_base * 300 + PCR_ext. The reason why PCR is divided and calculated is that 90 MHz of system clock reference (SCR), which functions as the PCR of MPEG-2 in MPEG-1 (ISO / IEC 11172) system, corresponds to 1/300 of MPEG-2 system clock frequency. This is for the purpose of providing compatibility with this MPEG-1 system.

That is, when MPEG-2 video elementary streams and MPEG-2 audio elementary streams are transmitted as MPEG-2 transport streams, and a receiver decodes a program using an MPEG-1 system decoder or an MPEG-1 video / audio decoder. The MPEG-1 system decoder sees only the PCR_base portion of the PCR portion of the MPEG-2 transport stream and treats it as if it were an SCR of MPEG-1.

In addition, since the MPEG-2 audio / video elementary streams are each compatible with the MPEG-1 audio / video stream, the MPEG-2 stream can be decoded by the MPEG-1 decoder. Therefore, assuming that the system clock frequency is a fixed value of 27 MHz, the frequency corresponding to 1/300 thereof is 90 KHz, and the relationship of the clock corresponding thereto is shown in detail in the lower part of FIG.

Therefore, in the above-described process, the system_clock_frequncy * t (i) is divided by 300 to take only an integer value (DIV300 operation), and the modular operation of 2 ³³ is performed to express the binary 33 bits in PCR_base. Is an integer value from the value of system_clock_frequncy * t (i) (DIV 1 operation) and the operation of modular 300 is expressed as 9 bits. As a result, PCR is calculated with the value of PCR_base * 300 + PCR_ext which sums them.

As described above, a detailed operation of generating the PCR signal defined in the MPEG system through the PCR generator 218 using the system clock will be described later in detail with reference to FIG. 3.

Referring back to FIG. 2, the clock divider 220 divides the 27 MHz system clock provided from the system clock generator 216 described above, and the audio and video sampling clocks fs_a and fs_v and the audio and video frame sinks. sync_a and sync_v, respectively, and the generated audio and video sampling clocks fs_a and fs_v are provided to the aforementioned A / D converters 202 and 208, respectively, and the generated audio and video frame syncs sync_a and sync_v are Provided to an audio encoder 204 and a video encoder 210, respectively.

Next, the PCR signal generator according to the present invention applicable to the system encoder having the above-described configuration will be described in detail.

3 is a block diagram of a PCR signal generator in a system encoder according to a preferred embodiment of the present invention.

As shown in the figure, the PCR signal generator of the present invention comprises a system clock generator 302, a first counter 304, a comparator 306, a second counter 308, a first combinational logic 310 and The second combinational logic 312 is included. Here, the system clock generator 302 corresponds to the system clock generator 216 shown in FIG. 2, and performs a substantially identical function, i.e., 27 MHz used to generate a PCR signal to be generated according to the present invention. Generate a system clock.

Referring to FIG. 3, first, when the operation of the system encoder 214 shown in FIG. 2 is started, both the first and second counters 304 and 308 are set to 0 by a reset signal from the outside. That is, the reset signal provided from the outside becomes a signal indicating the start of operation of the system encoder 214 shown in FIG.

In the present invention, the modular 300 9-bit counter is used as the first counter 304 and the 33-bit counter is used as the second counter 308, which synchronizes the synchronization between the PCR_base clock (90 KHz) and the PCR_ext (27 MHz) clock. To finish.

On the other hand, the first counter 304 is set to 0 at the next clock when the value starts at 0 and reaches a value of 299, and counts the 27 MHz system clock provided by the system clock generator 302 described above, where the count is counted. The output value, i.e., the output value counted in relation to 9 bit unit PCR_ext, is provided to the comparator 306 every system clock.

Next, the comparator 306 outputs the above-described output value from the first counter 304 to the second combinational logic 312, and at the same time the 9-bit binary value (reference value) for 299 and the first counter 304. Compares the input values provided from the input signal, and generates a carry signal at the time when the preset reference value 100101011 is equal to the input value from the first counter 304, and transmits one pulse to the second counter 308. to provide. At this time, the output value provided from the comparator 306 to the second combinational logic 312 is a bit value in the extension (PCR_ext) portion of the PCR signal.

On the other hand, like the first counter 304 described above, the second counter 308 is initialized by an externally reset signal, and the count value is increased by one each time a carry is input from the comparator 306 described above. Here, the counted value, that is, a count value (PCR_base related bit value in 33 bit units) counting the number of 9 bits of PCR_ext according to the carry signal is provided to the first combinational logic 310, and the first combinational logic. In 310, the output value of the second counter 308 is synchronized with the system clock provided by the system clock generator 302 described above, and then output to the second combinational logic 312.

On the other hand, in the second combinational logic 312, the 9-bit PCR_ext related count value provided from the above-described comparator 306, the reserved bits in 6-bit unit and the first combinational logic 308 described above. The 33-bit PCR_base related count value is combined and synchronized with the system clock from the system clock generator 302 described above to generate and store a new 48-bit PCR value. At this time, the previously generated PCR value is discarded. This operation is performed in synchronization with the system clock every system clock.

Therefore, the second combinational logic 312 generates PCR values (48 bits of field data) through the above-described process, and the generated PCR values are obtained by the PCR request signal from the system encoder 214 of FIG. When received, it is sent to the system encoder 214, and the system encoder 214 writes the corresponding PCR signal generated according to the present invention, referred to as a reference time for stream decoding at the receiving decoder, to a transport stream, i.e., a transport packet. It is inserted in the header part of.

As described above, according to the present invention, by using the system clock to generate the PCR signal in the system encoder, it is possible to minimize the decoding time delay when decoding the elementary stream encoded by the system decoder.

Claims (3)

Packetizing audio and video data coded at a predetermined compression rate in units of packets of a predetermined length to generate a transmission packet, and inserted into each of the generated transmission packets and having a predetermined bit length PCR signal referred to as a reference time for stream decoding. In the device for generating, System clock generating means for generating a predetermined several tens of MHz system clock required for the operation of the system encoder; A first counter initialized according to a reset signal from an external source and counting an extended bit of a predetermined length by increasing a bit count of a predetermined length by one according to a system clock from the system clock generating means; Comparing a count value from the first counter with a reference value of a predetermined bit, and generating a carry signal when the input count value and the reference value match, as a result of the comparison, PCR extension of the predetermined bit counted (PCR_ext) A comparator for generating a bit value; A second counter initialized according to a reset signal from an external source and counting the generated carry signal to generate a PCR base (PCR_base) bit value of a predetermined bit; First logic means for outputting the generated PCR base (PCR_base) bit value of the predetermined bit in synchronization with the generated tens of MHz system clock; And When the PCR request signal is input from the system encoder, the generated system clock is synchronized with the PCR extension (PCR_ext) bit value from the comparator, an additional bit value of a predetermined length, and the PCR from the first logic means. Second logic means for generating a PCR signal having a predetermined length by logically combining a base (PCR_base) bit value; PCR signal generator in a system encoder. The apparatus of claim 1, wherein the system clock has a category that satisfies the following condition when its frequency is 27 MHz. 27 MHz-810 Hz ≤ system_clock_frequency ≤ 27 MHz + 810 Hz Time change rate of system clock frequency ≤75 × 10 ^-3 Hz / sec The PCR signal according to claim 1 or 2, wherein the PCR signal is composed of a PCR base (PCR_base) bit value in units of 33 bits, an additional bit value in units of 6 bits, and a PCR extension (PCR_ext) bit value in units of 9 bits. PCR signal generator in a system encoder.