JPH08272076A - Production of printed wiring board - Google Patents

Abstract

PURPOSE: To provide a printed wiring board having excellent circuit width accuracy. CONSTITUTION: A through-hole distribution is digitized by an area coefft. and a pattern correction value is calculated from a correlative relation between the area coefft. and a plating thickness distribution. The through-hole distribution 1a, the design plating thickness 1b and base material copper foil thickness 1c are determined at the time of designing the printed wiring board. Next, the surface of laminated plates is divided into plural regions and the area coeffts. 2 are calculated for the respective regions from the through-hole distribution 1a. The actual plating thickness 3 is estimated from the area coeffts. 2 and a circuit width deviation 5 is estimated from the base material copper foil thickness 1c. Further, the pattern correction value 6 is calculated and an etching resist is formed by using a photomask corrected by this pattern correction value 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board in which a circuit is formed on a laminate having through holes by plating.

[0002]

2. Description of the Related Art In a method of manufacturing a printed wiring board by a so-called subtractive method in which a panel plating is performed after a hole is formed to form a through hole and a circuit is formed by etching, a highly reliable printed wiring board is manufactured by etching. It is essential to improve the circuit width accuracy of the circuit formed by. Since higher density of the printed wiring board is realized by making the circuit finer, higher density requires higher accuracy. In order to improve the circuit width accuracy, etching resist material
Investigations are being conducted in various fields such as etching resist developing devices, etching solutions, and etching devices. The plating thickness distribution also has a great influence on the circuit width accuracy. The circuit in the thick plating portion becomes thick and the circuit in the thin plating portion becomes thin. Therefore, in order to improve the circuit width accuracy, it is necessary to make the plating thickness distribution uniform. In order to make the plating thickness distribution uniform, improvements have been made by examining the plating solution composition, brightener component, current density, plating tank, plating jig structure, etc., but this is not complete. However, since there is a correlation between the plating thickness and the circuit width, if the distribution of the plating thickness can be known, the accuracy of the circuit width can be improved by correcting the pattern width of the photomask used for forming the etching resist. It will be possible. A method of correcting the pattern width of the photomask, which is reported in Japanese Patent Laid-Open No. 56-64493, will be described below.

(1) 500 × 5 using a normal plating device
Applying 40μm copper plating to a 00mm stainless steel plate,
When the plating film is peeled off and the copper plating thickness distribution is measured by the weight method, the results shown in FIG. 7 are obtained.

(2) The thickness of the copper plating and the amount of dimensional change of the circuit due to etching are calculated in advance as shown in FIG. 8 to obtain the result shown in FIG.

(4) In order to cancel the amount of dimensional change shown in FIG. 9, pattern width correction as shown in FIG. 10 is performed at each position of the photomask.

[0006]

In electrolytic copper plating, the outer shape of each printed wiring board, particularly the distribution of through holes, affects the distribution of plating thickness. Considering the area of the hole wall of the through holes, even if the areas are apparently the same area, the area to be plated is larger in the area having many through holes than in the area having few through holes. Therefore, the plating thickness of the portion having many through holes is thinner than that of the portion having few through holes. In the above-mentioned conventional technique, a substrate having no through hole is plated, the plating thickness of each region is measured, and a correction value is derived from the correlation between the plating thickness and the circuit width. This method is based on the assumption that there is no difference in the external shape of each printed wiring board, and it depends on the process or equipment specific factors such as plating solution composition, brightener component, current density, plating tank, plating jig structure, etc. The distribution of the resulting plating thickness is corrected. Therefore, there is a problem in that the distribution of the plating thickness caused by the difference in the pattern of each printed wiring board cannot be corrected and the circuit width accuracy cannot be improved.

An object of the present invention is to provide a method for manufacturing a printed wiring board, which can correct the distribution of the plating thickness caused by the difference in the pattern of each printed wiring board and can improve the circuit width accuracy.

[0008]

A method of manufacturing a printed wiring board according to the present invention comprises a step of forming a through hole in a laminated board, a step of plating to form a conductor layer and a through hole in the laminated board, and In a method for manufacturing a printed wiring board, which comprises a step of forming an etching resist using a photomask in a conductor layer and a through hole formation region, and a step of forming a circuit by etching, the step of forming the etching resist is It is divided into a plurality of regions of the laminated plate determined by the hole distribution, the design plating thickness, and the base copper foil thickness, and calculated from the area coefficient numerically calculated by the through hole distribution for each of the divided regions. It is characterized by including the step of forming the etching resist by using the photomask corrected by the corrected pattern correction value.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a perspective view of a laminated board used in the first embodiment of the present invention, and FIGS. 2 (a), 2 (b) and 2 (c) are shown in FIG.
It is a graph which shows the plating thickness between A and B, a circuit width, and a pattern correction value. In the first embodiment of the present invention, as shown in FIGS. 1 and 2 (a), the plating thickness of the region 1 where the through holes are dense is thin, and the plating thickness of the region with few or no through holes is large. Has been formed. Therefore, when a circuit is formed, as shown in FIG. 2B, the circuit width becomes large in the thick plating region and becomes small in the thin plating region. In order to suppress such a circuit width distribution, pattern width correction is applied to a photomask used when forming a resist. The pattern correction value as shown in FIG. 2C can be calculated if the plating thickness distribution of the target laminated plate can be obtained, but the plating thickness distribution differs depending on the through hole distribution of each individual laminated plate. It is not practical in terms of delivery time and man-hours to obtain the plating thickness distribution for all the manufactured laminated plates in order to calculate the pattern correction value. In this embodiment, the through-hole distribution is digitized by the area coefficient,
The pattern correction value is calculated from the correlation between the area coefficient and the plating thickness distribution. As a result, a pattern correction value can be obtained for each individual laminated plate at the time of design.

FIG. 3 is a flowchart showing the flow of the method for calculating the pattern correction value. When designing a printed wiring board, as shown in FIG. 3, first, (1a) through-hole distribution, (1b) design plating thickness, and (1c) base copper foil thickness of the laminate are determined. Next, the laminated plate is divided into a plurality of regions, and the area coefficient (2) is calculated from the (1a) through hole distribution for each region. Next, (3) actual plating thickness is estimated from the area coefficient, and (1c) base copper foil thickness is added to this to calculate (4) conductor thickness. Next, (4) the circuit width deviation is estimated from the conductor thickness, and (6) the pattern correction value is calculated. A more detailed description will be given below.

(1a) Through hole distribution: Determined when the printed wiring board is designed. It is information such as the position of the through hole of the laminate and the through hole.

(1b) Design plating thickness: The design plating thickness (hereinafter referred to as TS) is determined by the thickness of the target laminate, the minimum through hole diameter, and the throwing power of the plating process to be applied. In this example, the plating process as shown in Table 1 was applied. When the plate thickness is 5.0 mm and the minimum cutting diameter is 0.3 mm, TS = 60 μm.

[0014]

[Table 1]

(1c) Base copper foil thickness: Base copper foil thickness (hereinafter,
The thickness of TK) is often 18 μm, but it is difficult to form a circuit with a laminated plate having a large set plating thickness, and therefore it is necessary to make it as thin as possible. Here, a copper foil with TK = 9 μm was used.

(2) Area coefficient: In order to quantify a local area, an area coefficient (hereinafter referred to as A) is introduced as an actual area per unit area. When a laminated plate having a plate thickness of tmm is divided into a lattice having a length of L1 mm and a width of L2 mm and there are Nn hole diameters Dnmm through holes in a certain lattice, the area coefficient is calculated by the following equation.

A = L1 × L2 × 2 + Σ (3.14 × Nn
× (Dn × t−Dn × Dn / 4) / L1 × L2 × 2 Area coefficient is a value obtained by dividing (apparent area × area of through-hole hole wall−through-hole cross-sectional area) by apparent area. Become. Even with the same through hole distribution, in the case of a laminated plate having a large plate thickness, the area of the hole wall of the through hole becomes large and the area coefficient becomes large. The area coefficient of the portion where there is no through hole is 1.00, but for example, the area coefficient of a region in which through holes of 0.4 mm are arranged in a 1.27 mm grid on a laminated plate having a plate thickness of 5.0 mm is 2 It becomes .91.

(3) Plating thickness: The correlation between the area coefficient (A) and the plating thickness (hereinafter referred to as TM) is obtained in advance by an experiment. FIG. 4 is a graph showing the correlation between the area coefficient and the plating thickness obtained by the experiment. Table 1
An average of 60 using the plating solution and plating equipment as shown in
As a result of investigating the correlation between the area coefficient and the plating thickness by plating with a thickness of μm and dividing the laminated plate by a grid of 40 mm square, the correlation as shown in FIG. 4 was obtained. The area of one section is 1,
Since a good correlation was obtained between the area coefficient and the plating thickness in the case of 000 to 4,000 mm ² , the area of one section is divided on the laminated plate so as to fall within this range. For each of the divided regions, the plating thickness is calculated using (2) area coefficient calculated from the correlation shown in FIG.

(4) Conductor thickness: Conductor thickness (hereinafter referred to as H)
Is calculated by adding the base copper foil thickness and the plating thickness. H = (T
(K + TM) / (TK + TS) (5) Circuit width: The conductor thickness (H) and the circuit width (hereinafter referred to as W) are previously obtained by an experiment. FIG. 5 shows the conductor thickness obtained by the experiment. 3 is a graph showing the correlation between the circuit width and the circuit width. Etching solution as shown in Table 2
As a result of investigating the correlation using a circuit pattern having a width of 100 μm using an etching apparatus, the result shown in FIG. 5 was obtained. When the plating thickness is 80 μm, the circuit width becomes 100 μm. When the plating thickness is less than 80 μm, the circuit width is less than 100 μm and the plating thickness is 80 μm.
If it is larger than μm, the circuit width is also larger than 100 μm. For each of the divided regions, the circuit width is calculated using (4) conductor thickness calculated from the correlation shown in FIG.

[0020]

[Table 2]

(6) Pattern correction value: The pattern correction value (hereinafter referred to as ΔP) cancels out the circuit width distribution calculated above. That is, it is calculated by ΔP = 100−W.
With respect to each of the divided regions, the pattern width of the photomask is corrected using the calculated ΔP, an etching resist is formed using this photomask, and etching is performed. When a laminated plate having a plate thickness of 3.0 mm and a circuit width accuracy of ± 30 μm in the conventional manufacturing method is manufactured by the manufacturing method according to this embodiment, the circuit width accuracy is ± 10 μm.

FIG. 6 is a plan view showing a correction target area and a correction calculation area according to the second embodiment of the present invention. In the calculation of the area coefficient (2) of the first embodiment, the area to be corrected and the area for calculating the correction value are considered as different areas. For example, divide the laminated plate with a grid of 2 cm, and divide into 2 c
The m-square area is set as a correction target area, and the correction value is calculated as a 5-cm square area including the correction target area and its periphery. As shown in FIG. 6, the correction value for the correction target area 2 is calculated by the correction value calculation area 3, and the correction value of the correction target area 4 adjacent to the correction target area 2 is calculated by the correction value calculation area 5. To do. Since the correction value calculation region 3 and the correction value calculation region 5 have overlapping portions, the area coefficient values calculated by the respective regions do not differ greatly. Therefore, the correction values of the adjacent areas change stepwise, and the step difference of the circuit that occurs when the difference between the correction values of the adjacent areas is large is eliminated. Since it is necessary to divide the correction target area on the printed wiring board without any gaps, it is common to divide it into a grid, but the correction value calculation area is not limited to a rectangle but a circle if the correction target area is the center. Etc. are applicable.

According to the conventional method for manufacturing a printed wiring board, a laminated board having a circuit width accuracy of ± 50 μm and a plate thickness of 5.0 mm is manufactured by the method for manufacturing a printed wiring board according to the present embodiment. It was 10 μm.

[0024]

As described above, according to the present invention, the step of forming a hole in a laminated plate, the step of forming a conductor layer and a through hole by plating, the step of forming an etching resist using a photomask, and the etching In a method for manufacturing a printed wiring board including a step of forming a circuit by processing,
By using a photomask whose pattern width is corrected by the area coefficient of each region of the laminated plate in the process of forming the etching resist, the circuit width accuracy is ± 50 μm from the conventional value.
There is an effect that it can be increased to 10 μm.

[Brief description of drawings]

FIG. 1 is a perspective view of a laminated board used in a first embodiment of the present invention.

2A, 2B, and 2C are graphs showing the plating thickness, circuit width, and pattern correction value between FIGS. 1A and 1B.

FIG. 3 is a flowchart showing a flow of a method of calculating a pattern correction value.

FIG. 4 is a graph showing a correlation between an area coefficient and a plating thickness obtained by an experiment.

FIG. 5 is a graph showing a correlation between a conductor thickness and a circuit width obtained by an experiment.

FIG. 6 is a plan view showing a correction target area and a correction calculation area according to a second embodiment of the present invention.

FIG. 7 is a plan view showing a distribution of copper plating thickness according to an example of a conventional printed wiring board manufacturing method.

FIG. 8 is a graph showing a correlation between copper plating thickness and dimensional change according to an example of a conventional printed wiring board manufacturing method.

FIG. 9 is a plan view showing a size distribution of a circuit according to an example of a conventional printed wiring board manufacturing method.

FIG. 10 is a plan view showing an example of a correction value of a photomask pattern according to a conventional method for manufacturing a printed wiring board.

[Explanation of symbols]

 1 Area where through holes are densely located 2,4 Correction target area 3,5 Correction value calculation area

Claims (1)

[Claims] 1. A step of forming a through hole in a laminated plate, a step of plating to form a conductor layer and a through hole in the laminated plate, and an etching resist using a photomask in the conductor layer and the through hole formation region. A step of forming
In the method for manufacturing a printed wiring board, which comprises a step of forming a circuit by etching, the step of forming the etching resist includes through hole distribution, design plating thickness,
It is divided into a plurality of regions of the laminated plate which are determined by the thickness of the base copper foil, and each of the divided regions is corrected by a pattern correction value calculated from the area coefficient quantified by the through hole distribution. A method of manufacturing a printed wiring board, comprising the step of forming the etching resist using the formed photomask.