JP2782576B2 - Method of forming conductive circuit - Google Patents

Method of forming conductive circuit

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Publication number
JP2782576B2
JP2782576B2 JP5282136A JP28213693A JP2782576B2 JP 2782576 B2 JP2782576 B2 JP 2782576B2 JP 5282136 A JP5282136 A JP 5282136A JP 28213693 A JP28213693 A JP 28213693A JP 2782576 B2 JP2782576 B2 JP 2782576B2
Authority
JP
Japan
Prior art keywords
layer
conductive
circuit
forming
electroless plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5282136A
Other languages
Japanese (ja)
Other versions
JPH07115257A (en
Inventor
信 勝亦
秀則 山梨
均 牛島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yazaki Corp
Original Assignee
Yazaki Sogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yazaki Sogyo KK filed Critical Yazaki Sogyo KK
Priority to JP5282136A priority Critical patent/JP2782576B2/en
Publication of JPH07115257A publication Critical patent/JPH07115257A/en
Application granted granted Critical
Publication of JP2782576B2 publication Critical patent/JP2782576B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、回路体パターンを絶縁
性基板上に形成した、パワー回路用等の電流容量を必要
とする回路に適当な導電回路の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a conductive circuit suitable for a circuit requiring a current capacity, such as a power circuit, in which a circuit pattern is formed on an insulating substrate.

【0002】[0002]

【従来の技術】従来より、回路板は各種電子機器に対
し、電子部品を実装した交換可能な素子として、あるい
は電子部品を相互に接続するものとして用いられてい
る。このような回路板は、一般に、絶縁性基板上に銅の
回路体パターンが形成されており、特に、フレキシブル
基板上に回路体パターンが形成されたものにあっては、
機器類の小型化等に対応した、例えば狭隘な空間にも配
置でき、従って装着自由度が向上するため、近年多用さ
れている。
2. Description of the Related Art Conventionally, a circuit board has been used for various electronic devices as a replaceable element on which electronic components are mounted or as a device for interconnecting electronic components. Such a circuit board generally has a copper circuit pattern formed on an insulating substrate, and in particular, a circuit pattern formed on a flexible substrate,
It has been widely used in recent years because it can be arranged in, for example, a narrow space corresponding to miniaturization of devices and the like, and thus has a higher degree of freedom in mounting.

【0003】ところで、回路体パターンを形成するに
は、基板上の全面に例えば、銅箔を接着するなどの方法
で形成し、所望の回路体パターンに対応した画像のスク
リーンでレジスト剤を印刷し皮膜で覆われていない領域
の銅をエッチングにより取り去り、最後にレジスト剤を
除去して形成する方法がある。
In order to form a circuit pattern, a copper foil is formed on the entire surface of the substrate by, for example, bonding a copper foil, and a resist is printed on a screen having an image corresponding to a desired circuit pattern. There is a method in which copper in a region that is not covered with a film is removed by etching, and finally, a resist agent is removed to form copper.

【0004】[0004]

【発明が解決しようとする課題】上記の方法にて回路体
パターンを形成する場合、銅箔のエッチング速度と生産
性の兼ね合いより、一般的に25μm程度の銅箔が用い
られ、厚くとも75μmが限界である。そのため、従来
の回路体は信号回路や微小な電流回路等に用いられ、電
流容量を必要とするパワー回路等に用いることが出来な
かった。
When a circuit pattern is formed by the above-mentioned method, a copper foil of about 25 μm is generally used, and a thickness of 75 μm at most is used in view of a balance between the etching rate of copper foil and productivity. It is the limit. Therefore, the conventional circuit body is used for a signal circuit, a minute current circuit, or the like, and cannot be used for a power circuit or the like that requires a current capacity.

【0005】そこで、銅箔回路にさらに電解メッキをし
て電解メッキ層を積層し、厚膜の回路を得ることも可能
であるが、この様な厚膜回路を形成した場合、図8に示
すとおり、厚膜回路20には、銅箔22上の電解メッキ
層23の端部23aにドックボーンと呼ばれる盛り上が
りが出来てしまい、後加工としてのカバーレイがしづら
くなって回路体の作成が困難となる。なお、図中の符号
21は絶縁基板を示している。
[0005] Therefore, it is possible to obtain a thick film circuit by further electrolytic plating the copper foil circuit and laminating an electrolytic plating layer, but when such a thick film circuit is formed, it is shown in FIG. As described above, in the thick-film circuit 20, a bulge called a dock bone is formed at the end 23a of the electrolytic plating layer 23 on the copper foil 22, and it is difficult to form a circuit body by making it difficult to form a coverlay as a post-process. Becomes Reference numeral 21 in the drawing indicates an insulating substrate.

【0006】本発明の目的は、回路体パターンを安価に
かつ均質な厚膜の導電層にて形成し良好な導電回路を形
成することにある。
An object of the present invention is to form a good conductive circuit by forming a circuit body pattern at a low cost and using a uniform thick conductive layer.

【0007】[0007]

【課題を解決するための手段】本発明に係る上記目的
は、絶縁基板上に電解メッキの下地となる層を所定間隔
に複数並設した後、電解メッキ浴に浸漬し前記下地とな
る層に通電して電解メッキ層を該下地層のエッジ部で盛
り上がるように厚膜に析出させることで互いに隣接する
前記下地層を前記電解メッキ層により連通して所定
回路体パターンを形成することを特徴とする導電回路の
形成方法によって達成される。
SUMMARY OF THE INVENTION The object of the present invention is to provide a method and a method for arranging a plurality of layers as bases for electroplating on an insulating substrate at predetermined intervals, and then immersing the layers in an electroplating bath to form the base layers. Apply current to build up the electrolytic plating layer at the edge of the underlayer.
Adjacent to each other by depositing on a thick film so that it rises
This is achieved by a method of forming a conductive circuit, wherein a circuit pattern having a predetermined width is formed by connecting the underlayer with the electrolytic plating layer .

【0008】[0008]

【作用】所定間隔を隔てて複数並設された電解メッキの
下地となる層に電解メッキを厚膜に形成した際、ドッグ
ボーン効果により下地層のエッジの部分に集中的にメッ
キ層が析出する。そこで、互いに隣接する下地層が、析
出するメッキ層の集中を相互に引っ張って平坦化させ均
質な回路体を得る。従って、従来のように電解メッキに
よる厚膜作成時に発生するドッグボーンが抑制され、回
路体の凹凸がなくなり、後加工の絶縁処理が容易にでき
る。また、電解メッキの下地層は、導電性ペーストや無
電解メッキの触媒を含むペーストやトナーであり高価な
ものである。従って、上記した電解メッキの下地となる
層を所定間隔を隔てて複数並設させることにより、下地
層の使用量が半減し製造コストの低減が可能となる。
When a thick layer of electrolytic plating is formed on a plurality of underlying layers of electrolytic plating at predetermined intervals, the plating layer is concentrated on the edges of the underlying layer by the dogbone effect. . Therefore, the underlying layers adjacent to each other pull flatten the concentration of the deposited plating layer to obtain a uniform circuit body. Therefore, a dog bone generated at the time of forming a thick film by electrolytic plating as in the related art is suppressed, the unevenness of the circuit body is eliminated, and the post-processing insulation can be easily performed. The base layer for electrolytic plating is a paste or toner containing a conductive paste or a catalyst for electroless plating, and is expensive. Therefore, by arranging a plurality of layers serving as bases for the above-described electrolytic plating at predetermined intervals, the amount of the base layers used can be reduced by half, and the manufacturing cost can be reduced.

【0009】[0009]

【実施例】次に、本発明の導電回路の形成方法の実施例
を、図面を参照しながら詳細に説明するが、本発明はこ
れに限定されるものでない。図1〜図4は、本発明の導
電回路の形成方法の一実施例を回路製作工程順に示した
回路断面図である。図4において、本発明に係る導電回
路10は、絶縁基板1上に電解メッキの下地となる導電
性ペーストの印刷層2、電解メッキ層3、および絶縁層
4が順次積層されて回路体パターンを形成する。
Next, an embodiment of a method for forming a conductive circuit according to the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto. 1 to 4 are circuit sectional views showing one embodiment of a method for forming a conductive circuit according to the present invention in the order of circuit manufacturing steps. In FIG. 4, a conductive circuit 10 according to the present invention has a printed circuit layer 2, a conductive plated layer 3, and an insulating layer 4 of a conductive paste to be a base for electrolytic plating on an insulating substrate 1 in order to form a circuit pattern. Form.

【0010】図1に示すとおり、印刷層2は狭幅に形成
され、かつ、所定間隔2dをもって複数並設されるとと
もに、並設された全体幅eが所望の導電回路の回路体パ
ターン幅aより細幅に設定されている(図3参照)。そ
して、電解メッキは導電性ペーストの印刷層2に通電す
ることにより、図2に示すようにドッグボーン効果によ
り、導電性ペーストのエッジ部が盛り上がるように電解
メッキ層3を析出する。さらに、電解メッキ層3は、図
3に示すように導電性ペーストの印刷層間で互いに引っ
張られ、ドッグボーン効果を見越した厚膜bとなり、各
導電性ペーストの印刷層2を連通するように形成され、
所定の回路体幅aとなるように導電性ペーストの印刷層
2上に被着される。
As shown in FIG. 1, a plurality of printed layers 2 are formed in a narrow width, and a plurality of printed layers 2 are juxtaposed at a predetermined interval 2d, and the juxtaposed overall width e is a circuit pattern width a of a desired conductive circuit. The width is set to be narrower (see FIG. 3). Then, in the electroplating, when a current is applied to the printed layer 2 of the conductive paste, the electroplated layer 3 is deposited so that the edge of the conductive paste is raised by the dog bone effect as shown in FIG. Further, as shown in FIG. 3, the electroplating layer 3 is pulled between the printed layers of the conductive paste to form a thick film b in anticipation of the dogbone effect, and is formed so as to communicate the printed layers 2 of the respective conductive pastes. And
The conductive paste is applied on the printed layer 2 so as to have a predetermined circuit width a.

【0011】ちなみに、本発明者等が実験したところ、
導電性ペーストの厚さを30μm、細幅cを500μm
に設定し、厚膜bが200μmとなるように銅の電解メ
ッキ層3を設けた場合、導電性ペーストの印刷層2より
210μm程度銅メッキ層3が幅広に析出することを確
認した。また、回路体幅aと導電性ペーストの印刷層2
の細幅cとの関係は、概ね、下記数式に示すような結果
が得られることを見出した。
Incidentally, when the present inventors conducted experiments,
The thickness of the conductive paste is 30 μm, and the narrow width c is 500 μm.
When the electrolytic plating layer 3 of copper was provided so that the thick film b was 200 μm, it was confirmed that the copper plating layer 3 was deposited to be wider than the printed layer 2 of the conductive paste by about 210 μm. In addition, the circuit body width a and the conductive paste printed layer 2
It has been found that the relationship with the narrow width c can generally be obtained as shown in the following formula.

【0012】[0012]

【数1】a=n(c+2d) d=(1.0〜1.2)b なお、n≧2、c≧印刷層の印刷精度の限界(塗料によ
って異なる。通常、十数μm以上)
A = n (c + 2d) d = (1.0-1.2) b Note that n ≧ 2, c ≧ the limit of printing accuracy of the printing layer (depending on the paint, usually more than tens of μm)

【0013】しかし、上記数式の成立は、電解メッキ液
の種類が大きな要因となって変化する。なお、回路体幅
aや厚膜bは、必要とする電気容量に対して相違するも
のである。導電性ペーストによる印刷層の形成には、一
般的なスクリーン印刷が適用できる。絶縁層4は回路体
パターンを覆い回路体を保護するもので、絶縁性のフィ
ルムを接着するか絶縁性のペーストを均一に塗布するこ
とにより設けられる。
However, the establishment of the above equation varies depending on the type of the electrolytic plating solution. The circuit width a and the thick film b are different from the required electric capacity. General screen printing can be applied to the formation of the print layer using the conductive paste. The insulating layer 4 covers the circuit pattern and protects the circuit, and is provided by bonding an insulating film or uniformly applying an insulating paste.

【0014】図5は、本発明に係る導電回路の形成方法
を、さらに具体的に示した工程図である。導電回路10
は、先ずCADにより回路設計が行われ、所定の回路体
パターンが形成された後、この回路体パータンに応じた
スクリーンを作成して形成される。このスクリーンを用
いて、絶縁基板となるフィルム上に回路体パターンの印
刷層2がスクリーン印刷される。スクリーン印刷により
形成された印刷層2の形態が、図1に対応して示してあ
る。次いで、この印刷層2を乾燥硬化した後、電解メッ
キ浴に浸漬し電解メッキ層3を厚膜に析出させる。
FIG. 5 is a process diagram more specifically showing a method of forming a conductive circuit according to the present invention. Conductive circuit 10
First, a circuit is designed by CAD, a predetermined circuit pattern is formed, and then a screen corresponding to the circuit pattern is created. Using this screen, a printed layer 2 of a circuit pattern is screen-printed on a film to be an insulating substrate. The form of the printing layer 2 formed by screen printing is shown corresponding to FIG. Next, after drying and curing the printed layer 2, the printed layer 2 is immersed in an electrolytic plating bath to deposit the electrolytic plated layer 3 in a thick film.

【0015】以上に述べた回路体パターンの形態が、図
3に対応して示してある。そして、最後に、導電回路1
0は絶縁層4が形成された後、絶縁基板1を所定形状に
打抜き成形して形成される。なお、上記実施例では、電
解メッキの下地となる銅箔の回路を導電性ペーストの印
刷により設けるとして述べたが、これに代わって、本発
明は、例えば蒸着等の方法により絶縁基板上の全面に設
けた銅箔をエッチング処理して形成し、これに電解メッ
キを行う場合にも当然適用できる。
The form of the circuit pattern described above is shown corresponding to FIG. And finally, the conductive circuit 1
No. 0 is formed by punching the insulating substrate 1 into a predetermined shape after the insulating layer 4 is formed. In the above embodiment, the circuit of the copper foil serving as the base of the electrolytic plating is described as being provided by printing of a conductive paste. However, instead of this, the present invention employs, for example, a method of vapor deposition or the like on the entire surface of the insulating substrate. The present invention is also applicable to a case where the copper foil provided in the above is formed by etching and electrolytic plating is performed on the copper foil.

【0016】次に、本発明の他の実施例を図6を参照し
て説明する。この実施例では、電解メッキの下地層とし
て銅箔の代わりに、無電解メッキの触媒を添加したペー
ストを用いて下地層としている。すなわち、導電回路1
0Aは、絶縁基板1に、無電解メッキの触媒を添加した
ペーストの印刷層2Aをスクリーン印刷にて形成した
後、これを銅の無電解メッキ浴に浸漬することで無電解
メッキ層5が析出される。このとき、無電解メッキ層5
の厚みは僅かでよく、例えば印刷層2A上に均一に2μ
m程度析出されれば充分である。次いで、先の実施例と
同様の加工により、無電解メッキ層5に電解メッキ層3
の厚膜を電解メッキ浴に浸漬通電することで析出させた
後、絶縁層4を設けて導電回路10Aが形成される。
Next, another embodiment of the present invention will be described with reference to FIG. In this embodiment, instead of a copper foil, a paste to which a catalyst for electroless plating is added is used as a base layer for electrolytic plating. That is, the conductive circuit 1
0A is a method in which a printed layer 2A of a paste to which an electroless plating catalyst is added is formed on the insulating substrate 1 by screen printing, and this is immersed in a copper electroless plating bath to deposit the electroless plated layer 5. Is done. At this time, the electroless plating layer 5
May have a small thickness, for example, a uniform 2 μm on the printed layer 2A.
It is sufficient if about m is deposited. Next, the electroless plating layer 3 is applied to the electroless plating layer 5 by the same processing as in the previous embodiment.
Is deposited by immersion current in an electrolytic plating bath, and then an insulating layer 4 is provided to form a conductive circuit 10A.

【0017】図7は、本発明のさらに他の実施例を示し
ている。この実施例では、電解メッキの下地層が無電解
メッキの触媒を添加したトナーを写真技術で現像して設
けられている。すなわち、絶縁基板1上に、無電解メッ
キの触媒を添加したトナー6を正電荷パターンに沿って
現像した後、これを銅の無電解メッキ浴に浸漬すること
により無電解メッキ層5を、無電解メッキの触媒を添加
したトナー6上に均質に析出させる。次いで、導電回路
10Bは、先の図6に示した実施例と同様、無電解メッ
キ層5を電解メッキ浴に浸漬通電することで、この無電
解メッキ層5に電解メッキ層3の厚膜を析出させた後、
絶縁層4を形成して設けられる。
FIG. 7 shows still another embodiment of the present invention. In this embodiment, the underlayer for electrolytic plating is provided by developing a toner to which a catalyst for electroless plating is added by photographic technology. That is, a toner 6 to which an electroless plating catalyst has been added is developed along the positive charge pattern on the insulating substrate 1 and then immersed in a copper electroless plating bath to form the electroless plating layer 5. It is uniformly deposited on the toner 6 to which the catalyst for electrolytic plating is added. Next, as in the embodiment shown in FIG. 6, the conductive circuit 10 </ b> B immerses the electroless plating layer 5 in the electrolytic plating bath and applies a current to the electroless plating layer 5 to thereby form a thick film of the electrolytic plating layer 3 on the electroless plating layer 5. After precipitation
The insulating layer 4 is formed and provided.

【0018】[0018]

【発明の効果】以上述べたように、本発明に係る導電回
路の形成方法によれば、導電回路は、電解メッキの下地
となる層を所定間隔に複数並設することにより、下地と
なる高価な材料の使用量を低減することができるととも
に、厚膜に施す電解メッキにおいて、従来技術に観られ
たドッグボーンは、隣接する複数並設した下地層間で互
いに引っ張られて平坦化した電解メッキ層を形成し、後
加工による絶縁処理の障害となることなく、絶縁処理を
容易にして導電回路を形成できる。
As described above, according to the method for forming a conductive circuit according to the present invention, the conductive circuit is formed by arranging a plurality of layers which are the bases for electrolytic plating at predetermined intervals, thereby increasing the cost of the bases. In the electroplating applied to a thick film, the dog bone seen in the prior art is a flattened electroplating layer that is pulled from each other between a plurality of adjacent underlayers. And a conductive circuit can be formed by facilitating the insulating process without obstructing the insulating process by the post-processing.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例による導電回路の形成方法を
示す、第1工程図での回路断面図である。
FIG. 1 is a cross-sectional view of a circuit in a first process diagram illustrating a method of forming a conductive circuit according to an embodiment of the present invention.

【図2】本発明の一実施例による導電回路の形成方法を
示す、第2工程図での回路断面図である。
FIG. 2 is a circuit cross-sectional view in a second process diagram showing a method for forming a conductive circuit according to one embodiment of the present invention.

【図3】本発明の一実施例による導電回路の形成方法を
示し、第3工程図での回路断面図である。
FIG. 3 is a cross-sectional view illustrating a method of forming a conductive circuit according to an embodiment of the present invention in a third process diagram.

【図4】本発明の一実施例による導電回路の形成方法を
示し、最終工程図での回路断面図である。
FIG. 4 is a cross-sectional view illustrating a method of forming a conductive circuit according to an embodiment of the present invention, which is a final process diagram.

【図5】本発明の一実施例を具体的に示す工程図であ
る。
FIG. 5 is a process chart specifically showing one embodiment of the present invention.

【図6】本発明の他の実施例による導電回路の形成方法
を示す、回路断面図である。
FIG. 6 is a circuit sectional view showing a method of forming a conductive circuit according to another embodiment of the present invention.

【図7】本発明のさらに他の実施例による導電回路の形
成方法を示す、回路断面図である。
FIG. 7 is a circuit cross-sectional view illustrating a method of forming a conductive circuit according to still another embodiment of the present invention.

【図8】従来例を示す導電回路の回路断面図である。FIG. 8 is a circuit sectional view of a conductive circuit showing a conventional example.

【符号の説明】[Explanation of symbols]

10,10A,10B 導電回路 1 絶縁基板 2 印刷層 3 電解メッキ層 4 絶縁層 5 無電解メッキ層 6 トナー 10, 10A, 10B conductive circuit 1 insulating substrate 2 printing layer 3 electrolytic plating layer 4 insulating layer 5 electroless plating layer 6 toner

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭61−179593(JP,A) 特開 昭59−153891(JP,A) 特開 昭54−126959(JP,A) 特公 昭36−4873(JP,B1) (58)調査した分野(Int.Cl.6,DB名) H05K 3/10 - 3/24,3/38──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-179593 (JP, A) JP-A-59-153891 (JP, A) JP-A-54-126959 (JP, A) 4873 (JP, B1) (58) Field surveyed (Int. Cl. 6 , DB name) H05K 3/10-3/24, 3/38

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板上に電解メッキの下地となる層を所
定間隔に複数並設した後、電解メッキ浴に浸漬し前記下
地となる層に通電して電解メッキ層を該下地層のエッジ
部で盛り上がるように厚膜に析出させることで互いに隣
接する前記下地層を前記電解メッキ層により連通して
の回路体パターンを形成することを特徴とする導電
回路の形成方法。
[Claim 1] After several juxtaposed serving as a base layer of electrolytic plating on the substrate a predetermined distance, the electrolytic plating layer of underlayer by energizing the layer serving as the underlayer was immersed in the electrolytic plating bath edge
Next to each other by depositing on a thick film so that it rises in the area
The method for forming a conductive circuit, characterized in that the base layer to form a circuit element pattern of Tokoro <br/> constant width communicated by the electrolytic plating layer in contact.
【請求項2】 前記下地となる層が、導電性ペーストを
印刷にて所定間隔に複数並設されたものである請求項1
記載の導電回路の形成方法。
2. A method according to claim 1, wherein a plurality of said base layers are arranged at predetermined intervals by printing a conductive paste.
A method for forming the conductive circuit according to the above.
【請求項3】 前記下地となる層が、無電解メッキの触
媒を添加したペーストを印刷にて所定間隔に複数並設し
た後、無電解メッキ浴に浸漬し無電解メッキによる導電
層を析出させたものである請求項1記載の導電回路の形
成方法。
3. A method for forming a conductive layer by electroless plating after arranging a plurality of pastes containing a catalyst for electroless plating at predetermined intervals by printing and then immersing the paste in an electroless plating bath. The method for forming a conductive circuit according to claim 1, wherein
【請求項4】 前記下地となる層が、電子写真記録によ
り得られる静電荷パターンを無電解メッキの触媒入りト
ナーで現像することにより所定間隔に複数並設した後、
無電解メッキ浴に浸漬し無電解メッキによる導電層を析
出させたものである請求項1記載の導電回路の形成方
法。
4. The method according to claim 1, wherein a plurality of layers as the base are arranged at predetermined intervals by developing an electrostatic charge pattern obtained by electrophotographic recording with a toner containing a catalyst of electroless plating.
2. The method for forming a conductive circuit according to claim 1, wherein the conductive layer is immersed in an electroless plating bath to deposit a conductive layer by electroless plating.
【請求項5】 回路体パターンを覆って絶縁層が施され
た導電回路体であることを特徴とする請求項1記載の導
電回路の形成方法。
5. The method for forming a conductive circuit according to claim 1, wherein the conductive circuit is provided with an insulating layer covering the circuit pattern.
JP5282136A 1993-10-18 1993-10-18 Method of forming conductive circuit Expired - Lifetime JP2782576B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5282136A JP2782576B2 (en) 1993-10-18 1993-10-18 Method of forming conductive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5282136A JP2782576B2 (en) 1993-10-18 1993-10-18 Method of forming conductive circuit

Publications (2)

Publication Number Publication Date
JPH07115257A JPH07115257A (en) 1995-05-02
JP2782576B2 true JP2782576B2 (en) 1998-08-06

Family

ID=17648583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5282136A Expired - Lifetime JP2782576B2 (en) 1993-10-18 1993-10-18 Method of forming conductive circuit

Country Status (1)

Country Link
JP (1) JP2782576B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7348486B2 (en) 2019-07-25 2023-09-21 日亜化学工業株式会社 Method for manufacturing a light emitting device, light emitting device, wiring board for mounting an element, and method for manufacturing a wiring board for mounting an element

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54126959A (en) * 1978-03-25 1979-10-02 Nippon Mektron Kk Method of producing circuit board
JPS59153891A (en) * 1983-02-17 1984-09-01 Matsushita Electric Ind Co Ltd Process for forming partially plated part on conductive body of printed circuit board
JPS61179593A (en) * 1985-02-04 1986-08-12 藤好 克聡 Manufacture of electric circuit and electric circuit

Also Published As

Publication number Publication date
JPH07115257A (en) 1995-05-02

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