JPH08265079A - Chip filter - Google Patents

Chip filter

Info

Publication number
JPH08265079A
JPH08265079A JP6591895A JP6591895A JPH08265079A JP H08265079 A JPH08265079 A JP H08265079A JP 6591895 A JP6591895 A JP 6591895A JP 6591895 A JP6591895 A JP 6591895A JP H08265079 A JPH08265079 A JP H08265079A
Authority
JP
Japan
Prior art keywords
chip
internal electrode
layer
bare chip
filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6591895A
Other languages
Japanese (ja)
Inventor
Paakaa Baakusu Daanaru
ダーナル・パーカー・バークス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6591895A priority Critical patent/JPH08265079A/en
Publication of JPH08265079A publication Critical patent/JPH08265079A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To mount the filter onto a printed circuit board with high density by providing RC, LC or RLC function to the filter in a very small form of one chip. CONSTITUTION: The chip RC filter 10 is provided with one or two internal electrodes 12 or over, a bare chip 11 made of a ceramic dielectric body formed so that an internal electrode 12 appears to any of both chip ends opposite to each other, a resistance layer 13 provided from the one end to the other end of the surface of the bare chip 11 so as to be opposite via the internal electrode 12 and the ceramic dielectric body, and a couple of terminal electrodes 14, 15 baked to be conductive to one end of the internal electrode 12 and the resistive layer 13 at both ends of the bare chip 11 respectively.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント回路基板の表
面に実装可能なチップ型フィルタに関する。更に詳しく
は低域フィルタ、高域フィルタ、その他のフィルタに適
するチップ型フィルタに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type filter mountable on the surface of a printed circuit board. More specifically, the present invention relates to a chip type filter suitable for a low pass filter, a high pass filter and other filters.

【0002】[0002]

【従来の技術】1950年代の初期から厚膜回路基板は
商業的に製造されてきている。この回路製品はセラミッ
ク基板上にスクリーン印刷によって形成された抵抗体の
ネットワークに基づいていた。この回路の抵抗体は炭素
系の組成であり、導電体はAgであり、基板はアルミナ
又はステアタイトであった。基板をBaTiO3又はこ
れに近い高い比誘電率を有する誘電体で作ると、誘電体
である基板がコンデンサになってRC(抵抗の抵抗値
R、コンデンサの容量C)回路を作り得ることがその後
まもなく見い出された。そして抵抗体パターンをコンデ
ンサ上に位置させれば、連続的に静電容量が変化するた
め、分布した(distributed)RC機能が得られること
が判明した。このRCの分布したネットワークは高周波
フィルタとして有用で別々のRとCの部品より構成され
たフィルタでは得られない特性を有することが明らかに
なった。特筆すべきことは、これらの製品は誘電体のセ
ラミック基板をコンデンサとして用い、表面に形成した
抵抗パターンと基板内部で接続する構造を持つ導電体回
路から構成されていたことである。後に薄膜技術が同様
な目的のために用いられた。例えばRCネットワークを
作るためにTa/Ta25の技術が開発され、Ta25
を誘電体として用い、これらのいくつかは分布したRC
型の機能があった。
BACKGROUND OF THE INVENTION Thick film circuit boards have been manufactured commercially since the early 1950s. This circuit product was based on a network of resistors formed by screen printing on a ceramic substrate. The resistor of this circuit had a carbon-based composition, the conductor was Ag, and the substrate was alumina or steatite. If the substrate is made of BaTiO 3 or a dielectric having a high relative dielectric constant close to BaTiO 3 , the substrate that is the dielectric becomes a capacitor, and an RC (resistance value R of the resistor, capacitance C of the capacitor) circuit can be made thereafter. Soon found. It has been found that if the resistor pattern is placed on the capacitor, the capacitance is continuously changed, so that the distributed RC function can be obtained. It has been found that this RC distributed network has properties that are useful as high frequency filters and cannot be obtained with filters composed of separate R and C components. It should be noted that these products used a dielectric ceramic substrate as a capacitor, and were composed of a resistance pattern formed on the surface and a conductor circuit having a structure for connection inside the substrate. Later thin film technology was used for similar purposes. For example, Ta / Ta 2 O 5 technology was developed to create RC networks, and Ta 2 O 5
As the dielectric, some of these are distributed RC
There was a type feature.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来のR
Cフィルタは誘電体が基板であって、比較的大型である
ため、プリント回路基板に実装するには不適であり、基
板表面実装用のチップ形状をなしていなかった。本発明
の目的は、1チップの極めて小型の形態で、RC、LC
(インダクタのインダクタンスL、コンデンサの容量
C)又はRLC(抵抗の抵抗値R、インダクタのインダ
クタンスL、コンデンサの容量C)の機能を有し、高密
度にプリント回路基板に実装し得るチップ型フィルタを
提供することにある。
However, the conventional R
Since the C filter has a substrate made of a dielectric material and is relatively large, it is not suitable for mounting on a printed circuit board, and has not been formed into a chip shape for surface mounting on a substrate. The object of the present invention is to realize RC, LC in a very small form of one chip.
A chip-type filter having a function of (inductance L of inductor, capacitance C of capacitor) or RLC (resistance value R of resistor, inductance L of inductor, capacitance C of capacitor) and which can be mounted on a printed circuit board at high density is provided. To provide.

【0004】[0004]

【課題を解決するための手段】図1及び図2に示すよう
に、本発明の第1のチップ型RCフィルタ10は、チッ
プ内部に1又は2以上の内部電極12が設けられ、相対
向するチップ両端部のいずれか一端部に内部電極12が
現れるように形成されたセラミック誘電体からなるベア
チップ11と、このベアチップ11の表面の一端部から
他端部にかけて内部電極12と上記セラミック誘電体を
介して対向するように設けられた抵抗層13と、ベアチ
ップ11の両端部に内部電極12の一端部と抵抗層13
にそれぞれ導通するように焼付けられた一対の端子電極
14,15とを備えたものである。
As shown in FIGS. 1 and 2, a first chip-type RC filter 10 of the present invention is provided with one or more internal electrodes 12 inside the chip and face each other. A bare chip 11 made of a ceramic dielectric formed so that the internal electrode 12 appears at either one of both ends of the chip, and the internal electrode 12 and the ceramic dielectric are formed from one end to the other end of the surface of the bare chip 11. The resistance layer 13 provided so as to face each other with one end portion of the internal electrode 12 and the resistance layer 13 provided at both ends of the bare chip 11.
And a pair of terminal electrodes 14 and 15 that are baked so as to be electrically connected to each other.

【0005】図4及び図5に示すように、本発明の第2
のチップ型LCフィルタ20は、チップ内部に1又は2
以上の内部電極22が設けられ、相対向するチップ両端
部のいずれか一端部に内部電極22が現れるように形成
されたセラミック誘電体からなるベアチップ21と、こ
のベアチップ21の表面の一端部から他端部にかけて内
部電極22と上記セラミック誘電体を介して対向するよ
うに設けられたインダクタ層27と、ベアチップ21の
両端部に内部電極22の一端部とインダクタ層27にそ
れぞれ導通するように焼付けられた一対の端子電極2
4,25とを備えたものである。
As shown in FIGS. 4 and 5, the second aspect of the present invention is described.
The chip-type LC filter 20 of the
The above-mentioned internal electrode 22 is provided, and the bare chip 21 made of a ceramic dielectric is formed so that the internal electrode 22 appears at either one end of the opposite ends of the chip, and from the one end of the surface of the bare chip 21 to the other. The inductor layer 27 is provided so as to face the internal electrode 22 toward the end portion through the ceramic dielectric, and both ends of the bare chip 21 are baked so as to be electrically connected to the one end portion of the internal electrode 22 and the inductor layer 27, respectively. A pair of terminal electrodes 2
4 and 25 are provided.

【0006】図7及び図8に示すように、本発明の第3
のチップ型RLCフィルタ30は、チップ内部に1又は
2以上の内部電極32が設けられ、相対向するチップ両
端部のいずれか一端部に内部電極32が現れるように形
成されたセラミック誘電体からなるベアチップ31と、
このベアチップ31の表面の一端部から他端部にかけて
内部電極32と上記セラミック誘電体を介して対向する
ように設けられた抵抗層33と、ベアチップ31の裏面
の一端部から他端部にかけて内部電極32と上記セラミ
ック誘電体を介して対向するように設けられたインダク
タ層37と、ベアチップ31の両端部に内部電極32と
抵抗層33とインダクタ層37にそれぞれ導通するよう
に焼付けられた一対の端子電極34,35とを備えたも
のである。
As shown in FIGS. 7 and 8, the third aspect of the present invention is described.
The chip-type RLC filter 30 is made of a ceramic dielectric material in which one or more internal electrodes 32 are provided inside the chip and the internal electrodes 32 are formed so as to appear at either one of the opposite ends of the chip. Bare chip 31,
The resistance layer 33 is provided so as to face the internal electrode 32 from the one end to the other end of the bare chip 31 via the ceramic dielectric, and the internal electrode from the one end to the other end of the back surface of the bare chip 31. 32, an inductor layer 37 provided so as to face the ceramic dielectric body 32, and a pair of terminals baked on both ends of the bare chip 31 so as to be electrically connected to the internal electrode 32, the resistance layer 33, and the inductor layer 37, respectively. The electrodes 34 and 35 are provided.

【0007】本発明のチップ型フィルタ10〜30は、
湿式積層法又は乾式積層法により作られる。先ず最初に
BaTiO3系又はPb系の誘電体セラミック粉末、有
機バインダ、可塑剤及び有機溶剤を混合して誘電体ペー
スト又は誘電体スラリーを調製する。湿式積層法では、
この誘電体ペーストをカーテンコート法により台板上に
セラミック誘電体層を積層し乾燥した後、この誘電体層
の上に間隔をあけて導電性ペーストをスクリーン印刷し
乾燥することにより内部電極を形成する。内部電極が1
層の場合にはこの上に誘電体ペーストを同様に積層す
る。内部電極を複数層形成する場合には誘電体層と内部
電極の層を交互に繰返して複数回積層する。この積層体
を脱バインダ処理した後、焼成し、この焼結体の表面又
は裏面に抵抗体又はインダクタとなるペーストをスクリ
ーン印刷し乾燥して焼成する。この焼結体を抵抗体又は
インダクタの単位で一端部に内部電極が現れるように焼
結体をチップ状に切断する。得られたベアチップの両端
部に導電性ペーストを塗布し焼付けて一対の端子電極を
形成する。
The chip filters 10 to 30 of the present invention are
It is made by a wet laminating method or a dry laminating method. First, a BaTiO 3 -based or Pb-based dielectric ceramic powder, an organic binder, a plasticizer, and an organic solvent are mixed to prepare a dielectric paste or a dielectric slurry. In the wet lamination method,
This dielectric paste is laminated by a curtain coating method on a ceramic dielectric layer on a base plate and dried, and then a conductive paste is screen-printed on this dielectric layer at intervals and dried to form internal electrodes. To do. 1 internal electrode
In the case of a layer, a dielectric paste is similarly laminated on this. When forming a plurality of internal electrodes, the dielectric layers and the internal electrode layers are alternately repeated and laminated a plurality of times. The laminated body is subjected to binder removal processing and then fired, and a paste serving as a resistor or an inductor is screen-printed on the front surface or the back surface of the sintered body, dried and fired. The sintered body is cut into chips in a unit of a resistor or an inductor so that the internal electrode appears at one end. A conductive paste is applied to both ends of the obtained bare chip and baked to form a pair of terminal electrodes.

【0008】上記チップ型フィルタ10〜30を乾式積
層法で製造するには、上記誘電体スラリーをドクタブレ
ード法等により成膜乾燥してセラミックグリーンシート
を作り、このグリーンシートからなる誘電体層の上に湿
式積層法と同様に内部電極を形成する。内部電極が1層
の場合にはこの上にグリーンシートからなる誘電体層を
同様に積層する。内部電極を複数層形成する場合には誘
電体層と内部電極の層を交互に繰返して複数回積層す
る。以下、湿式積層法と同様に積層体の焼成、抵抗層又
はインダクタ層の形成、焼結体のチップ化を行い、最後
に一対の端子電極を形成する。
In order to manufacture the chip filters 10 to 30 by the dry lamination method, the dielectric slurry is film-dried by a doctor blade method or the like to form a ceramic green sheet, and a dielectric layer made of this green sheet is formed. An internal electrode is formed on the upper electrode similarly to the wet lamination method. When the internal electrode has one layer, a dielectric layer made of a green sheet is similarly laminated thereon. When forming a plurality of internal electrodes, the dielectric layers and the internal electrode layers are alternately repeated and laminated a plurality of times. Thereafter, the laminated body is fired, the resistance layer or the inductor layer is formed, and the sintered body is made into chips in the same manner as the wet lamination method, and finally a pair of terminal electrodes is formed.

【0009】第1〜第3のチップ型フィルタ10〜30
とも、抵抗層13,33及びインダクタ層27,37の
表面に絶縁膜16,26,36a,36bを形成するこ
とが好ましい。この絶縁膜としてはSiO2を主成分と
する膜が好ましい。この絶縁膜の形成方法としては、ガ
ラスペーストを塗布し焼成する厚膜形成法、或いは真空
蒸着法、スパッタリング法、イオンプレーティング法の
ような物理蒸着法(PVD法)又は化学蒸着法(CVD
法)の薄膜形成法により行われる。また上記絶縁膜1
6,26,36a,36bはチップ状に切断したベアチ
ップ11,21,31に端子電極14,15,24,2
5,34,35を形成した後又は前に形成してもよく、
或いはチップ状に切断する前にセラミック焼結体の抵抗
層13,33及びインダクタ層27,37の表面に形成
してもよい。
First to third chip type filters 10 to 30
In both cases, it is preferable to form the insulating films 16, 26, 36a and 36b on the surfaces of the resistance layers 13 and 33 and the inductor layers 27 and 37. As the insulating film, a film containing SiO 2 as a main component is preferable. As a method for forming this insulating film, a thick film forming method in which a glass paste is applied and baked, or a physical vapor deposition method (PVD method) such as a vacuum vapor deposition method, a sputtering method, an ion plating method, or a chemical vapor deposition method (CVD) is used.
Method). In addition, the insulating film 1
6, 26, 36a, 36b are terminal electrodes 14, 15, 24, 2 on bare chips 11, 21, 31 cut into chips.
May be formed after or before forming 5, 34, 35,
Alternatively, it may be formed on the surfaces of the resistance layers 13 and 33 and the inductor layers 27 and 37 of the ceramic sintered body before being cut into chips.

【0010】[0010]

【作用】第1のチップ型RCフィルタ10は抵抗層13
及び端子電極14,15からなる抵抗回路と、この抵抗
層13と内部電極12とこれらの間に介在するチップ1
1の誘電体からなる分布キャパシタンス回路とを構成
し、図3(a)又は図3(b)の等価回路で示される。
第2のチップ型LCフィルタ20はインダクタ層27及
び端子電極24,25からなるインダクタ回路と、この
インダクタ層27と内部電極22とこれらの間に介在す
るチップ21の誘電体からなる分布キャパシタンス回路
とを構成し、図6(a)又は図6(b)の等価回路で示
される。第3のチップ型RLCフィルタ30は抵抗層3
3及び端子電極34,35からなる抵抗回路と、インダ
クタ層37及び端子電極34,35からなるインダクタ
と、抵抗層33と内部電極32とこれらの間に介在する
チップ31の誘電体からなる分布キャパシタンス回路
と、インダクタ層37と内部電極33とこれらの間に介
在するチップ31の誘電体からなる分布キャパシタンス
回路とを構成し、図9(a)又は図9(b)の等価回路
で示される。
The first chip type RC filter 10 has the resistance layer 13
And a resistance circuit including the terminal electrodes 14 and 15, the resistance layer 13, the internal electrode 12, and the chip 1 interposed therebetween.
And a distributed capacitance circuit made of a dielectric material, which is shown by the equivalent circuit in FIG. 3 (a) or FIG. 3 (b).
The second chip type LC filter 20 includes an inductor circuit composed of an inductor layer 27 and terminal electrodes 24 and 25, and a distributed capacitance circuit composed of the inductor layer 27, an internal electrode 22 and a dielectric material of a chip 21 interposed therebetween. And is shown by the equivalent circuit of FIG. 6 (a) or FIG. 6 (b). The third chip type RLC filter 30 includes the resistance layer 3
3 and the terminal electrodes 34 and 35, the inductor layer 37 and the terminal electrodes 34 and 35, the inductor, the resistance layer 33 and the internal electrode 32, and the distributed capacitance formed of the dielectric of the chip 31 interposed therebetween. A circuit and a distributed capacitance circuit composed of the inductor layer 37, the internal electrode 33, and the dielectric material of the chip 31 interposed therebetween are shown in the equivalent circuit of FIG. 9A or 9B.

【0011】図11に示すように、RCフィルタの場
合、チップ状に切断する前に又は後でレーザビーム光な
どにより抵抗層13に所望の長さだけ切込み18を入れ
れば、所望のRC時定数が得られる。図示しないが第2
及び第3のチップ型フィルタの抵抗層又はインダクタ層
にも同様に切込みを入れれば、所望のRC時定数又はL
C時定数が得られる。
As shown in FIG. 11, in the case of the RC filter, a desired RC time constant can be obtained by making a notch 18 in a desired length in the resistance layer 13 by laser beam light before or after cutting it into chips. Is obtained. Although not shown, the second
If the notch is similarly made in the resistance layer or the inductor layer of the third chip type filter, the desired RC time constant or L
The C time constant is obtained.

【0012】抵抗層13,33及びインダクタ層27,
37の表面に絶縁膜16,26,36a,36bを形成
すると、第一に端子電極のはんだ耐熱性向上のためにN
iめっきを、又ははんだ付け性向上のためにSnめっき
をそれぞれ端子電極に施す場合にめっきが抵抗層、イン
ダクタ層に直接付着せず、抵抗値又はインダクタンス値
が変わらない。また第二にチップ型フィルタ10〜30
の使用環境が高温多湿であってもフィルタ特性が変わら
ない。
Resistor layers 13, 33 and inductor layers 27,
When the insulating films 16, 26, 36a, 36b are formed on the surface of 37, first, N is used for improving the solder heat resistance of the terminal electrode.
When i plating or Sn plating for improving solderability is applied to the terminal electrodes, the plating does not directly adhere to the resistance layer and the inductor layer, and the resistance value or the inductance value does not change. Secondly, chip type filters 10 to 30
The filter characteristics do not change even if the operating environment is hot and humid.

【0013】[0013]

【実施例】次に本発明の実施例を図面に基づいて詳しく
説明する。 <実施例1>図1及び図2に示すように、第1のチップ
型RCフィルタ10はセラミック誘電体からなるベアチ
ップ11と、内部電極12と、抵抗層13と、一対の端
子電極14,15を備える。このチップ型フィルタ10
は次の方法により作られる。先ずPb系リラクサ材料で
作られたセラミック誘電体グリーンシートを積層してセ
ラミック誘電体層を形成した後、所定のパターンでAg
系の厚膜ペーストをスクリーン印刷し乾燥して等間隔に
多数の内部電極を形成し、この上にこれらの内部電極を
全て被覆するようにして上述したセラミック誘電体層と
同形同大のセラミック誘電体層を積層した。これにより
内部電極は上下のセラミック誘電体層に挟持された。次
にこの積層体を焼成して誘電体の層厚がそれぞれ5〜数
100μmで内部電極12が内蔵された板状のセラミッ
ク焼結体を形成した後、この焼結体上に所定のパターン
でRuO2系厚膜ペーストを内部電極に相応する位置に
スクリーン印刷し焼成した。これにより厚さ5〜数10
0μmの抵抗層13が形成された。この所定のパターン
は内部電極の個々のパターンと幅が同一で長さが若干長
い個々のパターンからなる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. <Embodiment 1> As shown in FIGS. 1 and 2, a first chip type RC filter 10 includes a bare chip 11 made of a ceramic dielectric, an internal electrode 12, a resistance layer 13, and a pair of terminal electrodes 14 and 15. Equipped with. This chip type filter 10
Is created by the following method. First, a ceramic dielectric green sheet made of a Pb-based relaxor material is laminated to form a ceramic dielectric layer, and then Ag is formed in a predetermined pattern.
A thick film paste of the system is screen-printed and dried to form a large number of internal electrodes at equal intervals, and all of these internal electrodes are covered with the same size ceramic ceramic layer as described above. Dielectric layers were laminated. As a result, the internal electrodes were sandwiched between the upper and lower ceramic dielectric layers. Next, the laminated body is fired to form a plate-shaped ceramic sintered body having a dielectric layer thickness of 5 to several 100 μm and the internal electrodes 12 incorporated therein, and then a predetermined pattern is formed on the sintered body. The RuO 2 type thick film paste was screen-printed on the positions corresponding to the internal electrodes and baked. By this, thickness 5 to several 10
The resistance layer 13 of 0 μm was formed. This predetermined pattern consists of individual patterns having the same width as the individual patterns of the internal electrodes and a slightly longer length.

【0014】次にこの焼結体を個々の抵抗層毎にダイヤ
モンドソーでチップ状に切断した後、得られたベアチッ
プ11をバレル研磨してその一方の端面に内部電極を露
出させた。このベアチップ11の両端部にAg−Pdの
導電性ペーストを塗布し焼付けて一対の端子電極14,
15を形成した。更にこのベアチップ11の抵抗層13
の表面にガラスペーストを塗布して焼成し、SiO2
主成分とする厚さ5〜数10μmの絶縁膜16を形成す
ることによりチップ型RCフィルタ10を作製した。
Next, the sintered body was cut into individual resistance layers into chips with a diamond saw, and the obtained bare chips 11 were barrel-polished to expose the internal electrodes on one end face thereof. A conductive paste of Ag-Pd is applied to both ends of the bare chip 11 and baked to form a pair of terminal electrodes 14,
Formed 15. Further, the resistance layer 13 of the bare chip 11
The chip-type RC filter 10 was manufactured by applying a glass paste on the surface of and baking it to form an insulating film 16 containing SiO 2 as a main component and having a thickness of 5 to several tens of μm.

【0015】<実施例2>実施例1と同様にしてセラミ
ック焼結体を形成し、図4及び図5に示すようにこのセ
ラミック焼結体の上に実施例1のRuO2系厚膜ペース
トの代わりにフェライト又は強磁性体の厚膜ペーストを
実施例1と同様にスクリーン印刷し焼成した。これによ
り厚さ5〜数100μmのインダクタ層27が形成され
た。その後実施例1と同様にして端子電極24,25を
形成し、更に絶縁膜26を形成することによりチップ型
LCフィルタ20を作製した。
Example 2 A ceramic sintered body was formed in the same manner as in Example 1, and the RuO 2 type thick film paste of Example 1 was formed on the ceramic sintered body as shown in FIGS. 4 and 5. Instead of, a thick film paste of ferrite or ferromagnetic material was screen-printed and fired in the same manner as in Example 1. As a result, the inductor layer 27 having a thickness of 5 to several 100 μm was formed. After that, the terminal electrodes 24 and 25 were formed in the same manner as in Example 1, and the insulating film 26 was further formed to fabricate the chip type LC filter 20.

【0016】<実施例3>実施例1と同様にしてセラミ
ック焼結体を形成し、図7及び図8に示すようにこのセ
ラミック焼結体の表面には実施例1と同様にして抵抗層
33を形成し、セラミック焼結体の裏面には実施例2と
同様にしてインダクタ層37を形成した。その後実施例
1と同様にして端子電極34,35を形成し、更に絶縁
膜36a,36bを形成することによりチップ型RLC
フィルタ30を作製した。
<Example 3> A ceramic sintered body was formed in the same manner as in Example 1, and the resistance layer was formed on the surface of this ceramic sintered body in the same manner as in Example 1 as shown in FIGS. 33 was formed, and the inductor layer 37 was formed on the back surface of the ceramic sintered body in the same manner as in Example 2. After that, in the same manner as in Example 1, the terminal electrodes 34 and 35 are formed, and then the insulating films 36a and 36b are formed, whereby the chip-type RLC is formed.
The filter 30 was produced.

【0017】<実施例4>図10に示すように、内部電
極32を2層形成した以外は、実施例3と同様にしてR
LCチップ型フィルタ30を作製した。
<Embodiment 4> As shown in FIG. 10, R was formed in the same manner as in Embodiment 3 except that two layers of internal electrodes 32 were formed.
The LC chip type filter 30 was produced.

【0018】[0018]

【発明の効果】以上述べたように、本発明によれば、チ
ップ表面に形成した抵抗層又はインダクタ層をチップ内
部に形成した内部電極とともにコンデンサの構成要素と
したので、1チップの極めて小型の形態でRC、LC又
はRLCの機能を具備でき、高密度にプリント回路基板
に実装することができる。また抵抗層又はインダクタ層
に所望の長さだけ切込みを入れれば、所望のRC時定数
又はLC時定数が得られる。更に抵抗層及びインダクタ
層の表面に絶縁膜を形成すれば、端子電極のめっき処理
時にめっきが抵抗層、インダクタ層に直接付着せず、ま
たチップ型フィルタの使用環境が高温多湿であっても、
それぞれフィルタ特性が変わらない。
As described above, according to the present invention, the resistance layer or the inductor layer formed on the surface of the chip together with the internal electrodes formed inside the chip are used as the constituent elements of the capacitor. It can have a function of RC, LC or RLC in a form, and can be mounted on a printed circuit board with high density. Further, if the resistance layer or the inductor layer is cut into a desired length, a desired RC time constant or LC time constant can be obtained. Furthermore, if an insulating film is formed on the surface of the resistance layer and the inductor layer, the plating does not directly adhere to the resistance layer and the inductor layer during the plating process of the terminal electrode, and even if the environment of use of the chip type filter is high temperature and humidity,
The filter characteristics do not change.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例1のチップ型RCフィルタを示す
中央断面図。
FIG. 1 is a central cross-sectional view showing a chip type RC filter according to a first embodiment of the present invention.

【図2】その抵抗層を形成した後のベアチップの要部破
断斜視図。
FIG. 2 is a fragmentary perspective view of a bare chip after forming the resistance layer.

【図3】その等価回路図。FIG. 3 is an equivalent circuit diagram thereof.

【図4】本発明実施例2のチップ型LCフィルタを示す
中央断面図。
FIG. 4 is a central sectional view showing a chip type LC filter of Example 2 of the present invention.

【図5】そのインダクタ層を形成した後のベアチップの
要部破断斜視図。
FIG. 5 is a fragmentary perspective view of the bare chip after the inductor layer is formed.

【図6】その等価回路図。FIG. 6 is an equivalent circuit diagram thereof.

【図7】本発明実施例3のチップ型RLCフィルタを示
す中央断面図。
FIG. 7 is a central sectional view showing a chip type RLC filter of Example 3 of the present invention.

【図8】その抵抗層及びインダクタ層を形成した後のベ
アチップの要部破断斜視図。
FIG. 8 is a fragmentary perspective view of the bare chip after the resistance layer and the inductor layer are formed.

【図9】その等価回路図。FIG. 9 is an equivalent circuit diagram thereof.

【図10】本発明実施例4のチップ型RLCフィルタを
示す中央断面図。
FIG. 10 is a central cross-sectional view showing a chip type RLC filter of Example 4 of the present invention.

【図11】抵抗層に切込みが形成された図2に対応する
斜視図。
11 is a perspective view corresponding to FIG. 2 in which a cut is formed in the resistance layer.

【符号の説明】[Explanation of symbols]

10 チップ型RCフィルタ 11 ベアチップ 12 内部電極 13 抵抗層 14,15 端子電極 16 絶縁膜 18 切込み 20 チップ型LCフィルタ 21 ベアチップ 22 内部電極 24,25 端子電極 26 絶縁膜 27 インダクタ層 30 チップ型RLCフィルタ 31 ベアチップ 32 内部電極 33 抵抗層 34,35 端子電極 36a,36b 絶縁膜 37 インダクタ層 10 chip type RC filter 11 bare chip 12 internal electrode 13 resistance layer 14, 15 terminal electrode 16 insulating film 18 cut 20 chip type LC filter 21 bare chip 22 internal electrode 24, 25 terminal electrode 26 insulating film 27 inductor layer 30 chip type RLC filter 31 Bare chip 32 Internal electrode 33 Resistive layer 34, 35 Terminal electrode 36a, 36b Insulating film 37 Inductor layer

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 チップ内部に1又は2以上の内部電極(1
2)が設けられ、相対向するチップ両端部のいずれか一端
部に前記内部電極(12)が現れるように形成されたセラミ
ック誘電体からなるベアチップ(11)と、 前記ベアチップ(11)の表面の一端部から他端部にかけて
前記内部電極(12)と前記セラミック誘電体を介して対向
するように設けられた抵抗層(13)と、 前記ベアチップ(11)の両端部に前記内部電極(12)の一端
部と前記抵抗層(13)にそれぞれ導通するように焼付けら
れた一対の端子電極(14,15)とを備えたチップ型フィル
タ。
1. A chip having one or more internal electrodes (1
2) is provided, and a bare chip (11) made of a ceramic dielectric formed so that the internal electrode (12) appears at either one of the opposite ends of the chip, and the surface of the bare chip (11) A resistance layer (13) provided so as to face the internal electrode (12) through the ceramic dielectric from one end to the other end, and the internal electrodes (12) at both ends of the bare chip (11). A chip-type filter having one end and a pair of terminal electrodes (14, 15) baked so as to be electrically connected to the resistance layer (13).
【請求項2】 チップ内部に1又は2以上の内部電極(2
2)が設けられ、相対向するチップ両端部のいずれか一端
部に前記内部電極(22)が現れるように形成されたセラミ
ック誘電体からなるベアチップ(21)と、 前記ベアチップ(21)の表面の一端部から他端部にかけて
前記内部電極(22)と前記セラミック誘電体を介して対向
するように設けられたインダクタ層(27)と、 前記ベアチップ(21)の両端部に前記内部電極(22)の一端
部と前記インダクタ層(27)にそれぞれ導通するように焼
付けられた一対の端子電極(24,25)とを備えたチップ型
フィルタ。
2. One or more internal electrodes (2
2) is provided, and a bare chip (21) made of a ceramic dielectric formed so that the internal electrode (22) appears at either one of the opposite ends of the chip, and the surface of the bare chip (21) An inductor layer (27) provided to face the internal electrode (22) through the ceramic dielectric from one end to the other end, and the internal electrodes (22) at both ends of the bare chip (21). A chip-type filter having one end and a pair of terminal electrodes (24, 25) baked so as to be electrically connected to the inductor layer (27).
【請求項3】 チップ内部に1又は2以上の内部電極(3
2)が設けられ、相対向するチップ両端部のいずれか一端
部に前記内部電極(32)が現れるように形成されたセラミ
ック誘電体からなるベアチップ(31)と、 前記ベアチップ(31)の表面の一端部から他端部にかけて
前記内部電極(32)と前記セラミック誘電体を介して対向
するように設けられた抵抗層(33)と、 前記ベアチップ(31)の裏面の一端部から他端部にかけて
前記内部電極(32)と前記セラミック誘電体を介して対向
するように設けられたインダクタ層(37)と、 前記ベアチップ(31)の両端部に前記内部電極(32)の一端
部と前記抵抗層(33)と前記インダクタ層(37)にそれぞれ
導通するように焼付けられた一対の端子電極(34,35)と
を備えたチップ型フィルタ。
3. One or more internal electrodes (3
2) is provided, a bare chip (31) made of a ceramic dielectric formed so that the internal electrode (32) appears at either one of the opposite ends of the chip, and the surface of the bare chip (31) A resistance layer (33) provided so as to face the internal electrode (32) and the ceramic dielectric from one end to the other end, and from one end to the other end of the back surface of the bare chip (31). An inductor layer (37) provided so as to face the internal electrode (32) via the ceramic dielectric, one end of the internal electrode (32) and the resistance layer at both ends of the bare chip (31). A chip type filter comprising (33) and a pair of terminal electrodes (34, 35) baked so as to be electrically connected to the inductor layer (37).
【請求項4】 抵抗層(13,33)が絶縁膜(16,36a)で被覆
された請求項1又は3記載のチップ型フィルタ。
4. The chip type filter according to claim 1, wherein the resistance layer (13, 33) is covered with an insulating film (16, 36a).
【請求項5】 インダクタ層(27,37)が絶縁膜(26,36b)
で被覆された請求項2又は3記載のチップ型フィルタ。
5. The inductor layer (27,37) is an insulating film (26,36b)
The chip type filter according to claim 2 or 3, which is covered with.
【請求項6】 抵抗層(13,33)に所望の長さの切込み(1
8)が入れられRC時定数が所望の値に設定された請求項
1又は3記載のチップ型フィルタ。
6. A notch (1) having a desired length is formed in the resistance layer (13, 33).
The chip type filter according to claim 1 or 3, wherein 8) is inserted and the RC time constant is set to a desired value.
【請求項7】 インダクタ層(27,37)に所望の長さの切
込みが入れられLC時定数が所望の値に設定された請求
項2又は3記載のチップ型フィルタ。
7. The chip type filter according to claim 2, wherein the inductor layer (27, 37) is provided with a notch having a desired length and the LC time constant is set to a desired value.
JP6591895A 1995-03-24 1995-03-24 Chip filter Withdrawn JPH08265079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6591895A JPH08265079A (en) 1995-03-24 1995-03-24 Chip filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6591895A JPH08265079A (en) 1995-03-24 1995-03-24 Chip filter

Publications (1)

Publication Number Publication Date
JPH08265079A true JPH08265079A (en) 1996-10-11

Family

ID=13300840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6591895A Withdrawn JPH08265079A (en) 1995-03-24 1995-03-24 Chip filter

Country Status (1)

Country Link
JP (1) JPH08265079A (en)

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