JP3231350B2 - Capacitor network - Google Patents

Capacitor network

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Publication number
JP3231350B2
JP3231350B2 JP10240591A JP10240591A JP3231350B2 JP 3231350 B2 JP3231350 B2 JP 3231350B2 JP 10240591 A JP10240591 A JP 10240591A JP 10240591 A JP10240591 A JP 10240591A JP 3231350 B2 JP3231350 B2 JP 3231350B2
Authority
JP
Japan
Prior art keywords
electrode
ceramic substrate
face
common electrode
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP10240591A
Other languages
Japanese (ja)
Other versions
JPH04333208A (en
Inventor
治 牧野
考生 秦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP10240591A priority Critical patent/JP3231350B2/en
Publication of JPH04333208A publication Critical patent/JPH04333208A/en
Application granted granted Critical
Publication of JP3231350B2 publication Critical patent/JP3231350B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、主として高周波回路の
ノイズフィルタとして用いるコンデンサネットワークに
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor network mainly used as a noise filter for a high-frequency circuit.

【0002】[0002]

【従来の技術】近年、コンデンサネットワークは高速デ
ジタル回路の高周波ノイズ吸収素子として多用されてい
る。
2. Description of the Related Art In recent years, capacitor networks are frequently used as high frequency noise absorbing elements in high-speed digital circuits.

【0003】以下に従来の厚膜貫通コンデンサネットワ
ークについて説明する。
A conventional thick film capacitor network will be described below.

【0004】図13および図14に示すように、チタン
酸バリウム系のセラミックコンデンサ粉を短冊形に加圧
成形して1300℃前後の高温で焼成した磁器コンデン
サ基板12に、容量形成用の電極14と共通電極13と
が磁器コンデンサ基板12を挟んで対向するように銀系
の厚膜ペーストを印刷,焼成して形成する。さらにリー
ド端子15をはんだ付け後、絶縁塗料16を被覆してコ
ンデンサネットワークを完成する。
As shown in FIGS. 13 and 14, a barium titanate-based ceramic capacitor powder is formed into a strip shape under pressure and fired at a high temperature of about 1300 ° C. on a ceramic capacitor substrate 12. A silver-based thick film paste is printed and fired so that the ceramic electrode substrate 13 and the common electrode 13 are opposed to each other with the ceramic capacitor substrate 12 interposed therebetween. Furthermore, after soldering the lead terminals 15, the insulating paint 16 is covered to complete the capacitor network.

【0005】この従来のコンデンサネットワークは、3
0pF〜10nFの容量値のコンデンサ3〜12素子を一つ
の部品に複合したもので、特にマイコンの入出力部の高
周波ノイズ吸収素子として広く用いられている。
[0005] This conventional capacitor network has three
It is a composite of 3 to 12 capacitors having a capacitance of 0 pF to 10 nF in one component, and is widely used particularly as a high frequency noise absorbing element in an input / output unit of a microcomputer.

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記の従
来の構成では、リードタイプでしかも背丈が高いため、
薄型で小型化を求められる機器には使えないという問題
点、また、電極14同志の間に発生する浮遊容量のため
隣接端子間の信号のクロストークや、リード端子15に
よって発生する残留インダクタンスによる共振周波数の
低下により高速デジタル回路には使えないという問題
点、さらに、磁器コンデンサ基板12自体の機械的強度
が弱いため、磁器コンデンサ基板12の厚みを薄くでき
ないばかりか、シート状の焼結体をチョコレート・ブレ
ークして個片化する製造方法を採用できず量産性が悪い
という問題点を有していた。
However, in the above-mentioned conventional configuration, since it is a lead type and has a high height,
It cannot be used for a device which is required to be thin and small. In addition, a crosstalk of a signal between adjacent terminals due to a stray capacitance generated between the electrodes 14 and a resonance due to a residual inductance generated by the lead terminal 15. The problem is that it cannot be used for high-speed digital circuits due to the decrease in frequency, and furthermore, the mechanical strength of the ceramic capacitor substrate 12 itself is weak, so that not only can the thickness of the ceramic capacitor substrate 12 be reduced, but also the sheet-shaped sintered body can be used in chocolate. -There was a problem that the manufacturing method of breaking into individual pieces could not be adopted and mass productivity was poor.

【0007】本発明は上記従来の問題点を解決するもの
で、優れた実装性とノイズ吸収特性を有しかつ量産性の
良いコンデンサネットワークを提供することを目的とす
る。
An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a capacitor network having excellent mountability, noise absorption characteristics, and good mass productivity.

【0008】[0008]

【課題を解決するための手段】この目的を達成するため
に本発明のコンデンサネットワークは、電気絶縁性を示
す短冊形のセラミック基板と、前記セラミック基板の上
に形成した複数の独立した貫通電極、および前記貫通電
極との対向面積が一定になるように、厚膜誘電体層を介
して対向する共通電極を含み、前記セラミック基板上に
あってネットワーク化されたコンデンサ要素と、前記セ
ラミック基板の端面に形成され、前記複数の独立した貫
通電極と前記共通電極とにそれぞれ接続された複数の端
面電極対とを備え、前記厚膜誘電体層は、前記貫通電極
の両端の一部を残して前記貫通電極を覆うように形成し
たものである。
In order to achieve the above object, a capacitor network according to the present invention comprises a strip-shaped ceramic substrate having electrical insulation, a plurality of independent through electrodes formed on the ceramic substrate , And the through current
A common electrode facing through a thick-film dielectric layer is included so that the area facing the poles is constant, and a networked capacitor element on the ceramic substrate is formed on an end face of the ceramic substrate. , A plurality of end face electrode pairs respectively connected to the plurality of independent through electrodes and the common electrode, wherein the thick film dielectric layer comprises:
Formed so as to cover the through electrode, leaving a part of both ends of
It is a thing.

【0009】[0009]

【作用】この構成によれば、予め焼成されたセラミック
基板の端面のみに直接厚膜導体ペーストを印刷・焼成し
て端面電極が設けられているため、密着性が良く端面電
極の強度が大きくなるものである。また、セラミック基
板の端面のみに設けた端面電極を回路基板に直接はんだ
付けできるので、低背でしかも高密度に実装できると共
に、リードレスのため不要なインダクタが発生しないこ
ととなり、また、量産性を高くすることとなる。
According to this structure, a ceramic fired in advance is used.
Since the thick-film conductor paste is printed and fired directly on the end face of the substrate to provide the end face electrode, the adhesion is good and the strength of the end face electrode is increased. In addition, since the end surface electrodes provided only on the end surface of the ceramic substrate can be directly soldered to the circuit board, they can be mounted at a low profile and at a high density, and unnecessary inductors are not generated due to leadless, and mass production is possible. Will be higher.

【0010】[0010]

【実施例】(実施例1) 以下本発明の実施例1について、図面を参照しながら説
明する。
EXAMPLES For the Examples 1 (Example 1) Hereinafter the present invention will be described with reference to the drawings.

【0011】図1〜図4に示すように、独立した複数の
貫通電極3aを形成した電気絶縁性のアルミナ系のセラ
ミック基板1aに厚膜誘電体層4aを介して貫通電極3
aと対向する共通電極5aおよび複数の端面電極対8
a、9aを配設した構成のコンデンサネットワークにつ
いて、図5を用いてその製造方法を説明する。
As shown in FIGS. 1 to 4 , an electrically insulating alumina-based ceramic substrate 1a on which a plurality of independent through electrodes 3a are formed is formed through a thick dielectric layer 4a.
a and a plurality of end face electrode pairs 8 facing
A method for manufacturing a capacitor network having a configuration in which the capacitors a and 9a are provided will be described with reference to FIG.

【0012】図5(a)に示すように、分割後の1個片
が2.5mm×7mmの短冊形のセラミック基板1aになる
ように縦横に一次分割溝6と二次分割溝7を加工したシ
ート状のセラミック基板2aの片面に銀パラジュウム系
の厚膜導体ペーストをスクリーン印刷し850℃で1時
間焼成することにより、複数の独立した貫通電極3aを
形成する。つぎに、図5(b)に示すように、貫通電極
3aの両端の一部を残して貫通電極3aを覆うように、
マグネ・ニオブ酸鉛系の厚膜コンデンサペーストをスク
リーン印刷し850℃で1時間焼成し厚膜誘電体層4a
を形成する。ついで図5(c)に示すように、各貫通電
極3aとの対向面積が一定となるような共通電極5a
を、銀パラジュウム系の厚膜導体ペーストをスクリーン
印刷し850℃で1時間焼成することにより設け、コン
デンサ要素を形成する。ついで図5(d)に示すよう
に、シート状のセラミック基板2aの一次分割溝6に沿
って分割した後、図5(e)に示すように分割された両
端面に貫通電極3aに接続する信号用の端面電極対9a
共通電極5aに接続するアース端子用の端面電極対8
aを銀パラジュウム系の厚膜導体ペーストを塗布し60
0℃で1時間焼成することによって形成し、最後に、図
5(f)に示すように、二次分割溝7に沿って分割する
ことによって個片にしてコンデンサネットワークを完成
させる。
As shown in FIG. 5 (a), the primary division groove 6 and the secondary division groove 7 are machined vertically and horizontally so that one piece after division becomes a rectangular ceramic substrate 1a of 2.5 mm × 7 mm. A plurality of independent through-electrodes 3a are formed by screen-printing a silver-paradium-based thick-film conductor paste on one side of the sheet-shaped ceramic substrate 2a and baking it at 850 ° C. for 1 hour. Next, as shown in FIG. 5B, a part of both ends of the through electrode 3a is left so as to cover the through electrode 3a.
Thick film dielectric paste 4a is screen-printed and baked at 850 ° C. for 1 hour.
To form Next, as shown in FIG. 5 (c), the common electrode 5a has a constant area facing each through electrode 3a.
Is formed by screen printing a silver palladium-based thick film conductor paste and baking it at 850 ° C. for 1 hour to form a capacitor element. Next, as shown in FIG. 5D, after the sheet-like ceramic substrate 2a is divided along the primary division grooves 6, the divided end faces are connected to the through electrodes 3a as shown in FIG. 5E. End electrode pair 9a for signal
And an end face electrode pair 8 for a ground terminal connected to the common electrode 5a
a is coated with a silver-palladium thick conductor paste
It is formed by firing at 0 ° C. for one hour, and finally, as shown in FIG. 5 (f), is divided along the secondary division grooves 7 to complete the capacitor network.

【0013】本実施例1によるコンデンサネットワーク
と従来のコンデンサネットワークのそれぞれの1コンデ
ンサ素子の挿入損失特性を図6に比較して示している。
尚、両者共に静電容量値が2200pFのもので、回路イ
ンピーダンスが50Ωで測定した。
FIG. 6 shows the insertion loss characteristics of one capacitor element of each of the capacitor network according to the first embodiment and the conventional capacitor network.
In both cases, the capacitance value was 2200 pF, and the circuit impedance was measured at 50Ω.

【0014】図6から明らかなように、本発明によるコ
ンデンサネットワークは、高周波ノイズ吸収性の点で優
れた効果が得られる。
As is clear from FIG. 6, the capacitor network according to the present invention has an excellent effect in terms of high frequency noise absorption.

【0015】以上のように本実施例1によれば、短冊形
のセラミック基板1aと、セラミック基板1a上にあっ
てネットワーク化され、かつ複数の独立した貫通電極3
a、および前記貫通電極3aとの対向面積が一定になる
ように、厚膜誘電体層4aを介して対向する共通電極5
aを含むコンデンサ要素と、前記セラミック基板1aの
端面のみに形成され、かつ貫通電極3aと共通電極5a
とに接続される複数の端面電極対8a、9aを設けるこ
とにより、ノイズ除去性および実装性を優れたものにす
ることができる。
According to the first embodiment described above, the ceramic substrate 1a of the thin and long, be on the ceramic substrate 1a
Network and a plurality of independent through electrodes 3
a and the area facing the through electrode 3a becomes constant.
As described above, the common electrode 5 opposed via the thick film dielectric layer 4a
a , and a through electrode 3a and a common electrode 5a formed only on the end face of the ceramic substrate 1a.
By providing a plurality of end face electrode pairs 8a and 9a connected to the above , the noise elimination property and the mountability can be improved.

【0016】(実施例2) 以下本発明の実施例2について図面を参照しながら説明
する。
[0016] (Example 2) will be described with reference to the following with the second embodiment of the present invention with reference to the accompanying drawings.

【0017】図7〜図10において、2bはアルミナ系
シート状のセラミック基板、1bはセラミック基板、
8bおよび9bは端面電極対、3bは貫通電極、4bは
厚膜誘電体層、5bは共通電極、6は一次分割溝、7は
二次分割溝で、以上は実施例1の構成と同様なものであ
る。実施例1の構成と異なるのは、貫通電極3bが厚膜
誘電体層4bの厚み方向の中央部を貫通し、かつ、厚膜
誘電体層4bの下面に下面共通電極11を設けた点と、
貫通電極3bと接続される信号用の端面電極対9bをセ
ラミック基板1bの長辺側の端面の凹部に形成した点
と、共通電極5bや下面共通電極11と接続されるアー
ス端子用の端面電極対8bをセラミック基板1bの短辺
側の端面に形成した点である。
7 to 10 , 2b is an alumina-based sheet ceramic substrate, 1b is a ceramic substrate,
8b and 9b are end face electrode pairs, 3b is a through electrode, 4b is a thick film dielectric layer, 5b is a common electrode, 6 is a primary division groove, 7 is a secondary division groove, and the above is the same as the configuration of the first embodiment. Things. And different from the configuration example 1, the through electrode 3b penetrates the central portion in the thickness direction of the thick film dielectric layer 4b, and a point having a lower surface common electrode 11 on the lower surface of the thick film dielectric layer 4b ,
The end face electrode pair 9b for signal connected to the through electrode 3b is
A point formed in the concave portion on the long side end surface of the lamic substrate 1b is connected to an arc connected to the common electrode 5b and the lower surface common electrode 11 .
This is the point that an end face electrode pair 8b for the terminal is formed on the short side end face of the ceramic substrate 1b.

【0018】上記のように構成されたコンデンサネット
ワークについて、図10を用いてその製造方法を説明す
る。まず、図10(a)に示すように、二次分割溝7に
沿って直径4mmの丸孔10を等ピッチに設けたシート状
のセラミック基板2bの丸孔10の部分に銀パラジュウ
ム系の厚膜導体ペーストをスクリーン印刷機でスルーホ
ール印刷し、850℃で1時間焼成することにより、複
数の端面電極対9bと下面共通電極11を形成する。つ
ぎに、図10(b)に示すように、下面共通電極11を
覆うように、マグネ・ニオブ酸鉛系の厚膜コンデンサペ
ーストをスクリーン印刷した上に、図10(c)に示す
ように、複数の貫通電極3bを印刷してから、図10
(d)に示すように、さらに厚膜コンデンサペーストを
印刷して850℃で1時間焼成し厚膜誘電体層4を形成
する。その後に、図10(e)に示すように、共通電極
5aを、銀パラジュウム系の厚膜導体ペーストをスクリ
ーン印刷し850℃で1時間焼成することにより設け、
コンデンサ要素を形成する。さらに、図10(f)に示
すように、シート状のセラミック基板2bの一次分割溝
6を分割した後、セラミック基板1bの短辺側の端面に
あたるこの分割面に共通電極5bと接続され、かつ相対
向するような端面電極対8bを銀パラジュウム系の厚膜
導体ペーストを塗布し焼成することによって形成する。
最後に、二次分割溝7に沿って分割することによって
ラミック基板1bからなる個片にしてコンデンサネット
ワークを完成させる。
A method of manufacturing the capacitor network configured as described above will be described with reference to FIG. First, as shown in FIG. 10 (a), a silver palladium-based thickness is formed in a round hole 10 of a sheet-shaped ceramic substrate 2b in which round holes 10 having a diameter of 4 mm are provided at equal pitches along the secondary dividing groove 7. The film conductor paste is subjected to through-hole printing using a screen printer, and baked at 850 ° C. for 1 hour, thereby forming a plurality of end face electrode pairs 9 b and a lower face common electrode 11. Next, as shown in FIG. 10B, a magne-niobate-based thick film capacitor paste was screen-printed so as to cover the lower surface common electrode 11, and as shown in FIG. After printing a plurality of through electrodes 3b, FIG.
As shown in (d), a thick film capacitor paste is further printed and baked at 850 ° C. for 1 hour to form a thick film dielectric layer 4. Thereafter, as shown in FIG. 10E, the common electrode 5a is provided by screen-printing a silver palladium-based thick film conductor paste and firing at 850 ° C. for 1 hour.
Form a capacitor element. Further, as shown in FIG. 10 (f), after dividing the primary division groove 6 of the sheet-shaped ceramic substrate 2b, the divided surface corresponding to the short side end surface of the ceramic substrate 1b is connected to the common electrode 5b, and The end face electrode pairs 8b facing each other are formed by applying a silver-paradium-based thick-film conductor paste and firing the paste.
Se Finally, by dividing along the secondary dividing groove 7
A capacitor network is completed by using the individual pieces made of the lamic substrate 1b .

【0019】このようにして得られたコンデンサネット
ワークの挿入損失特性を実施例1と同様にして測定した
結果、100MHzでの挿入損失が2dBほど大きく、高周
波ノイズ吸収性の点で優れた効果が得られる。
The insertion loss characteristics of the capacitor network thus obtained were measured in the same manner as in Example 1. As a result, the insertion loss at 100 MHz was as large as 2 dB, and an excellent effect in terms of high frequency noise absorption was obtained. Can be

【0020】以上のように、本実施例2によれば2層の
共通電極5b,11にはさまれた厚膜誘電体層4b,
の中に貫通電極3bを配設することにより、コンデンサ
のシールド効果を強め、高周波特性のより優れたものに
できる。
As described above , according to the second embodiment, the thick dielectric layers 4b, 4 sandwiched between the two common electrodes 5b, 11 are formed.
By disposing the through electrode 3b in the inside, the shielding effect of the capacitor can be strengthened and the high frequency characteristics can be further improved.

【0021】(実施例3) 以下本発明の実施例3について図面を参照しながら説明
する。図11に示すように、実施例1の構成と異なるの
は、貫通電極3cと接続される信号用の端面電極対9c
をセラミック基板1cの長辺側の端面の凸部に形成した
点と、共通電極5cと接続されるアース端子用の端面電
極対8cをセラミック基板1cの短辺側の端面に形成し
た点である。
[0021] will be described with reference to the drawings attached to the third embodiment (Embodiment 3) The following present invention. As shown in FIG. 11, a difference from the configuration of the first embodiment is that a pair of end face electrodes 9c for signals connected to the through electrodes 3c is provided.
Is formed on the protruding portion of the end face on the long side of the ceramic substrate 1c, and the end face voltage for the ground terminal connected to the common electrode 5c is formed.
The point is that the pole pair 8c is formed on the end face on the short side of the ceramic substrate 1c.

【0022】本実施例3のコンデンサネットワークの製
造方法は、実施例1と基本的には同様であるが、二次分
割溝7に沿って一辺が4mmの角孔をまた一次分割溝6に
沿って長方形の角穴を等ピッチに設けたシート状のセラ
ミック基板1cを用いた点と、一次分割後にアース端子
用の端面電極対8cを設けた点である。本実施例3の
ンデンサネットワークは優れたノイズ吸収特性を有して
いた。
The method of manufacturing the capacitor network of the third embodiment is basically the same as that of the first embodiment, except that a square hole having a side of 4 mm is formed along the secondary division groove 7 and along the primary division groove 6. The point is that a sheet-like ceramic substrate 1c in which rectangular holes are provided at equal pitches is used, and an end face electrode pair 8c for a ground terminal is provided after primary division. The capacitor network of Example 3 had excellent noise absorption characteristics.

【0023】なお、上記実施例1〜3においては、厚膜
導体ペーストは銀パラジュウムを用いてすべて空気中で
焼成したが、銅系のペーストを用いて非酸化性の雰囲気
で焼成してもよい。また、上記実施例1〜3では、厚膜
誘電体層4,4a,4bはセラミック基板の片面のみに
形成したが、セラミック基板の両面でも良い。また、図
12に示すように、セラミック基板1dに端面電極対8
d,9dを備えたコンデンサ素子の保護を目的とした例
えばガラス層の保護コート層17を覆設しても良い。さ
らには、上記実施例1〜3の厚膜誘電体層4,4a,4
bはすべてそれらの厚膜ペーストをスクリーン印刷によ
り設けたが、グリーンシートを接着するなど他の方法に
よって形成してもよいものである。
[0023] In the above Examples 1-3, all thick film conductor pastes using silver palladium was calcined in air, it may be fired in non-oxidizing atmosphere using a copper-based paste . Further, in Examples 1 to 3, the thick film was used.
Although the dielectric layers 4, 4a, 4b are formed only on one side of the ceramic substrate, they may be formed on both sides of the ceramic substrate. Further, as shown in FIG. 12, the end face electrode pair 8 is provided on the ceramic substrate 1d .
A protective coat layer 17 of, for example, a glass layer for the purpose of protecting the capacitor element provided with d and 9d may be provided. Furthermore, the thick dielectric layers 4, 4a, 4
In the case of b, these thick film pastes are provided by screen printing, but may be formed by other methods such as bonding a green sheet .

【0024】[0024]

【発明の効果】以上のように本発明は、短冊形のセラミ
ック基板と、前記セラミック基板の上に形成した複数の
独立した貫通電極、および前記貫通電極との対向面積が
一定になるように、厚膜誘電体層を介して対向する共通
電極を含み、前記セラミック基板上にあってネットワー
ク化されたコンデンサ要素と、前記セラミック基板の端
面に形成され、前記複数の独立した貫通電極と前記共通
電極とにそれぞれ接続された複数の端面電極対とを
え、前記厚膜誘電体層は、前記貫通電極の両端の一部を
残して前記貫通電極を覆うように形成したもので、この
構成によれば、端面電極とセラミック基板との密着強度
が向上するため、優れた実装性とノイズ吸収特性を有
し、量産性の良い優れたコンデンサネットワークを実現
できるものである。
As described above, the present invention provides a rectangular ceramic substrate, a plurality of independent through-electrodes formed on the ceramic substrate , and a constant area of opposition to the through-electrode . Common facing through thick dielectric layer
A capacitor element that includes an electrode and is networked on the ceramic substrate; and a plurality of end face electrode pairs formed on an end face of the ceramic substrate and connected to the plurality of independent through electrodes and the common electrode, respectively. Bei the door
The thick-film dielectric layer is formed by forming a part of both ends of the through electrode.
This is formed so as to cover the through electrode while leaving
According to the configuration, in order to improve the adhesion strength between the end surface electrode and the ceramic substrate, in which has excellent mountability and noise absorption properties, it can realize a good capacitor network mass productivity.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1におけるコンデンサネットワ
ークの外観斜視図
FIG. 1 is an external perspective view of a capacitor network according to a first embodiment of the present invention.

【図2】図1のA−A′断面図FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1;

【図3】図1のB−B′断面図FIG. 3 is a sectional view taken along line BB ′ of FIG. 1;

【図4】同コンデンサネットワークの回路図FIG. 4 is a circuit diagram of the capacitor network.

【図5】同コンデンサネットワークの主な製造工程にお
けるセラミック基板の平面略図
FIG. 5 is a schematic plan view of a ceramic substrate in main manufacturing steps of the capacitor network.

【図6】同コンデンサネットワークと従来のコンデンサ
ネットワークの挿入損失特性の比較図
FIG. 6 is a comparison diagram of the insertion loss characteristics of the capacitor network and a conventional capacitor network.

【図7】本発明の実施例2におけるコンデンサネットワ
ークの正面断面図
FIG. 7 is a front sectional view of a capacitor network according to a second embodiment of the present invention.

【図8】同コンデンサネットワークの側面断面図FIG. 8 is a side sectional view of the capacitor network.

【図9】同コンデンサネットワークの回路図FIG. 9 is a circuit diagram of the capacitor network.

【図10】同コンデンサネットワークの主な製造工程に
おけるセラミック基板の平面略図
FIG. 10 is a schematic plan view of a ceramic substrate in main manufacturing steps of the capacitor network.

【図11】本発明の実施例3におけるコンデンサネット
ワークの外観斜視図
FIG. 11 is an external perspective view of a capacitor network according to a third embodiment of the present invention.

【図12】本発明の他の実施例におけるコンデンサネッ
トワークの外観斜視図
FIG. 12 is an external perspective view of a capacitor network according to another embodiment of the present invention.

【図13】従来のコンデンサネットワークの一部を切欠
きした外観斜視図
FIG. 13 is a cutaway view of a part of a conventional capacitor network.
External perspective view of the can

【図14】従来のコンデンサネットワークの回路図FIG. 14 is a circuit diagram of a conventional capacitor network.

【符号の説明】[Explanation of symbols]

1a セラミック基板 3a 貫通電極 4a 厚膜誘電体層 5a 共通電極 6 一次分割溝 7 二次分割溝 8a 端面電極対 9a 端面電極対 1a Ceramic substrate 3a Through electrode 4a Thick film dielectric layer 5a Common electrode 6 Primary division groove 7 Secondary division groove 8a End face electrode pair 9a End face electrode pair

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平2−33908(JP,A) 特開 昭57−206016(JP,A) 特開 昭56−104429(JP,A) 実開 平2−45623(JP,U) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-33908 (JP, A) JP-A-57-206016 (JP, A) JP-A-56-104429 (JP, A) 45623 (JP, U)

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電気絶縁性を示す短冊形のセラミック基
板と、前記セラミック基板の上に形成した複数の独立し
貫通電極、および前記貫通電極との対向面積が一定に
なるように、厚膜誘電体層を介して対向する共通電極を
含み、前記セラミック基板上にあってネットワーク化さ
れたコンデンサ要素と、前記セラミック基板の端面に形
成され、前記複数の独立した貫通電極と前記共通電極と
にそれぞれ接続された複数の端面電極対とを備え、前記
厚膜誘電体層は、前記貫通電極の両端の一部を残して前
記貫通電極を覆うように形成したコンデンサネットワー
ク。
1. A strip-shaped ceramic substrate exhibiting electrical insulation, a plurality of independent through electrodes formed on the ceramic substrate , and a thick-film dielectric so that an area facing the through electrode is constant. The common electrode facing through the body layer
Wherein a capacitor element that is networked be on the ceramic substrate, wherein formed on the end face of the ceramic substrate, and a plurality of independent through electrode and the common electrode and a plurality of end surface electrode pairs respectively connected to Prepared, said
The thick-film dielectric layer is formed by leaving a part of both ends of the through electrode.
A capacitor network formed to cover the through electrode .
【請求項2】 電気絶縁性を示す短冊形のセラミック基
板と、前記セラミック基板の上に形成した下面共通電
極、この下面共通電極の上に形成した厚膜誘電体層、こ
の厚膜誘電体層の厚み方向の中央部を貫通する複数の独
立した貫通電極、およびこの貫通電極の上方に位置しか
つ前記厚膜誘電体層を介して厚膜誘電体層の上面に形成
した共通電極を含み、前記セラミック基板上にあってネ
ットワーク化されたコンデンサ要素と、前記セラミック
基板の端面に形成され、前記複数の独立した貫通電極と
前記下面共通電極および共通電極とにそれぞれ接続され
た複数の端面電極対とを備え、前記厚膜誘電体層は、前
記貫通電極の両端の一部を残して前記貫通電極を覆うよ
うに形成したコンデンサネットワーク。
2. A strip-shaped ceramic substrate having electrical insulation properties.
Plate and a lower common electrode formed on the ceramic substrate.
Pole, a thick dielectric layer formed on the lower common electrode,
Through the center of the thick dielectric layer in the thickness direction.
Standing through electrode, and position only above this through electrode
Formed on the upper surface of the thick dielectric layer via the thick dielectric layer
Including the common electrode,
Networked capacitor element and the ceramic
The plurality of independent through electrodes formed on the end face of the substrate;
Connected to the lower surface common electrode and the common electrode, respectively.
A plurality of end face electrode pairs, wherein the thick film dielectric layer is
The through-electrode is covered except a part of both ends of the through-electrode.
Formed capacitor network.
【請求項3】 セラミック基板は端面に規則的な凹凸を
有し、前記セラミック基板の端面の凹部か凸部のどちら
かに端面電極対を備えた請求項1記載のコンデンサネッ
トワーク。
3. The capacitor network according to claim 1, wherein the ceramic substrate has regular irregularities on an end face, and a pair of end face electrodes is provided on either a concave part or a convex part on the end face of the ceramic substrate.
【請求項4】 セラミック基板の長辺側の端面に貫通電
極と接続される信号用の端面電極対を備えるとともに、
前記セラミック基板の短辺側の端面に共通電極もしくは
下面共通電極および共通電極と接続されるアース端子用
の端面電極対を備えた請求項1または2記載のコンデン
サネットワーク。
4. A signal end face electrode pair connected to a through electrode on a long side end face of a ceramic substrate ,
A common electrode or a short-side end face of the ceramic substrate
The capacitor network according to claim 1, further comprising a lower surface common electrode and an end face electrode pair for a ground terminal connected to the common electrode .
JP10240591A 1991-05-08 1991-05-08 Capacitor network Expired - Lifetime JP3231350B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10240591A JP3231350B2 (en) 1991-05-08 1991-05-08 Capacitor network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10240591A JP3231350B2 (en) 1991-05-08 1991-05-08 Capacitor network

Publications (2)

Publication Number Publication Date
JPH04333208A JPH04333208A (en) 1992-11-20
JP3231350B2 true JP3231350B2 (en) 2001-11-19

Family

ID=14326534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10240591A Expired - Lifetime JP3231350B2 (en) 1991-05-08 1991-05-08 Capacitor network

Country Status (1)

Country Link
JP (1) JP3231350B2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104429A (en) * 1980-01-24 1981-08-20 Teiideiikei Eishiiai Kk Condenser array and method of manufacturing same
JPS57206016A (en) * 1981-06-12 1982-12-17 Tdk Electronics Co Ltd Chip type composite through condenser
JPH0620035B2 (en) * 1988-07-23 1994-03-16 ティーディーケイ株式会社 Manufacturing method of parts with multiple terminal electrodes
JPH0621227Y2 (en) * 1988-09-26 1994-06-01 株式会社村田製作所 Composite capacitor

Also Published As

Publication number Publication date
JPH04333208A (en) 1992-11-20

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