JPH06267791A - Noise filter block with varistor function - Google Patents
Noise filter block with varistor functionInfo
- Publication number
- JPH06267791A JPH06267791A JP5056736A JP5673693A JPH06267791A JP H06267791 A JPH06267791 A JP H06267791A JP 5056736 A JP5056736 A JP 5056736A JP 5673693 A JP5673693 A JP 5673693A JP H06267791 A JPH06267791 A JP H06267791A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- signal
- ground electrode
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Thermistors And Varistors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Filters And Equalizers (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、複数の信号線路におけ
る高周波ノイズを除去するためのノイズフィルタブロッ
クに関する。更に詳しくはコネクタ等に内蔵するに適
し、かつサージ電圧を吸収可能なバリスタ機能付きノイ
ズフィルタブロックに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise filter block for removing high frequency noise in a plurality of signal lines. More specifically, the present invention relates to a noise filter block with a varistor function, which is suitable for being built in a connector or the like and is capable of absorbing surge voltage.
【0002】[0002]
【従来の技術】コンピュータ等のデジタル機器では、信
号線路に高周波のノイズが混入すると誤動作を生じ易
く、しかも他の電子機器等に障害をもたらす恐れのある
不要な電磁波を配線から放射する問題点がある。このた
め、信号線路にはコンデンサ素子を用いた高周波ノイズ
を除去するノイズフィルタが多用されている。複数の信
号線路における高周波ノイズを除去するためのノイズフ
ィルタブロックとしては、金属製のアース板やシールド
ケースに形成された複数の取付孔にそれぞれ貫通コンデ
ンサをはんだ付けにより配列したものや、或いは印刷回
路基板にチップコンデンサをはんだ付けにより実装した
ものが知られている。2. Description of the Related Art In digital equipment such as computers, there is a problem that if electromagnetic waves of high frequency are mixed in a signal line, malfunctions are likely to occur, and that unnecessary electromagnetic waves that may damage other electronic equipment are radiated from wiring. is there. For this reason, a noise filter using a capacitor element for removing high frequency noise is often used in the signal line. As a noise filter block for removing high frequency noise in a plurality of signal lines, a feedthrough capacitor is arranged by soldering in a plurality of mounting holes formed in a metal ground plate or a shield case, or a printed circuit. It is known that a chip capacitor is mounted on a board by soldering.
【0003】一方、この種の信号線路には高周波ノイズ
が混入する以外にサージ電圧が印加されることがあるた
め、従来、高周波ノイズを除去し、同時にサージ電圧を
吸収し得る「高周波及びサージ吸収フィルタ」が開示さ
れている(特開平1−102874)。このフィルタで
は、容量性及びバリスタ特性をもつ誘電材料からなる平
板の一方の面に、電気信号伝達用の細長い信号線を設
け、他方の面のほぼ全体にアース電極を設け、前記信号
線とアース電極との間に分布定数型コンデンサ及びバリ
スタを形成している。On the other hand, since a surge voltage may be applied to this kind of signal line in addition to the mixing of high frequency noise, conventionally, high frequency noise can be removed and at the same time, surge voltage can be absorbed. A "filter" is disclosed (JP-A-1-102874). In this filter, an elongated signal line for transmitting an electric signal is provided on one surface of a flat plate made of a dielectric material having capacitive and varistor characteristics, and an earth electrode is provided on almost the other surface of the flat surface. Distributed constant type capacitors and varistors are formed between the electrodes.
【0004】[0004]
【発明が解決しようとする課題】しかし、上記貫通コン
デンサを用いたノイズフィルタブロックには、 複数の貫通コンデンサをアース板に取付けた場合、
貫通コンデンサの長さの分だけノイズフィルタブロック
が厚くなり、その薄型化が困難であり、また貫通コンデ
ンサの外径に相応して取付孔相互の間隔をあけなければ
ならず、信号線路の狭ピッチ化が困難であり、 コネクタに組込まれた状態で温度サイクル試験を実
施した場合、コネクタの絶縁性樹脂とアース板の熱膨張
率の違いにより、端子であるコネクタピンに応力が発生
し、このコネクタピンが挿通する貫通コンデンサに割れ
等が発生することがあり、 貫通コンデンサの静電容量の取得可能な範囲が狭く
限定される等の問題点があった。またチップコンデンサ
を用いたノイズフィルタブロックには、基板上の印刷パ
ターンの引き回しや、アース電極の構造により高周波ノ
イズを除去する性能が不十分であった。However, in a noise filter block using the above feedthrough capacitors, when a plurality of feedthrough capacitors are attached to the ground plate,
The noise filter block becomes thicker by the length of the feedthrough capacitor, making it difficult to make it thinner.In addition, the mounting holes must be spaced in accordance with the outer diameter of the feedthrough capacitor, and the narrow pitch of the signal line. However, when the temperature cycle test is carried out with the connector built into the connector, the difference in the coefficient of thermal expansion between the insulating resin of the connector and the ground plate causes stress on the connector pin, which is the terminal. There is a problem that the feedthrough capacitor through which the pin is inserted may be cracked, and the range in which the capacitance of the feedthrough capacitor can be acquired is limited. Further, the noise filter block using the chip capacitor is insufficient in the ability to route the printed pattern on the substrate and the structure of the ground electrode to remove high frequency noise.
【0005】更に特開平1−102874号公報に示さ
れる「高周波及びサージ吸収フィルタ」はセラミック基
板のような誘電体にコンデンサとしての役割のみなら
ず、バリスタとしての役割を同時に求めているため、所
望の効果を得ようとすると、セラミック基板の構造や組
成を厳格に規定しなければならず、しかも上記貫通コン
デンサと同様に静電容量の取得可能な範囲が狭く限定さ
れ、ノイズ遮断特性を改善するためにフェライト板やフ
ェライトビーズなどを必要とする不具合があった。Further, the "high frequency and surge absorption filter" disclosed in Japanese Patent Application Laid-Open No. Hei 1-102874 requires not only a role as a capacitor but also a role as a varistor for a dielectric such as a ceramic substrate. In order to obtain the effect of, the structure and composition of the ceramic substrate must be rigorously specified, and the range in which the electrostatic capacitance can be acquired is narrowed like the feedthrough capacitor, improving the noise blocking characteristics. Therefore, there was a problem that a ferrite plate or ferrite beads were required.
【0006】本発明の目的は、全体形状を薄型にし、か
つ信号線路間のピッチを狭くして小型化でき、温度サイ
クル試験を実施しても割れ等の発生がないノイズフィル
タブロックを提供することにある。本発明の別の目的
は、簡単な構造で、静電容量の取得範囲が広く、十分に
高周波ノイズを除去でき、併せてサージ電圧を吸収でき
るバリスタ機能付きノイズフィルタブロックを提供する
ことにある。An object of the present invention is to provide a noise filter block which has a thin overall shape and can be miniaturized by narrowing a pitch between signal lines and which is free from cracks or the like even when a temperature cycle test is carried out. It is in. Another object of the present invention is to provide a noise filter block with a varistor function, which has a simple structure, has a wide range of capacitance acquisition, can sufficiently remove high frequency noise, and can also absorb surge voltage.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
の本発明の構成を、実施例に対応する図1を用いて説明
する。本発明のバリスタ機能付きノイズフィルタブロッ
ク10は、複数の端子挿入用孔12が所定の間隔をあけ
て設けられた絶縁性基板11と、この基板11の孔周縁
の表面に孔の内面の内面電極12aに連続して形成され
た信号用電極14と、この信号用電極14と所定の絶縁
間隙15をあけて基板11の表面に形成された第1アー
ス電極16と、孔12の内面の内面電極12aと所定の
絶縁間隙18をあけて基板11の裏面に形成され第1ア
ース電極16に電気的に接続された第2アース電極17
と、ベアチップ19a両端に設けられた一対の端子電極
19b,19cを信号用電極14と第1アース電極16
にそれぞれ接続するように基板表面の信号用電極14と
第1アース電極16との間に架設されたチップコンデン
サ19と、ベアチップ29a両端に設けられた一対の端
子電極29b,29cを信号用電極14と第1アース電
極16にそれぞれ接続するように基板表面の信号用電極
14と第1アース電極16との間に架設されたチップバ
リスタ29とを備える。A configuration of the present invention for achieving the above object will be described with reference to FIG. 1 corresponding to an embodiment. The noise filter block 10 with a varistor function of the present invention includes an insulating substrate 11 having a plurality of terminal insertion holes 12 provided at predetermined intervals, and an inner surface electrode on the inner surface of the hole on the peripheral surface of the substrate 11. 12a, a signal electrode 14 continuously formed on the substrate 12a, a first ground electrode 16 formed on the surface of the substrate 11 with a predetermined insulating gap 15 from the signal electrode 14, and an inner electrode on the inner surface of the hole 12. A second ground electrode 17 formed on the back surface of the substrate 11 with a predetermined insulating gap 18 between the second ground electrode 12a and the first ground electrode 16a.
And a pair of terminal electrodes 19b and 19c provided at both ends of the bare chip 19a are connected to the signal electrode 14 and the first ground electrode 16 respectively.
The chip capacitor 19 provided between the signal electrode 14 on the substrate surface and the first ground electrode 16 so as to be connected to the signal electrode 14 and the pair of terminal electrodes 29b and 29c provided at both ends of the bare chip 29a are connected to the signal electrode 14 respectively. And a chip varistor 29 installed between the signal electrode 14 on the substrate surface and the first ground electrode 16 so as to be respectively connected to the first ground electrode 16.
【0008】[0008]
【作用】複数の端子挿入用孔12にコネクタピンのよう
な信号線路Pを挿入し、これらの信号線路Pを基板表面
の信号用電極14にそれぞれ接続するとともに、基板裏
面の第2アース電極17をアース用シールドケースのア
ース電極に接続する。チップコンデンサ19により僅か
なスペースで大きな静電容量が得られるため、ノイズフ
ィルタブロック10を小型で薄くすることができるとと
もに、このブロック10によりコネクタに実装した後の
アース側に発生する残留インダクタンスを極めて小さく
抑えることができ、しかも各信号線路を通る信号の高周
波ノイズを一括して確実に除去することができる。また
信号線路Pにサージ電圧が印加された場合には、チップ
バリスタ29により信号用電極14とアース電極16,
17が導通し、サージ電流をアース電極16,17を介
してシールドケースのアース電極に流して、信号線路P
に接続された電子機器を保護する。The signal lines P such as connector pins are inserted into the plurality of terminal insertion holes 12, the signal lines P are connected to the signal electrodes 14 on the front surface of the substrate, and the second ground electrode 17 on the rear surface of the substrate is connected. To the ground electrode of the ground shield case. Since the chip capacitor 19 can provide a large electrostatic capacity in a small space, the noise filter block 10 can be made small and thin, and the residual inductance generated on the ground side after being mounted on the connector can be extremely reduced by the block 10. It can be suppressed to a small value, and high-frequency noise of the signal passing through each signal line can be collectively and reliably removed. When a surge voltage is applied to the signal line P, the chip varistor 29 causes the signal electrode 14 and the ground electrode 16,
17 conducts, and a surge current flows through the earth electrodes 16 and 17 to the earth electrode of the shield case, and the signal line P
Protect electronic devices connected to.
【0009】[0009]
【実施例】次に本発明の実施例を図面に基づいて詳しく
説明する。図1〜図4は本発明第1実施例バリスタ機能
付きノイズフィルタブロック10を示す。図1〜図4に
示すように、絶縁性基板であるガラスエポキシ基板11
の両面に薄い銅箔を貼付けた銅張積層板を出発材料と
し、不要な部分をエッチングで取去ることにより、信号
用電極14、第1及び第2アース電極16,17を形成
した。即ち、銅張基板11の中央には4個の端子挿入用
孔12を、また基板11の両端縁近傍には10個のスル
ーホール13をそれぞれ等間隔に設けた。孔12及びス
ルーホール13の各内面には銅めっきにより内面電極1
2a及び13aを形成した。Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 4 show a noise filter block 10 with a varistor function according to the first embodiment of the present invention. As shown in FIGS. 1 to 4, a glass epoxy substrate 11 which is an insulating substrate.
As a starting material, a copper clad laminate having thin copper foils attached to both surfaces thereof was used to remove unnecessary portions by etching to form signal electrodes 14, and first and second ground electrodes 16 and 17. That is, four terminal insertion holes 12 were provided at the center of the copper-clad substrate 11, and ten through holes 13 were provided at equal intervals in the vicinity of both edges of the substrate 11. The inner surface of each of the holes 12 and the through holes 13 is plated with copper to form an inner electrode 1.
2a and 13a were formed.
【0010】基板11の表面では孔12を中心とする円
形状の信号用電極14及びこの周囲の第1アース電極1
6の部分に、間隙15を残してレジストが印刷され、基
板11の裏面では孔12の周囲の間隙18を残して第2
アース電極17の部分に、それぞれレジストが印刷され
た。エッチング処理して間隙15と間隙18の部分の銅
箔を除去した。この結果、信号用電極14が基板11の
孔周縁の表面に孔12の内面の内面電極12aに連続し
て形成され、第1アース電極16はこの信号用電極14
を囲んでかつ電極14と所定の絶縁間隙15をあけて形
成された。また基板11の裏面には第2アース電極17
が孔12の内面の内面電極12aを囲んでかつ電極12
aと所定の絶縁間隙18をあけて形成され、この第2ア
ース電極17はスルーホール13の内面の内面電極13
aを介して第1アース電極16に電気的に接続された。
基板11の表面の信号用電極14と第1アース電極16
との間には、信号用電極1個当りチップコンデンサ19
とチップバリスタ29が1個ずつ架設される。チップコ
ンデンサ19の架設は、そのベアチップ19aの両端に
設けられた一対の端子電極19b,19cを信号用電極
14と第1アース電極16にそれぞれはんだ付けするこ
とにより、行われる。チップコンデンサ19はチップ型
積層セラミックコンデンサであって、ベアチップ19a
は内部電極とチタン酸バリウム系又は鉛系の誘電体層を
交互に積層した後、焼成して得られた焼結体である。端
子電極19b,19cはAgを含む導電性ペーストをベ
アチップの両端面に塗布後、焼付けて形成され、端子電
極表面にはんだめっきが施される。On the surface of the substrate 11, a circular signal electrode 14 centered on the hole 12 and the first ground electrode 1 around the signal electrode 14 are provided.
The resist is printed on the portion 6 at a gap 15 and the second portion is formed on the back surface of the substrate 11 at a gap 18 around the hole 12.
A resist was printed on each of the ground electrodes 17. The copper foil in the gaps 15 and 18 was removed by etching. As a result, the signal electrode 14 is continuously formed on the surface of the peripheral edge of the hole of the substrate 11 with the inner surface electrode 12a of the inner surface of the hole 12, and the first ground electrode 16 is the signal electrode 14
The electrode 14 and the electrode 14 are formed with a predetermined insulating gap 15 therebetween. The second earth electrode 17 is formed on the back surface of the substrate 11.
Surround the inner surface electrode 12a on the inner surface of the hole 12 and
The second ground electrode 17 is formed with a predetermined insulating gap 18 between the inner surface electrode 13 and the inner surface electrode 13 of the through hole 13.
It was electrically connected to the first ground electrode 16 via a.
The signal electrode 14 and the first ground electrode 16 on the surface of the substrate 11
Between the chip electrodes and the chip capacitor 19 for each signal electrode.
And one chip varistor 29 are installed. The chip capacitor 19 is installed by soldering the pair of terminal electrodes 19b and 19c provided at both ends of the bare chip 19a to the signal electrode 14 and the first ground electrode 16, respectively. The chip capacitor 19 is a chip type monolithic ceramic capacitor, and is a bare chip 19a.
Is a sintered body obtained by alternately stacking internal electrodes and barium titanate-based or lead-based dielectric layers and then firing. The terminal electrodes 19b and 19c are formed by applying a conductive paste containing Ag to both end surfaces of the bare chip and then baking it, and the surface of the terminal electrodes is subjected to solder plating.
【0011】またチップバリスタ29の架設は、そのベ
アチップ29aの両端に設けられた一対の端子電極29
b,29cを信号用電極14と第1アース電極16にそ
れぞれはんだ付けすることにより、行われる。チップバ
リスタ29はチップ型積層セラミックバリスタであっ
て、ベアチップ29aは内部電極と酸化亜鉛系のバリス
タ層を交互に積層した後、焼成して得られた焼結体であ
る。端子電極29b,29cは端子電極19b,19c
と同様に形成される。Further, the chip varistor 29 is installed by arranging a pair of terminal electrodes 29 provided at both ends of the bare chip 29a.
This is performed by soldering b and 29c to the signal electrode 14 and the first ground electrode 16, respectively. The chip varistor 29 is a chip-type multilayer ceramic varistor, and the bare chip 29a is a sintered body obtained by alternately stacking internal electrodes and zinc oxide based varistor layers and then firing. The terminal electrodes 29b and 29c are the terminal electrodes 19b and 19c.
Is formed similarly to.
【0012】このように構成されたバリスタ機能付きノ
イズフィルタブロック10を例えばコネクタ(図示せ
ず)に内蔵する場合について説明する。4個の端子挿入
用孔12に信号線路である4本のコネクタピンP(図
1)をそれぞれ挿入し、これらのコネクタピンPを内面
電極12aに、また基板11の裏面の第2アース電極1
7をアース用シールドケース(図示せず)にそれぞれは
んだ付けにより電気的に接続する。コネクタピンPは内
面電極12a、信号用電極14及びチップコンデンサ1
9又はチップバリスタ29を介してアース電極16,1
7に接続される。チップコンデンサ19により僅かなス
ペースで大きな静電容量が得られるため、ノイズフィル
タブロック10を小型で薄くすることができるととも
に、このブロック10によりコネクタに実装した後のア
ース側に発生する残留インダクタンスを極めて小さく抑
えることができ、しかも各信号線路を通る信号の高周波
ノイズを一括して確実に除去することができる。またチ
ップバリスタ29により、信号線路Pにサージ電圧が印
加された場合には、信号用電極14とアース電極16,
17が導通し、サージ電流をアース電極16,17を介
してシールドケースのアース電極に流して、信号線路P
に接続された電子機器を保護する。A case will be described in which the noise filter block 10 with a varistor function configured as described above is built in, for example, a connector (not shown). Four connector pins P (FIG. 1), which are signal lines, are inserted into the four terminal insertion holes 12, and these connector pins P are used as the inner surface electrode 12a and the second ground electrode 1 on the back surface of the substrate 11.
7 are electrically connected to a ground shield case (not shown) by soldering. The connector pin P is the inner surface electrode 12a, the signal electrode 14 and the chip capacitor 1.
9 or the ground electrode 16, 1 via the chip varistor 29
Connected to 7. Since the chip capacitor 19 can provide a large electrostatic capacity in a small space, the noise filter block 10 can be made small and thin, and the residual inductance generated on the ground side after being mounted on the connector can be extremely reduced by the block 10. It can be suppressed to a small value, and high-frequency noise of the signal passing through each signal line can be collectively and reliably removed. When a surge voltage is applied to the signal line P by the chip varistor 29, the signal electrode 14 and the ground electrode 16,
17 conducts, and a surge current flows through the earth electrodes 16 and 17 to the earth electrode of the shield case, and the signal line P
Protect electronic devices connected to.
【0013】図5〜図8は本発明第2実施例バリスタ機
能付きノイズフィルタブロック20を示す。図1〜図4
と同一符号は同一構成部品を示す。この例の特徴ある構
成は、第1実施例のスルーホール13を設ける代わり
に、絶縁性基板11の両端面に端面電極21が形成さ
れ、第1アース電極16と第2アース電極17が、内面
電極13aの代わりに端面電極21を介して電気的に接
続されたことにある。この例では絶縁性基板11として
アルミナセラミックス基板を用いた。基板11の中央に
第1実施例と同様に4個の端子挿入用孔12を等間隔に
設けた。これらの孔12の内面にはスルーホール印刷に
より内面電極12aを形成した。基板11の表面に信号
用電極14及び第1アース電極16をAg又はAg/P
dなどを含む導電性ペーストをスクリーン印刷して形成
した。即ち、信号用電極14は基板11の孔周縁の表面
にこれらの孔12の内面の内面電極12aに連続して円
形状に形成され、第1アース電極16はこの信号用電極
14を囲んでかつ電極14と所定の絶縁間隙15をあけ
て形成された。5 to 8 show a noise filter block 20 with a varistor function according to a second embodiment of the present invention. 1 to 4
The same reference numerals denote the same components. The characteristic structure of this example is that, instead of providing the through holes 13 of the first embodiment, end face electrodes 21 are formed on both end faces of the insulating substrate 11, and the first ground electrode 16 and the second ground electrode 17 are formed on the inner surface. It is electrically connected via the end face electrode 21 instead of the electrode 13a. In this example, an alumina ceramic substrate was used as the insulating substrate 11. Similar to the first embodiment, four terminal insertion holes 12 were provided at the center of the substrate 11 at equal intervals. Inner electrodes 12a were formed on the inner surfaces of these holes 12 by through-hole printing. The signal electrode 14 and the first ground electrode 16 are Ag or Ag / P on the surface of the substrate 11.
It was formed by screen-printing a conductive paste containing d and the like. That is, the signal electrode 14 is formed in a circular shape on the surface of the peripheral edge of the hole of the substrate 11 so as to be continuous with the inner electrode 12a on the inner surface of the hole 12, and the first ground electrode 16 surrounds the signal electrode 14 and The electrode 14 and the electrode 14 are formed with a predetermined insulating gap 15.
【0014】基板11の裏面に第2アース電極17を上
記と同じ導電性ペーストをスクリーン印刷して形成し
た。更に基板11の端面に導電性ペーストをコーティン
グして焼付け端面電極21を形成した。これにより、第
2アース電極17は孔12の内面の内面電極12aを囲
んでかつ電極12aと所定の絶縁間隙18をあけて形成
され、第2アース電極17が端面電極21を介して第1
アース電極16に電気的に接続された。基板11の表面
の信号用電極14と第1アース電極16との間には、第
1実施例と同様にチップコンデンサ19及びチップバリ
スタ29が架設された。このノイズフィルタブロック2
0の使用方法及び特性は前記第1実施例と同様であるの
で繰り返しの説明を省略する。A second ground electrode 17 was formed on the back surface of the substrate 11 by screen printing the same conductive paste as above. Further, the end face of the substrate 11 was coated with a conductive paste to form a baked end face electrode 21. As a result, the second ground electrode 17 is formed so as to surround the inner surface electrode 12a on the inner surface of the hole 12 and to leave a predetermined insulating gap 18 from the electrode 12a, and the second ground electrode 17 is provided with the first surface electrode 21 via the end surface electrode 21.
It was electrically connected to the ground electrode 16. A chip capacitor 19 and a chip varistor 29 were provided between the signal electrode 14 and the first ground electrode 16 on the surface of the substrate 11 as in the first embodiment. This noise filter block 2
The use method and characteristics of 0 are the same as those in the first embodiment, and thus the repeated description will be omitted.
【0015】なお、上記例では絶縁性基板としてガラス
エポキシ基板及びアルミナセラミックス基板を示した
が、耐熱性のある、機械的強度の高い絶縁性基板であれ
ば、他の基板を用いてもよい。また、信号用電極の形状
は円形に限らず、角形、楕円形など他の形状でもよい。
また、チップコンデンサ及びチップコンデンサを信号用
電極1個当り1個ずつ設けたが、この数は一例であっ
て、除去する周波数範囲に応じてチップコンデンサを2
個以上設けてもよく、或いは除去する周波数範囲に応じ
て静電容量を変えてもよい。またチップバリスタは必要
とするサージ耐量に応じて2個以上設けてもよい。更
に、端子挿入用孔の数、又はスルーホールの数は一例で
あって、上記例に限るものではない。Although the glass epoxy substrate and the alumina ceramics substrate are shown as the insulating substrate in the above example, other substrates may be used as long as they are heat resistant and have high mechanical strength. Further, the shape of the signal electrode is not limited to a circular shape, but may be another shape such as a square shape or an elliptical shape.
Further, one chip capacitor and one chip capacitor are provided for each signal electrode, but this number is an example, and two chip capacitors are provided according to the frequency range to be removed.
One or more pieces may be provided, or the capacitance may be changed according to the frequency range to be removed. Two or more chip varistors may be provided depending on the surge withstand capability required. Furthermore, the number of terminal insertion holes or the number of through holes is an example, and is not limited to the above example.
【0016】[0016]
【発明の効果】以上述べたように、本発明によれば、以
下の優れた効果を奏する。 (a) コンデンサ素子として従来の貫通コンデンサの代わ
りにチップコンデンサを用いるため、信号線路間を狭ピ
ッチ化でき、ノイズフィルタブロックの小型化、薄型化
が可能となり、これを内蔵するフィルタコネクタの小型
化が可能となる。 (b) コネクタ等に装着した後、コネクタピン等の端子に
荷重を加えてもコンデンサ素子であるチップコンデンサ
及びサージ吸収素子であるチップバリスタには直接荷重
がかからないため、これらのチップ電子部品を損傷させ
ることがない。また温度サイクル試験を実施しても割れ
等の発生がない。As described above, the present invention has the following excellent effects. (a) Since a chip capacitor is used as the capacitor element instead of the conventional feedthrough capacitor, the pitch between signal lines can be narrowed, and the noise filter block can be made smaller and thinner, and the filter connector incorporating this can be made smaller. Is possible. (b) Even if a load is applied to the terminals such as connector pins after mounting on a connector, etc., the chip capacitor, which is a capacitor element, and the chip varistor, which is a surge absorbing element, are not directly loaded. There is nothing to do. Moreover, even if a temperature cycle test is performed, no cracks or the like occur.
【0017】(c) チップコンデンサを搭載しているた
め、従来の貫通コンデンサと比べて静電容量の取得範囲
が広く、十分に高周波ノイズを除去できるとともに、チ
ップコンデンサを複数個搭載し、例えば高周波用、低周
波用のチップコンデンサを組合せれば、広い周波数範囲
のノイズ対策が可能となる。 (d) 絶縁性基板の表面及び裏面にそれぞれ第1及び第2
アース電極を設けて、基板端面又はスルーホールにより
両アース電極を電気的に接続するため、コネクタ等のア
ース用シールドケースに取り付けた場合、シールド効果
が高いとともに、アース側に発生する残留インダクタン
スが抑えられ、高周波除去効果に優れている。 (e) チップバリスタを搭載しているため、信号線路にサ
ージ電圧が印加された場合には、サージ電流をシールド
ケースのアース電極に流して信号線路に接続された電子
機器を保護する。 (f) 特に本発明のフィルタブロックはノイズ除去とサー
ジ吸収とをそれぞれ専用のチップ電子部品で行うため、
所望の効果を得るための設計及び製造が簡単であり、複
雑な構造にすることなく確実に両機能を果たすことがで
きる。(C) Since a chip capacitor is mounted, the capacitance acquisition range is wider than that of a conventional feedthrough capacitor, and high-frequency noise can be sufficiently removed. By combining a chip capacitor for high frequency and low frequency, it is possible to take measures against noise in a wide frequency range. (d) First and second on the front and back of the insulating substrate, respectively.
Since a ground electrode is provided and both ground electrodes are electrically connected by the end face of the board or through holes, when installed in a ground shield case such as a connector, the shield effect is high and the residual inductance generated on the ground side is suppressed. And is excellent in high frequency removal effect. (e) Since a chip varistor is installed, when a surge voltage is applied to the signal line, a surge current is passed through the earth electrode of the shield case to protect the electronic equipment connected to the signal line. (f) In particular, since the filter block of the present invention performs noise removal and surge absorption by dedicated chip electronic components,
It is easy to design and manufacture to obtain a desired effect, and can reliably perform both functions without making a complicated structure.
【図1】本発明第1実施例のバリスタ機能付きノイズフ
ィルタブロックの図2のA−A線断面図。FIG. 1 is a sectional view taken along line AA of FIG. 2 of a noise filter block with a varistor function according to a first embodiment of the present invention.
【図2】その平面図。FIG. 2 is a plan view thereof.
【図3】その外観斜視図。FIG. 3 is an external perspective view thereof.
【図4】その反転した外観斜視図。FIG. 4 is an inverted perspective view of the same.
【図5】本発明第2実施例のバリスタ機能付きノイズフ
ィルタブロックの図6のB−B線断面図。5 is a sectional view taken along line BB of FIG. 6 of the noise filter block with a varistor function according to the second embodiment of the present invention.
【図6】その平面図。FIG. 6 is a plan view thereof.
【図7】その外観斜視図。FIG. 7 is an external perspective view thereof.
【図8】その反転した外観斜視図。FIG. 8 is an inverted perspective view of the same.
P コネクタピン(信号線路) 10,20 バリスタ機能付きノイズフィルタブロック 11 絶縁性基板 12 端子挿入用孔 12a,13a 内面電極 13 スルーホール 14 信号用電極 15,18 絶縁間隙 16 第1アース電極 17 第2アース電極 19 チップコンデンサ 19a ベアチップ 19b,19c 端子電極 21 端面電極 29 チップバリスタ 29a ベアチップ 29b,29c 端子電極 P Connector pin (Signal line) 10, 20 Noise filter block with varistor function 11 Insulating substrate 12 Terminal insertion hole 12a, 13a Inner surface electrode 13 Through hole 14 Signal electrode 15,18 Insulation gap 16 First earth electrode 17 Second Ground electrode 19 Chip capacitor 19a Bare chip 19b, 19c Terminal electrode 21 End surface electrode 29 Chip varistor 29a Bare chip 29b, 29c Terminal electrode
Claims (3)
あけて設けられた絶縁性基板(11)と、 前記基板(11)の孔周縁の表面に前記孔(12)の内面の内面
電極(12a)に連続して形成された信号用電極(14)と、 前記信号用電極(14)と所定の絶縁間隙(15)をあけて前記
基板(11)の表面に形成された第1アース電極(16)と、 前記孔(12)の内面の内面電極(12a)と所定の絶縁間隙(1
8)をあけて前記基板(11)の裏面に形成され前記第1アー
ス電極(16)に電気的に接続された第2アース電極(17)
と、 ベアチップ(19a)両端に設けられた一対の端子電極(19b,
19c)を前記信号用電極(14)と前記第1アース電極(16)に
それぞれ接続するように前記基板(11)の表面の前記信号
用電極(14)と前記第1アース電極(16)との間に架設され
たチップコンデンサ(19)と、 ベアチップ(29a)両端に設けられた一対の端子電極(29b,
29c)を前記信号用電極(14)と前記第1アース電極(16)に
それぞれ接続するように前記基板(11)の表面の前記信号
用電極(14)と前記第1アース電極(16)との間に架設され
たチップバリスタ(29)とを備えたバリスタ機能付きノイ
ズフィルタブロック。1. An insulative substrate (11) having a plurality of terminal insertion holes (12) provided at predetermined intervals, and an inner surface of the hole (12) on a surface of a hole periphery of the substrate (11). A signal electrode (14) continuously formed on the inner surface electrode (12a) of the electrode, and a predetermined insulating gap (15) from the signal electrode (14) formed on the surface of the substrate (11). A predetermined insulation gap (1) is formed between the first ground electrode (16) and the inner electrode (12a) on the inner surface of the hole (12).
A second ground electrode (17) which is formed on the back surface of the substrate (11) by opening 8) and is electrically connected to the first ground electrode (16).
And a pair of terminal electrodes (19b, 19b) provided on both ends of the bare chip (19a).
19c) is connected to the signal electrode (14) and the first ground electrode (16) respectively, and the signal electrode (14) and the first ground electrode (16) on the surface of the substrate (11) are connected to each other. Between the chip capacitor (19) and the pair of terminal electrodes (29b, 29b) provided on both ends of the bare chip (29a).
29c) is connected to the signal electrode (14) and the first ground electrode (16) respectively, and the signal electrode (14) and the first ground electrode (16) on the surface of the substrate (11) are connected to each other. A noise filter block with a varistor function that includes a chip varistor (29) installed between the two.
3)が設けられ、第1アース電極(16)と第2アース電極(1
7)が前記スルーホール(13)の内面電極(13a)を介して電
気的に接続された請求項1記載のバリスタ機能付きノイ
ズフィルタブロック。2. A plurality of through holes (1) in an insulating substrate (11).
3) is provided, and the first ground electrode (16) and the second ground electrode (1
The noise filter block with a varistor function according to claim 1, wherein 7) is electrically connected through an inner electrode (13a) of the through hole (13).
形成され、第1アース電極(16)と第2アース電極(17)が
前記端面電極(21)を介して電気的に接続された請求項1
記載のバリスタ機能付きノイズフィルタブロック。3. An end surface electrode (21) is formed on an end surface of an insulating substrate (11), and a first ground electrode (16) and a second ground electrode (17) are electrically connected via the end surface electrode (21). Claim 1 connected to
Noise filter block with varistor function described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5056736A JP3061092B2 (en) | 1993-03-17 | 1993-03-17 | Noise filter block with varistor function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5056736A JP3061092B2 (en) | 1993-03-17 | 1993-03-17 | Noise filter block with varistor function |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06267791A true JPH06267791A (en) | 1994-09-22 |
JP3061092B2 JP3061092B2 (en) | 2000-07-10 |
Family
ID=13035809
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5056736A Expired - Lifetime JP3061092B2 (en) | 1993-03-17 | 1993-03-17 | Noise filter block with varistor function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3061092B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010283069A (en) * | 2009-06-03 | 2010-12-16 | Hitachi Ltd | Electronic device and method for measuring noise current |
KR101334291B1 (en) * | 2012-06-13 | 2013-11-29 | 주식회사 세모스 | Emi connector filter |
CN111816443A (en) * | 2020-05-11 | 2020-10-23 | 北京七星飞行电子有限公司 | High-temperature ceramic plate type array capacitor and preparation method thereof |
WO2024038394A1 (en) * | 2022-08-19 | 2024-02-22 | Alcon Inc. | Vga monitor emulating printed circuit board |
-
1993
- 1993-03-17 JP JP5056736A patent/JP3061092B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010283069A (en) * | 2009-06-03 | 2010-12-16 | Hitachi Ltd | Electronic device and method for measuring noise current |
KR101334291B1 (en) * | 2012-06-13 | 2013-11-29 | 주식회사 세모스 | Emi connector filter |
CN111816443A (en) * | 2020-05-11 | 2020-10-23 | 北京七星飞行电子有限公司 | High-temperature ceramic plate type array capacitor and preparation method thereof |
WO2024038394A1 (en) * | 2022-08-19 | 2024-02-22 | Alcon Inc. | Vga monitor emulating printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JP3061092B2 (en) | 2000-07-10 |
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