JPH08265084A - Chip filter - Google Patents

Chip filter

Info

Publication number
JPH08265084A
JPH08265084A JP6592395A JP6592395A JPH08265084A JP H08265084 A JPH08265084 A JP H08265084A JP 6592395 A JP6592395 A JP 6592395A JP 6592395 A JP6592395 A JP 6592395A JP H08265084 A JPH08265084 A JP H08265084A
Authority
JP
Japan
Prior art keywords
corner
internal electrode
electrode
internal
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6592395A
Other languages
Japanese (ja)
Inventor
Paakaa Baakusu Daanaru
ダーナル・パーカー・バークス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6592395A priority Critical patent/JPH08265084A/en
Publication of JPH08265084A publication Critical patent/JPH08265084A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To mount a very small sized form of one chip onto a printed circuit board with high density through the provision of an RC or an LC function. CONSTITUTION: First to 4th internal electrodes 1-14 are provided in the inside of a bare chip 16 made of a rectangular ceramic dielectric material, and 1st and 2nd internal electrodes 11, 12 appear respectively at a 1st corner 16a and a 2nd corner of the pair chip 16 and 3rd and 4th internal electrodes 13, 14 appear respectively at a 3rd corner 16c and a 4th corner. A 1st resistive layer 21 is formed from the 1st corner 16a and the 2nd corner on the surface of the bare chip 16 and the 2nd resistive layer 22 is formed over the 2nd and 4th corners on the rear side of the bare chip 16. A 1st external electrode 31 electrically connected with the 1st internal electrode 11 and the 1st resistive layer 21, a 2nd external electrode electrically connected with the 1st and 2nd resistive layers 21, 22 and the 2nd internal electrode 12, a ground electrode in continuity with the 3rd external electrode 13, a 3rd external electrode electrically connected with a 4th internal electrode 14 and the 2nd resistive layer 22 are baked respectively to the 1st to 4th corners.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント回路基板の表
面に実装可能なチップ型フィルタに関する。更に詳しく
は低域フィルタ、高域フィルタ、その他のフィルタに適
するチップ型フィルタに適するチップ型フィルタに関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type filter mountable on the surface of a printed circuit board. More specifically, the present invention relates to a chip-type filter suitable for a low-pass filter, a high-pass filter, and a chip-type filter suitable for other filters.

【0002】[0002]

【従来の技術】1950年代の初期から厚膜回路基板は
商業的に製造されてきている。この回路製品はセラミッ
ク基板上にスクリーン印刷によって形成された抵抗体の
ネットワークに基づいていた。この回路の抵抗体は炭素
系の組成であり、導電体はAgであり、基板はアルミナ
又はステアタイトであった。基板をBaTiO3又はこ
れに近い高い比誘電率を有する誘電体で作ると、誘電体
である基板がコンデンサになってRC(抵抗の抵抗値
R、コンデンサの容量C)回路を作り得ることがその後
まもなく見い出された。そして抵抗体パターンをコンデ
ンサ上に位置させれば、連続的に静電容量が変化するた
め、分布した(distributed)RC機能が得られること
が判明した。このRCの分布したネットワークは高周波
フィルタとして有用で別々のRとCの部品より構成され
たフィルタでは得られない特性を有することが明らかに
なった。特筆すべきことは、これらの製品は誘電体のセ
ラミック基板をコンデンサとして用い、表面に形成した
抵抗パターンと基板内部で接続する構造を持つ導電体回
路から構成されていたことである。後に薄膜技術が同様
な目的のために用いられた。例えばRCネットワークを
作るためにTa/Ta25の技術が開発され、Ta25
を誘電体として用い、これらのいくつかは分布したRC
型の機能があった。
BACKGROUND OF THE INVENTION Thick film circuit boards have been manufactured commercially since the early 1950s. This circuit product was based on a network of resistors formed by screen printing on a ceramic substrate. The resistor of this circuit had a carbon-based composition, the conductor was Ag, and the substrate was alumina or steatite. If the substrate is made of BaTiO 3 or a dielectric having a high relative dielectric constant close to BaTiO 3 , the substrate that is the dielectric becomes a capacitor, and an RC (resistance value R of the resistor, capacitance C of the capacitor) circuit can be made thereafter. Soon found. It has been found that if the resistor pattern is placed on the capacitor, the capacitance is continuously changed, so that the distributed RC function can be obtained. It has been found that this RC distributed network has properties that are useful as high frequency filters and cannot be obtained with filters composed of separate R and C components. It should be noted that these products used a dielectric ceramic substrate as a capacitor, and were composed of a resistance pattern formed on the surface and a conductor circuit having a structure for connection inside the substrate. Later thin film technology was used for similar purposes. For example, Ta / Ta 2 O 5 technology was developed to create RC networks, and Ta 2 O 5
As the dielectric, some of these are distributed RC
There was a type feature.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来のR
Cフィルタは誘電体が基板であって、比較的大型である
ため、プリント回路基板に実装するには不適であり、基
板表面実装用のチップ形状をなしていなかった。本発明
の目的は、1チップの極めて小型の形態で、RC又はL
C(インダクタのインダクタンスL、コンデンサの容量
C)の機能を有し、高密度にプリント回路基板に実装し
得るチップ型フィルタを提供することにある。
However, the conventional R
Since the C filter has a substrate made of a dielectric material and is relatively large, it is not suitable for mounting on a printed circuit board, and has not been formed into a chip shape for surface mounting on a substrate. It is an object of the invention to provide RC or L
It is intended to provide a chip type filter having a function of C (inductance L of inductor, capacitance C of capacitor) and capable of being mounted on a printed circuit board at high density.

【0004】[0004]

【課題を解決するための手段】図1〜図6に示すよう
に、本発明の第1のチップ型フィルタ10は、矩形のセ
ラミック誘電体により構成され、チップ内部に第1内部
電極11と第2内部電極12と第3内部電極13と第4
内部電極14が設けられ、第1隅部16aに第1内部電
極11が現れるように形成され、第2隅部16bに第2
内部電極12が現れるように形成され、第3隅部16c
に第1及び第2内部電極11,12とセラミック誘電体
を介して対向する第3内部電極13が現れるように形成
され、第4隅部16dに第3内部電極13とセラミック
誘電体を介して対向する第4内部電極14が現れるよう
に形成されたベアチップ16と、ベアチップ16の表面
の第1隅部16aと第2隅部16bにかけてかつ第1及
び第2内部電極11,12とセラミック誘電体を介して
対向するように形成された第1抵抗層21と、ベアチッ
プ16の裏面の第2隅部16bと第4隅部16dにかけ
てかつ第4内部電極14とセラミック誘電体を介して対
向するように形成された第2抵抗層22と、ベアチップ
16の第1隅部16aに第1内部電極11及び第1抵抗
層21にそれぞれ導通するように焼付けられた第1外部
電極31と、ベアチップ16の第2隅部16bに第1抵
抗層21と第2内部電極12と第2抵抗層22にそれぞ
れ導通するように焼付けられた第2外部電極32と、ベ
アチップ16の第3隅部16cに第3内部電極13に導
通するように焼付けられた接地電極17と、ベアチップ
16の第4隅部16dに第4内部電極14及び第2抵抗
層22にそれぞれ導通するように焼付けられた第3外部
電極33とを備えたものである。
As shown in FIGS. 1 to 6, a first chip type filter 10 of the present invention is made of a rectangular ceramic dielectric material, and has a first internal electrode 11 and a first internal electrode 11 inside the chip. 2 internal electrode 12, 3rd internal electrode 13 and 4th
The internal electrode 14 is provided, the first internal electrode 11 is formed so as to appear in the first corner portion 16a, and the second internal portion is formed in the second corner portion 16b.
The third corner 16c is formed so that the internal electrode 12 appears.
Is formed so that the third internal electrode 13 that faces the first and second internal electrodes 11 and 12 through the ceramic dielectric is exposed, and the third internal electrode 13 and the ceramic dielectric are provided at the fourth corner 16d. The bare chip 16 formed so that the opposing fourth internal electrode 14 appears, and the first and second internal electrodes 11, 12 and the ceramic dielectric over the first corner portion 16a and the second corner portion 16b of the surface of the bare chip 16. The first resistance layer 21 formed so as to face each other through the second corner portion 16b and the fourth corner portion 16d on the back surface of the bare chip 16 and so as to face the fourth internal electrode 14 through the ceramic dielectric. The second resistance layer 22 formed on the first chip, the first outer electrode 31 baked on the first corner 16a of the bare chip 16 so as to be electrically connected to the first internal electrode 11 and the first resistance layer 21, respectively. Second outer electrode 32 burned so as to be electrically connected to the first resistance layer 21, the second internal electrode 12, and the second resistance layer 22, respectively, and the third corner portion of the bare chip 16 in the second corner portion 16b of the chip 16. 16c, a ground electrode 17 burned so as to conduct to the third internal electrode 13, and 4th corner 16d of the bare chip 16 burned so as to conduct to the fourth internal electrode 14 and the second resistance layer 22, respectively. And 3 external electrodes 33.

【0005】図8〜図11に示すように、本発明の第2
のチップ型フィルタ50は、矩形のセラミック誘電体に
より構成され、チップ内部に第1内部電極11と第2内
部電極12と第3内部電極13と第4内部電極14が設
けられ、第1隅部16aに第1内部電極11が現れるよ
うに形成され、第2隅部16bに第2内部電極12が現
れるように形成され、第3隅部16cに第1及び第2内
部電極11,12とセラミック誘電体を介して対向する
第3内部電極13が現れるように形成され、第4隅部1
6dに第3内部電極13とセラミック誘電体を介して対
向する第4内部電極14が現れるように形成されたベア
チップ16と、ベアチップ16の表面の第1隅部16a
と第2隅部16bにかけてかつ第1及び第2内部電極1
1,12とセラミック誘電体を介して対向するように形
成された第1インダクタ層51と、ベアチップ16の裏
面の第2隅部16bと第4隅部16dにかけてかつ第4
内部電極14とセラミック誘電体を介して対向するよう
に形成された第2インダクタ層52と、ベアチップ16
の第1隅部16aに第1内部電極11及び第1インダク
タ層51にそれぞれ導通するように焼付けられた第1外
部電極31と、ベアチップ16の第2隅部16bに第1
インダクタ層51と第2内部電極12と第2インダクタ
層52にそれぞれ導通するように焼付けられた第2外部
電極32と、ベアチップ16の第3隅部16cに第3内
部電極13に導通するように焼付けられた接地電極17
と、ベアチップ16の第4隅部16dに第4内部電極1
4及び第2インダクタ層52にそれぞれ導通するように
焼付けられた第3外部電極33とを備えたものである。
As shown in FIGS. 8 to 11, the second aspect of the present invention is described.
The chip-type filter 50 of No. 1 is composed of a rectangular ceramic dielectric, is provided with the first internal electrode 11, the second internal electrode 12, the third internal electrode 13, and the fourth internal electrode 14 inside the chip, and has the first corner portion. 16a is formed so that the first internal electrode 11 appears, the second corner electrode 16b is formed so that the second internal electrode 12 appears, and the third corner part 16c is formed with the first and second internal electrodes 11 and 12 and the ceramic. It is formed so that the third internal electrodes 13 facing each other via the dielectric material appear, and the fourth corner portion 1 is formed.
Bare chip 16 formed so that fourth internal electrode 14 that faces third internal electrode 13 via a ceramic dielectric appears in 6d, and first corner portion 16a of the surface of bare chip 16
To the second corner 16b and the first and second internal electrodes 1
The first inductor layer 51 formed so as to face the first and the second dielectric layers 12 through the ceramic dielectric, the second corner portion 16b and the fourth corner portion 16d on the back surface of the bare chip 16, and the fourth
The second inductor layer 52 formed so as to face the internal electrode 14 with the ceramic dielectric interposed therebetween, and the bare chip 16
Of the first internal electrode 11 and the first inductor layer 51 on the first corner 16a of the first external electrode 31 and the second corner 16b of the bare chip 16 on the first external electrode 31.
The second external electrode 32 baked so as to be electrically connected to the inductor layer 51, the second internal electrode 12, and the second inductor layer 52, and the third internal electrode 13 is electrically connected to the third corner portion 16c of the bare chip 16. Baked ground electrode 17
And the fourth internal electrode 1 on the fourth corner 16d of the bare chip 16.
4 and the second inductor layer 52, and the third external electrode 33 baked so as to be electrically connected to each other.

【0006】本発明の第1のチップ型フィルタ10は、
湿式積層法又は乾式積層法により作られる。先ず最初に
BaTiO3系又はPb系の誘電体セラミック粉末、有
機バインダ、可塑剤及び有機溶剤を混合して誘電体ペー
スト又は誘電体スラリーを調製する。湿式積層法では、
この誘電体ペーストをカーテンコート法により台板上に
セラミック誘電体層を積層し乾燥した後、この誘電体層
の上に間隔をあけて導電性ペーストをスクリーン印刷し
乾燥することにより同一平面上に多数の第4内部電極1
4を形成する。この内部電極14の上に誘電体ペースト
を同様に積層した後、導電性ペーストをスクリーン印刷
し乾燥することにより多数の第3内部電極13を形成す
る。次いでこの内部電極13の上に誘電体ペーストを同
様に積層した後、導電ペーストをスクリーン印刷し乾燥
することにより多数の第1及び第2内部電極11,12
を同一平面上に所定の間隔をあけて形成する。更にこれ
らの内部電極11,12の上に誘電体ペーストを同様に
積層する。この積層体を脱バインダ処理した後、焼成
し、この焼結体の表面及び裏面に第1及び第2抵抗層2
1,22となるペーストをそれぞれスクリーン印刷し乾
燥して焼成する。
The first chip type filter 10 of the present invention is
It is made by a wet laminating method or a dry laminating method. First, a BaTiO 3 -based or Pb-based dielectric ceramic powder, an organic binder, a plasticizer, and an organic solvent are mixed to prepare a dielectric paste or a dielectric slurry. In the wet lamination method,
After this dielectric paste is laminated by a curtain coating method on a ceramic dielectric layer on a base plate and dried, a conductive paste is screen-printed on this dielectric layer at intervals to be dried on the same plane. Many fourth internal electrodes 1
4 is formed. A dielectric paste is similarly laminated on the internal electrodes 14, and then a conductive paste is screen-printed and dried to form a large number of third internal electrodes 13. Next, a dielectric paste is similarly laminated on the internal electrodes 13, and then a conductive paste is screen-printed and dried to obtain a large number of first and second internal electrodes 11, 12.
Are formed on the same plane at predetermined intervals. Further, a dielectric paste is similarly laminated on these internal electrodes 11 and 12. The laminated body is subjected to binder removal processing and then fired, and the first and second resistance layers 2 are formed on the front and back surfaces of the sintered body.
The pastes 1 and 22 are respectively screen-printed, dried and fired.

【0007】第1抵抗層21と、第1及び第2内部電極
11,12と、第3内部電極13と、第4内部電極14
と、第2抵抗層22は図3〜図6に示すように上方から
見たときにほぼ重なり合って形成される。また第1及び
第2抵抗層21,22は所望の抵抗値が得られれば、第
3内部電極13より一回り小さい又は大きい略矩形に形
成しても、第3内部電極13と略同形同大に形成しても
或いはその他の形状に形成してもよい。この焼結体を第
1抵抗層21及び第1内部電極11が第1隅部16aに
それぞれ現れ、第1抵抗層11と第2内部電極12と第
2抵抗層22が第1隅部16aに隣接する第2隅部16
bにそれぞれ現れ、第3内部電極13が第1隅部16a
に対向する第3隅部16cに現れ、更に第4内部電極1
4及び第2抵抗層22が第1隅部16aに隣接する第4
隅部16dに現れるように矩形のチップ状に切断する。
得られたベアチップ16の第1隅部16aに第1抵抗層
21及び第1内部電極11に導通するように導電性ペー
ストを塗布し焼付けて第1外部電極31を形成し、第2
隅部16bに第1抵抗層21と第2内部電極12と第2
抵抗層22に導通するように導電性ペーストを塗布し焼
き付けて第2外部電極32を形成する。またベアチップ
16の第3隅部16cに第3内部電極13に導通するよ
うに導電性ペーストを塗布し焼付けて接地電極17を形
成し、第4隅部16dに第4内部電極14及び第2抵抗
層22に導通するように導電性ペーストを塗布し焼き付
けて第3外部電極33を形成する。
The first resistance layer 21, the first and second internal electrodes 11 and 12, the third internal electrode 13, and the fourth internal electrode 14
Then, the second resistance layer 22 is formed so as to substantially overlap with each other when viewed from above, as shown in FIGS. Also, if the first and second resistance layers 21 and 22 have a substantially rectangular shape that is slightly smaller or larger than the third internal electrode 13 as long as a desired resistance value is obtained, the first and second resistive layers 21 and 22 have substantially the same shape as the third internal electrode 13. It may be formed in a large size or in another shape. In this sintered body, the first resistance layer 21 and the first internal electrode 11 appear in the first corner 16a, and the first resistance layer 11, the second internal electrode 12, and the second resistance layer 22 appear in the first corner 16a. Adjacent second corner 16
b, and the third internal electrode 13 has the first corner 16a.
Appearing in the third corner 16c opposite to, and further the fourth internal electrode 1
4 and the second resistance layer 22 are adjacent to the first corner 16a
It is cut into a rectangular chip shape so as to appear in the corner 16d.
A conductive paste is applied to the first corner portion 16a of the obtained bare chip 16 so as to be electrically connected to the first resistance layer 21 and the first internal electrode 11 and baked to form the first external electrode 31, and the second external electrode 31 is formed.
The first resistance layer 21, the second internal electrode 12 and the second
A conductive paste is applied so as to be electrically connected to the resistance layer 22 and baked to form the second external electrode 32. Further, a conductive paste is applied to the third corner portion 16c of the bare chip 16 so as to be electrically connected to the third internal electrode 13 and baked to form the ground electrode 17, and the fourth internal electrode 14 and the second resistor 16 are formed at the fourth corner portion 16d. A conductive paste is applied so as to be electrically connected to the layer 22 and baked to form the third external electrode 33.

【0008】上記チップ型フィルタ10を乾式積層法で
製造するには、上記誘電体スラリーをドクタブレード法
等により成膜乾燥してセラミックグリーンシートを作
り、このグリーンシートからなる誘電体層の上に湿式積
層法と同様に第4内部電極14を形成する。この内部電
極14の上に上記グリーンシートを積層した後、このグ
リーンシートの上に湿式積層法と同様に第3内部電極1
3を形成する。次いでこの内部電極13の上に上記グリ
ーンシートを積層した後、このグリーンシートの上に湿
式積層法と同様に第1及び第2内部電極11,12を形
成する。更にこれらの内部電極11,12の上に上記グ
リーンシートを積層する。以下、湿式積層法と同様に積
層体の焼成、第1及び第2抵抗層21,22の形成、焼
結体のチップ化を行い、最後に第1〜第3外部電極31
〜33と接地電極17とを形成する。
In order to manufacture the chip type filter 10 by a dry lamination method, a film of the above dielectric slurry is dried by a doctor blade method or the like to form a ceramic green sheet, and a ceramic green sheet is formed on the green sheet. The fourth internal electrode 14 is formed as in the wet lamination method. After the green sheet is laminated on the internal electrode 14, the third internal electrode 1 is formed on the green sheet by the wet lamination method.
3 is formed. Next, after stacking the green sheet on the internal electrode 13, the first and second internal electrodes 11 and 12 are formed on the green sheet in the same manner as the wet stacking method. Further, the green sheet is laminated on these internal electrodes 11 and 12. Thereafter, the laminated body is fired, the first and second resistance layers 21 and 22 are formed, the sintered body is made into chips, as in the wet lamination method, and finally the first to third external electrodes 31 are formed.
~ 33 and the ground electrode 17 are formed.

【0009】本発明の第2のチップ型フィルタ50は第
1のフィルタ10の第1及び第2抵抗層21,22を第
1及び第2インダクタ層51,52にそれぞれ置き換え
たことを除いて第1のフィルタ10と同様に作製され
る。第1又は第2のチップ型フィルタ10又は50と
も、第1及び第2抵抗層21,22の表面又は第1及び
第2インダクタ層51,52の表面に絶縁膜18を形成
することが好ましい。この絶縁膜18としてはSiO2
を主成分とする膜が好ましい。この絶縁膜18の形成方
法としては、ガラスペーストを塗布し焼成する厚膜形成
法、或いは真空蒸着法、スパッタリング法、イオンプレ
ーティング法のような物理蒸着法(PVD法)又は化学
蒸着法(CVD法)の薄膜形成法により行われる。また
上記絶縁膜18はチップ状に切断したベアチップ16に
外部電極31〜33や接地電極17を形成した後又は前
に形成してもよく、或いはチップ状に切断する前にセラ
ミック焼結体の抵抗層21,22及びインダクタ層5
1,52の表面に形成してもよい。
The second chip type filter 50 of the present invention is the first chip type filter 50 except that the first and second resistance layers 21 and 22 of the first filter 10 are replaced with first and second inductor layers 51 and 52, respectively. It is manufactured in the same manner as the filter 10 of No. 1. In both the first and second chip type filters 10 and 50, it is preferable to form the insulating film 18 on the surfaces of the first and second resistance layers 21 and 22 or the surfaces of the first and second inductor layers 51 and 52. The insulating film 18 is made of SiO 2
A film containing as a main component is preferable. As a method of forming the insulating film 18, a thick film forming method in which a glass paste is applied and baked, a physical vapor deposition method (PVD method) such as a vacuum vapor deposition method, a sputtering method, an ion plating method, or a chemical vapor deposition method (CVD) is used. Method). The insulating film 18 may be formed after or before the external electrodes 31 to 33 and the ground electrode 17 are formed on the bare chip 16 cut into chips, or the resistance of the ceramic sintered body is cut before cutting into chips. Layers 21 and 22 and inductor layer 5
You may form on the surface of 1,52.

【0010】[0010]

【作用】第1のチップ型RCフィルタ10は第1外部電
極31と第1抵抗層21と第2外部電極32からなる抵
抗回路と、第2外部電極32と第2抵抗層22と第3外
部電極33からなる抵抗回路と、第3内部電極13と第
1及び第2内部電極11,12とこれらの間に介在する
ベアチップ16の誘電体からなる分布キャパシタンス回
路と、第3内部電極13と第4内部電極14とこれらの
間に介在するベアチップ16の誘電体からなる分布キャ
パシタンス回路とを構成し、図7の等価回路で示され
る。
The first chip type RC filter 10 has a resistance circuit including the first external electrode 31, the first resistance layer 21, and the second external electrode 32, the second external electrode 32, the second resistance layer 22, and the third external electrode. A resistance circuit composed of the electrode 33, a distributed capacitance circuit composed of the third internal electrode 13, the first and second internal electrodes 11, 12 and the dielectric of the bare chip 16 interposed therebetween, the third internal electrode 13 and the 4 internal electrodes 14 and a distributed capacitance circuit made of a dielectric material of the bare chip 16 interposed therebetween, which is shown by an equivalent circuit in FIG.

【0011】第2のチップ型LCフィルタ50は第1外
部電極31と第1インダクタ層51と第2外部電極32
からなるインダクタ回路と、第2外部電極32と第2イ
ンダクタ層52と第3外部電極33からなるインダクタ
回路と、第3内部電極13と第1及び第2内部電極1
1,12とこれらの間に介在するベアチップ16の誘電
体からなる分布キャパシタンス回路と、第3内部電極1
3と第4内部電極14とこれらの間に介在するベアチッ
プ16の誘電体からなる分布キャパシタンス回路とを構
成し、図12の等価回路で示される。
The second chip type LC filter 50 includes a first outer electrode 31, a first inductor layer 51 and a second outer electrode 32.
An inductor circuit including a second external electrode 32, a second inductor layer 52 and a third external electrode 33, a third internal electrode 13, a first and second internal electrode 1
1, 12 and a distributed capacitance circuit composed of a dielectric material of a bare chip 16 interposed therebetween, and a third internal electrode 1
The third and fourth internal electrodes 14 and the distributed capacitance circuit made of the dielectric material of the bare chip 16 interposed therebetween are shown in an equivalent circuit of FIG.

【0012】抵抗層21,22の表面やインダクタ層5
1,52の表面に絶縁膜18をそれぞれ形成すると、第
一に外部電極31〜33や接地電極17のはんだ耐熱性
向上のためにNiめっきを、又ははんだ付け性向上のた
めにSnめっきをそれぞれ外部電極31〜33や接地電
極17に施す場合にめっきが抵抗層21,22又はイン
ダクタ層51,52に直接付着せず、抵抗値やインダク
タンスが変わらない。また第二にチップ型フィルタ10
又は50の使用環境が高温多湿であってもフィルタ特性
が変わらない。
The surfaces of the resistance layers 21 and 22 and the inductor layer 5
When the insulating films 18 are respectively formed on the surfaces of 1, 52, first, Ni plating is performed to improve the solder heat resistance of the external electrodes 31 to 33 and the ground electrode 17, or Sn plating is performed to improve the solderability. When applied to the external electrodes 31 to 33 and the ground electrode 17, the plating does not directly adhere to the resistance layers 21 and 22 or the inductor layers 51 and 52, and the resistance value and the inductance do not change. Secondly, the chip type filter 10
Alternatively, the filter characteristics do not change even when the usage environment of 50 is high temperature and high humidity.

【0013】[0013]

【実施例】次に本発明の実施例を図面に基づいて詳しく
説明する。 <実施例1>図1〜図6に示すように、本発明の第1の
チップ型フィルタ10はRCフィルタであり、セラミッ
ク誘電体からなるベアチップ16と、第1〜第4内部電
極11〜14と、第1及び第2抵抗層21,22と、第
1〜第3外部電極31〜33と、接地電極17を備え
る。このチップ型フィルタ10は次の方法により作られ
る。先ずPb系リラクサ材料で作られたセラミック誘電
体グリーンシートを積層してセラミック誘電体層を形成
した後、所定のパターンでAg系の厚膜ペーストをスク
リーン印刷し乾燥して同一平面内に等間隔に多数の第4
内部電極14を形成し(図1、図2及び図6)、この上
にこれらの内部電極14を全て被覆するようにして上述
したセラミック誘電体層と同形同大のセラミック誘電体
層を積層した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. <Embodiment 1> As shown in FIGS. 1 to 6, a first chip type filter 10 of the present invention is an RC filter, and a bare chip 16 made of a ceramic dielectric and first to fourth internal electrodes 11 to 14 are used. , First and second resistance layers 21 and 22, first to third external electrodes 31 to 33, and a ground electrode 17. The chip type filter 10 is manufactured by the following method. First, a ceramic dielectric green sheet made of a Pb-based relaxor material is laminated to form a ceramic dielectric layer, and then an Ag-based thick film paste is screen-printed in a predetermined pattern and dried to form equal intervals in the same plane. A large number of 4th
An internal electrode 14 is formed (FIGS. 1, 2 and 6), and a ceramic dielectric layer having the same shape and size as the above-mentioned ceramic dielectric layer is laminated thereon so as to cover all the internal electrodes 14. did.

【0014】このセラミック誘電体層上の第4内部電極
14に相応する位置に第4内部電極14の個々のパター
ンより幅が約2倍で長さが同一の略矩形のパターンでA
g系の厚膜ペーストをスクリーン印刷し乾燥して多数の
第3内部電極13を形成し(図1、図2及び図5)、こ
の上にこれらの内部電極13を全て被覆するようにして
上述したセラミック誘電体層と同形同大のセラミック誘
電体層を積層した。このセラミック誘電体層上の第3内
部電極13に相応する位置に第3内部電極13の個々の
パターンと幅が同一で長さが約半分のパターンでAg系
の厚膜ペーストをスクリーン印刷し乾燥することによ
り、互いに所定の間隔をあけた多数組の第1及び第2内
部電極11,12を形成した(図1、図2及び図4)。
この上にこれらの内部電極11,12を全て被覆するよ
うにして上述したセラミック誘電体層と同形同大のセラ
ミック誘電体層を積層した。
At a position on the ceramic dielectric layer corresponding to the fourth internal electrode 14, a substantially rectangular pattern having a width about twice that of the individual patterns of the fourth internal electrode 14 and the same length as A is formed.
The g-based thick film paste is screen-printed and dried to form a large number of third internal electrodes 13 (FIGS. 1, 2 and 5), and the above-mentioned internal electrodes 13 are all covered thereon. A ceramic dielectric layer having the same shape and size as the ceramic dielectric layer was laminated. At a position corresponding to the third internal electrode 13 on the ceramic dielectric layer, an Ag-based thick film paste is screen-printed with a pattern having the same width as the individual patterns of the third internal electrode 13 and a length of about half, and dried. By doing so, a large number of sets of first and second internal electrodes 11 and 12 spaced from each other by a predetermined distance were formed (FIGS. 1, 2, and 4).
On top of this, a ceramic dielectric layer having the same shape and size as the above-mentioned ceramic dielectric layer was laminated so as to cover all the internal electrodes 11 and 12.

【0015】次いでこの積層体を焼成して誘電体の層厚
がそれぞれ5〜数100μmで第1〜第4内部電極11
〜14が内蔵された板状のセラミック焼結体を形成した
後、この焼結体の表面に所定のパターンでRuO2系厚
膜ペーストを第1及び第2内部電極11,12に相応す
る位置にスクリーン印刷し焼成することにより厚さ5〜
数100μmの第1抵抗層21を形成し(図1〜図
3)、焼結体の裏面に所定のパターンでRuO2系厚膜
ペーストを第4内部電極14に相応する位置にスクリー
ン印刷し焼成することにより第1抵抗層21と略同形同
大の厚さ5〜数100μmの第2抵抗層22を形成した
(図1、図2及び図6)。これらの抵抗層21,22は
第3内部電極13より一回り小さい略矩形に形成され
る。
Next, the laminated body is fired so that the dielectric layers each have a thickness of 5 to several hundred μm and the first to fourth internal electrodes 11 are formed.
After forming a plate-shaped ceramic sintered body containing 14 to 14, RuO 2 -based thick film paste is formed on the surface of the sintered body at a position corresponding to the first and second internal electrodes 11 and 12. By screen printing and baking on
A first resistance layer 21 having a thickness of several 100 μm is formed (FIGS. 1 to 3), and a RuO 2 thick film paste is screen-printed on a back surface of the sintered body in a predetermined pattern at a position corresponding to the fourth internal electrode 14 and baked. By doing so, the second resistance layer 22 having a thickness of 5 to several hundreds μm and having substantially the same shape and size as the first resistance layer 21 was formed (FIGS. 1, 2 and 6). These resistance layers 21 and 22 are formed in a substantially rectangular shape slightly smaller than the third internal electrode 13.

【0016】また第1内部電極11の第1コーナ部11
aには同一平面内で外方に突出する第1内部突起11b
が形成され、第2内部電極12の第2コーナ部12aに
は同一平面内で外方に突出する第2内部突起12bが形
成される(図4)。第3内部電極13の第3コーナ部1
3aには同一平面内で外方に突出する第3内部突起13
bが形成され(図5)、第4内部電極14の第4コーナ
部14aには同一平面内で外方に突出する第4内部突起
14bが形成される(図6)。第1抵抗層21の第1及
び第2コーナ部21a,21bには同一平面内で外方に
突出する第1及び第2表面突起21c,21dがそれぞ
れ形成され(図3)、第2抵抗層22の第2及び第4コ
ーナ部22a,22bには同一平面内で外方に突出する
第1及び第2裏面突起22c,22dがそれぞれ形成さ
れる(図6)。
The first corner portion 11 of the first internal electrode 11
a is a first internal protrusion 11b protruding outward in the same plane.
Is formed, and the second corner portion 12a of the second inner electrode 12 is formed with the second inner protrusion 12b protruding outward in the same plane (FIG. 4). Third corner portion 1 of third internal electrode 13
3a is a third internal protrusion 13 protruding outward in the same plane.
b is formed (FIG. 5), and a fourth internal protrusion 14b is formed on the fourth corner portion 14a of the fourth internal electrode 14 so as to project outward in the same plane (FIG. 6). The first and second corner portions 21a and 21b of the first resistance layer 21 are respectively formed with first and second surface protrusions 21c and 21d protruding outward in the same plane (FIG. 3), and the second resistance layer. First and second rear surface protrusions 22c and 22d, which protrude outward in the same plane, are formed on the second and fourth corner portions 22a and 22b of 22 (FIG. 6).

【0017】次にこの焼結体を第1抵抗層21毎にダイ
ヤモンドソーで矩形のチップ状に切断した。得られたベ
アチップ16をバレル研磨することにより、その第1隅
部16aに第1内部電極11の第1内部突起11b及び
第1抵抗層21の第1表面突起21cをそれぞれ露出さ
せ、第1隅部16aに隣接する第2隅部16bに第2内
部電極12の第2内部突起12bと第1抵抗層21の第
2表面突起21dと第2抵抗層22の第1裏面突起22
cとをそれぞれ露出させ、第1隅部16aに対向する第
3隅部16cに第3内部電極13の第3内部突起13b
を露出させ、更に第1隅部16aに隣接する第4隅部1
6dに第4内部電極14の第4内部突起14b及び第2
抵抗層22の第2裏面突起22dをそれぞれ露出させ
た。
Next, the sintered body was cut into rectangular chips with a diamond saw for each of the first resistance layers 21. The bare chip 16 thus obtained is barrel-polished to expose the first internal protrusions 11b of the first internal electrodes 11 and the first surface protrusions 21c of the first resistance layer 21 at the first corners 16a thereof, and the first corners are exposed. The second inner protrusion 12b of the second inner electrode 12, the second front protrusion 21d of the first resistance layer 21, and the first back protrusion 22 of the second resistance layer 22 are formed at the second corner 16b adjacent to the portion 16a.
c and the third inner protrusion 13b of the third inner electrode 13 are exposed at the third corner 16c facing the first corner 16a.
And the fourth corner 1 adjacent to the first corner 16a.
6d includes a fourth inner protrusion 14b of the fourth inner electrode 14 and a second inner protrusion 14b.
The second back surface protrusions 22d of the resistance layer 22 were exposed.

【0018】ベアチップ16の第1隅部16aにAg−
Pdの導電性ペーストを塗布し焼付けて第1内部突起1
1b及び第1表面突起21cに導通するように第1外部
電極31を形成し、第2隅部16bにAg−Pdの導電
性ペーストを塗布し焼付けて第2内部突起12bと第2
表面突起21dと第1裏面突起22cとに導通するよう
に第2外部電極32を形成し、第3隅部16cにAg−
Pdの導電性ペーストを塗布し焼付けて第3内部突起1
3bに導通するように接地電極17を形成し、第4隅部
16dにAg−Pdの導電性ペーストを塗布し焼付けて
第4内部突起14b及び第2裏面突起22dに導通する
ように第3外部電極33を形成した。更にベアチップ1
6の第1及び第2抵抗層21,22の表面にガラスペー
ストを塗布して焼成してSiO2を主成分とする厚さ5
〜数10μmの絶縁膜18,18(図1及び図2)をそ
れぞれ形成することにより、チップ型RCフィルタ10
を作製した。
At the first corner 16a of the bare chip 16, Ag-
Applying a conductive paste of Pd and baking it to form the first internal protrusion 1
1b and the first surface protrusion 21c are electrically connected to each other, the first outer electrode 31 is formed, and the second corner portion 16b is coated with a conductive paste of Ag-Pd and baked to form the second inner protrusion 12b and the second inner protrusion 12b.
The second external electrode 32 is formed so as to be electrically connected to the front surface projection 21d and the first back surface projection 22c, and Ag− is formed at the third corner 16c.
Applying a conductive paste of Pd and baking it to form the third internal protrusion 1
The ground electrode 17 is formed so as to be electrically connected to 3b, and the fourth corner portion 16d is coated with a conductive paste of Ag-Pd and baked to be electrically connected to the fourth inner protrusion 14b and the second back protrusion 22d. The electrode 33 was formed. Bare chip 1
Glass paste is applied to the surfaces of the first and second resistance layers 21 and 22 of No. 6 and baked to have a thickness of 5 containing SiO 2 as a main component.
By forming the insulating films 18, 18 (FIGS. 1 and 2) each having a thickness of several tens of μm, the chip-type RC filter 10 is formed.
Was produced.

【0019】<実施例2>第2のチップ型フィルタ50
はLCフィルタであり、実施例1と同様にしてセラミッ
ク焼結体を形成し、図8〜図11に示すようにこのセラ
ミック焼結体の表面及び裏面に実施例1のRuO2系厚
膜ペーストの代わりにフェライト又は強磁性体の厚膜ペ
ーストを実施例1と同様にスクリーン印刷し焼成した。
これにより厚さ5〜数100μmの第1及び第2インダ
クタ層51,52が形成された。その後実施例1と同様
にしてチップ型LCフィルタ50を作製した。51c及
び51dは第1インダクタ層51の第1及び第2コーナ
部51a,51bにそれぞれ形成された第1及び第2表
面突起であり、52c及び52dは第2インダクタ層5
2の第2及び第4コーナ部52a,52bにそれぞれ形
成された第1及び第2裏面突起である。図8〜図11に
おいて上記実施例1と同一符号は同一部品を示す。
<Second Embodiment> Second chip type filter 50
Is an LC filter, and a ceramic sintered body is formed in the same manner as in Example 1. As shown in FIGS. 8 to 11, the RuO 2 thick film paste of Example 1 is applied to the front and back surfaces of this ceramic sintered body. Instead of, a thick film paste of ferrite or ferromagnetic material was screen-printed and fired in the same manner as in Example 1.
As a result, the first and second inductor layers 51 and 52 having a thickness of 5 to several 100 μm were formed. After that, a chip type LC filter 50 was produced in the same manner as in Example 1. Reference numerals 51c and 51d denote first and second surface protrusions respectively formed on the first and second corner portions 51a and 51b of the first inductor layer 51, and 52c and 52d denote the second inductor layer 5
The second and fourth corner portions 52a and 52b are the first and second backside protrusions, respectively. 8 to 11, the same reference numerals as those of the above-described first embodiment indicate the same parts.

【0020】[0020]

【発明の効果】以上述べたように、本発明のチップ型フ
ィルタは、チップ内部に形成した第3内部電極と第1、
第2及び第4内部電極とによりそれぞれコンデンサを構
成し、チップの表面及び裏面に第1及び第2抵抗層又は
第1及び第2インダクタ層を形成したので、1チップの
極めて小型の形態でRC又はLCの機能を具備でき、高
密度にプリント回路基板に実装することができる。また
第1及び第2抵抗層表面又は第1及び第2インダクタ層
表面に絶縁膜を形成すれば、外部電極や接地電極のめっ
き処理時にめっきが第1及び第2抵抗層又は第1及び第
2インダクタ層に直接付着せず、またチップ型フィルタ
の使用環境が高温多湿であっても、それぞれフィルタ特
性が変わらない。
As described above, the chip type filter of the present invention has the third internal electrode and the first internal electrode formed inside the chip.
Since capacitors are respectively constituted by the second and fourth internal electrodes and the first and second resistance layers or the first and second inductor layers are formed on the front surface and the back surface of the chip, the RC can be realized in a very small form of one chip. Alternatively, it can have an LC function and can be mounted on a printed circuit board with high density. Further, if an insulating film is formed on the surface of the first and second resistance layers or the surface of the first and second inductor layers, the plating is performed on the first and second resistance layers or the first and second resistance layers during the plating process of the external electrode and the ground electrode. Even if the chip type filter is not directly attached to the inductor layer and the use environment of the chip type filter is high temperature and high humidity, the filter characteristics do not change.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例1のチップ型フィルタの抵抗層表
面に絶縁膜が形成された状態を示す図3のA−A線断面
図。
FIG. 1 is a cross-sectional view taken along the line AA of FIG. 3 showing a state in which an insulating film is formed on the surface of a resistance layer of a chip type filter according to a first embodiment of the present invention.

【図2】そのチップ型フィルタの抵抗層表面に絶縁膜が
形成された状態を示す図3のB−B線断面図。
FIG. 2 is a sectional view taken along line BB of FIG. 3 showing a state in which an insulating film is formed on the surface of the resistance layer of the chip type filter.

【図3】抵抗層表面に絶縁膜を形成する前の状態を示す
チップ型フィルタの平面図。
FIG. 3 is a plan view of a chip filter showing a state before an insulating film is formed on the surface of a resistance layer.

【図4】図1のC−C線断面図。4 is a cross-sectional view taken along the line CC of FIG.

【図5】図1のD−D線断面図。5 is a cross-sectional view taken along line DD of FIG.

【図6】図1のE−E線断面図。6 is a sectional view taken along line EE of FIG.

【図7】その等価回路図。FIG. 7 is an equivalent circuit diagram thereof.

【図8】本発明の実施例2のチップ型フィルタのインダ
クタ層表面に絶縁膜が形成された状態を示す図10のF
−F線断面図。
FIG. 8F of FIG. 10 showing a state in which an insulating film is formed on the inductor layer surface of the chip type filter according to the second embodiment of the present invention.
-F line sectional view.

【図9】そのチップ型フィルタのインダクタ層表面に絶
縁膜が形成された状態を示す図10のG−G線断面図。
9 is a cross-sectional view taken along line GG of FIG. 10 showing a state in which an insulating film is formed on the inductor layer surface of the chip type filter.

【図10】インダクタ層表面に絶縁膜を形成する前の状
態を示すチップ型フィルタの平面図。
FIG. 10 is a plan view of the chip filter showing a state before an insulating film is formed on the surface of the inductor layer.

【図11】図8のH−H線断面図。11 is a sectional view taken along line HH of FIG.

【図12】その等価回路図。FIG. 12 is an equivalent circuit diagram thereof.

【符号の説明】[Explanation of symbols]

10,50 チップ型フィルタ 11〜14 内部電極 16 ベアチップ 16a〜16d 隅部 17 接地電極 18 絶縁膜 21,22 抵抗層 31〜33 外部電極 51,52 インダクタ層 10,50 Chip type filter 11-14 Internal electrode 16 Bare chip 16a-16d Corner 17 Grounding electrode 18 Insulating film 21,22 Resistance layer 31-33 External electrode 51,52 Inductor layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 矩形のセラミック誘電体により構成さ
れ、チップ内部に第1内部電極(11)と第2内部電極(12)
と第3内部電極(13)と第4内部電極(14)が設けられ、第
1隅部(16a)に前記第1内部電極(11)が現れるように形
成され、第2隅部(16b)に前記第2内部電極(12)が現れ
るように形成され、第3隅部(16c)に前記第1及び第2
内部電極(11,12)と前記セラミック誘電体を介して対向
する第3内部電極(13)が現れるように形成され、第4隅
部(16d)に前記第3内部電極(13)と前記セラミック誘電
体を介して対向する第4内部電極(14)が現れるように形
成されたベアチップ(16)と、 前記ベアチップ(16)の表面の前記第1隅部(16a)と第2
隅部(16b)にかけてかつ前記第1及び第2内部電極(11,1
2)と前記セラミック誘電体を介して対向するように形成
された第1抵抗層(21)と、 前記ベアチップ(16)の裏面の前記第2隅部(16b)と第4
隅部(16d)にかけてかつ前記第4内部電極(14)と前記セ
ラミック誘電体を介して対向するように形成された第2
抵抗層(22)と、 前記ベアチップ(16)の第1隅部(16a)に前記第1内部電
極(11)及び前記第1抵抗層(21)にそれぞれ導通するよう
に焼付けられた第1外部電極(31)と、 前記ベアチップ(16)の第2隅部(16b)に前記第1抵抗層
(21)と前記第2内部電極(12)と前記第2抵抗層(22)にそ
れぞれ導通するように焼付けられた第2外部電極(32)
と、 前記ベアチップ(16)の第3隅部(16c)に前記第3内部電
極(13)に導通するように焼付けられた接地電極(17)と、 前記ベアチップ(16)の第4隅部(16d)に前記第4内部電
極(14)及び前記第2抵抗層(22)にそれぞれ導通するよう
に焼付けられた第3外部電極(33)とを備えたチップ型フ
ィルタ。
1. A first internal electrode (11) and a second internal electrode (12) formed of a rectangular ceramic dielectric material inside a chip.
And a third internal electrode (13) and a fourth internal electrode (14) are provided so that the first internal electrode (11) appears at the first corner (16a) and the second corner (16b). Is formed so that the second internal electrode (12) appears, and the first and second inner electrodes are formed at the third corner (16c).
The third internal electrode (13) facing the internal electrodes (11, 12) through the ceramic dielectric is formed to appear, and the third internal electrode (13) and the ceramic are formed at the fourth corner (16d). A bare chip (16) formed so that a fourth internal electrode (14) facing each other via a dielectric appears; a first corner portion (16a) of the bare chip (16);
Over the corner (16b) and the first and second internal electrodes (11, 1)
2) a first resistance layer (21) formed so as to face the ceramic dielectric body, a second corner (16b) on the back surface of the bare chip (16) and a fourth
A second portion formed so as to extend to the corner portion (16d) and face the fourth internal electrode (14) through the ceramic dielectric.
A resistance layer (22) and a first outer portion baked on the first corner (16a) of the bare chip (16) so as to be electrically connected to the first internal electrode (11) and the first resistance layer (21), respectively. The electrode (31) and the first resistance layer on the second corner (16b) of the bare chip (16)
(21), the second internal electrode (12), and the second external electrode (32) baked so as to be electrically connected to the second resistance layer (22), respectively.
A ground electrode (17) burned to the third corner (16c) of the bare chip (16) so as to be electrically connected to the third internal electrode (13), and a fourth corner () of the bare chip (16). 16d) A chip-type filter having the fourth internal electrode (14) and the third external electrode (33) baked so as to be electrically connected to the second resistance layer (22).
【請求項2】 第1及び第2抵抗層(21,22)の表面がそ
れぞれ絶縁膜(18)で被覆された請求項1記載のチップ型
フィルタ。
2. The chip type filter according to claim 1, wherein the surfaces of the first and second resistance layers (21, 22) are each covered with an insulating film (18).
【請求項3】 矩形のセラミック誘電体により構成さ
れ、チップ内部に第1内部電極(11)と第2内部電極(12)
と第3内部電極(13)と第4内部電極(14)が設けられ、第
1隅部(16a)に前記第1内部電極(11)が現れるように形
成され、第2隅部(16b)に前記第2内部電極(12)が現れ
るように形成され、第3隅部(16c)に前記第1及び第2
内部電極(11,12)と前記セラミック誘電体を介して対向
する第3内部電極(13)が現れるように形成され、第4隅
部(16d)に前記第3内部電極(13)と前記セラミック誘電
体を介して対向する第4内部電極(14)が現れるように形
成されたベアチップ(16)と、 前記ベアチップ(16)の表面の前記第1隅部(16a)と第2
隅部(16b)にかけてかつ前記第1及び第2内部電極(11,1
2)と前記セラミック誘電体を介して対向するように形成
された第1インダクタ層(51)と、 前記ベアチップ(16)の裏面の前記第2隅部(16b)と第4
隅部(16d)にかけてかつ前記第4内部電極(14)とセラミ
ック誘電体を介して対向するように形成された第2イン
ダクタ層(52)と、 前記ベアチップ(16)の第1隅部(16a)に前記第1内部電
極(11)及び前記第1インダクタ層(51)にそれぞれ導通す
るように焼付けられた第1外部電極(31)と、 前記ベアチップ(16)の第2隅部(16b)に前記第1インダ
クタ層(51)と前記第2内部電極(12)と前記第2インダク
タ層(52)にそれぞれ導通するように焼付けられた第2外
部電極(32)と、 前記ベアチップ(16)の第3隅部(16c)に前記第3内部電
極(13)に導通するように焼付けられた接地電極(17)と、 前記ベアチップ(16)の第4隅部(16d)に前記第4内部電
極(14)及び前記第2インダクタ層(52)にそれぞれ導通す
るように焼付けられた第3外部電極(33)とを備えたチッ
プ型フィルタ。
3. A first internal electrode (11) and a second internal electrode (12) formed of a rectangular ceramic dielectric material inside a chip.
And a third internal electrode (13) and a fourth internal electrode (14) are provided so that the first internal electrode (11) appears at the first corner (16a) and the second corner (16b). Is formed so that the second internal electrode (12) appears, and the first and second inner electrodes are formed at the third corner (16c).
The third internal electrode (13) facing the internal electrodes (11, 12) through the ceramic dielectric is formed to appear, and the third internal electrode (13) and the ceramic are formed at the fourth corner (16d). A bare chip (16) formed so that a fourth internal electrode (14) facing each other via a dielectric appears; a first corner portion (16a) of the bare chip (16);
Over the corner (16b) and the first and second internal electrodes (11, 1)
2) a first inductor layer (51) formed so as to face the ceramic dielectric, and a second corner portion (16b) of the back surface of the bare chip (16) and a fourth inductor layer (51).
A second inductor layer (52) formed over the corner (16d) and facing the fourth internal electrode (14) via a ceramic dielectric; and a first corner (16a) of the bare chip (16). ), A first external electrode (31) burned so as to be electrically connected to the first internal electrode (11) and the first inductor layer (51), and a second corner portion (16b) of the bare chip (16). A second external electrode (32) burned so as to be electrically connected to the first inductor layer (51), the second internal electrode (12), and the second inductor layer (52), and the bare chip (16) A ground electrode (17) burned so as to be electrically connected to the third internal electrode (13) at a third corner (16c) of the fourth internal portion (16c), and a fourth internal portion at a fourth corner (16d) of the bare chip (16). A chip type filter including an electrode (14) and a third external electrode (33) baked so as to be electrically connected to the second inductor layer (52).
【請求項4】 第1及び第2インダクタ層(51,52)の表
面がそれぞれ絶縁膜(18)で被覆された請求項3記載のチ
ップ型フィルタ。
4. The chip type filter according to claim 3, wherein the surfaces of the first and second inductor layers (51, 52) are each covered with an insulating film (18).
JP6592395A 1995-03-24 1995-03-24 Chip filter Withdrawn JPH08265084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6592395A JPH08265084A (en) 1995-03-24 1995-03-24 Chip filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6592395A JPH08265084A (en) 1995-03-24 1995-03-24 Chip filter

Publications (1)

Publication Number Publication Date
JPH08265084A true JPH08265084A (en) 1996-10-11

Family

ID=13300987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6592395A Withdrawn JPH08265084A (en) 1995-03-24 1995-03-24 Chip filter

Country Status (1)

Country Link
JP (1) JPH08265084A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150205A (en) * 1997-11-19 1999-06-02 Mitsubishi Materials Corp Chip-type cr element
JP2003008153A (en) * 2001-06-19 2003-01-10 Taiyo Yuden Co Ltd Electronic circuit device and low-pass filter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150205A (en) * 1997-11-19 1999-06-02 Mitsubishi Materials Corp Chip-type cr element
JP2003008153A (en) * 2001-06-19 2003-01-10 Taiyo Yuden Co Ltd Electronic circuit device and low-pass filter

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