JPH08256353A - Line double-speed conversion circuit - Google Patents

Abstract

PURPOSE: To provide a line double-speed conversion circuit in which a fault caused when multiplexed data are subject to double speed conversion and the data are demultiplexed is prevented. CONSTITUTION: A line memory 1 writes data resulting from multiplexing R-Y, B-Y signals and the data are read at a double speed for each horizontal period. D-FFs 4, 5 are used to demultiplex the data after double-speed conversion based on clock signals inverted to each other. A clock phase detection circuit 6 detects the phases of the R-Y, B-Y to generate a phase detection signal. A clock selection circuit 7 gives selectively the clock signals inverted to each other to the D-FFs 4, 5 based on the phase detection signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line double speed conversion circuit by digital signal processing.

[0002]

2. Description of the Related Art Generally, a color difference signal has a narrow frequency band (about 1 MHz). Therefore, in a television receiver using digital signal processing, RY and BY are time-division multiplexed (multi-multi). It is well known that the memory capacity used for signal processing is reduced by plexing. For example, in the case of multiplexing a color difference signal having a 4fsc clock rate, the 8fsc system clock synchronized with the horizontal synchronizing signal is divided by 2 to be 2
The fsc clock is used, and the RY data and the BY data are multiplexed by the 2fsc clock. Note that fsc is the color subcarrier frequency.

By the way, in a television receiver adapted to convert a single density signal into a double density signal for display, a color difference signal multiplexed as described above is separated into an original color difference signal (demultiplexing). In this case, the color difference signal data is subjected to double speed conversion processing. A line double speed conversion circuit performs double speed conversion processing on such data. In the line double speed conversion process, the data is written in the line memory and read at a double speed for each horizontal period, and the time axis is compressed and output to realize the double speed conversion process.

FIG. 5 is a block diagram showing an example of a conventional line double speed conversion circuit. The configuration and operation of this conventional line double speed conversion circuit will be described with reference to the waveform chart shown in FIG. In FIG. 5, the line memory 1 has a structure shown in FIG.
The multiplexed color difference signal data shown in (C) or is input. The horizontal synchronizing signal and the 8fsc system clock shown in FIG. 6D are input to the 1/2 frequency dividing circuit 2, and the 1/2 frequency dividing circuit 2 is synchronized with the horizontal synchronizing signal to 4fsc shown in FIG. 6A. Output clock. The 4fsc clock is input to the line memory 1 as a write clock, and the 8fsc system clock is input to the line memory 1 as a read clock. The line memory 1 writes the color difference signal data at the 4fsc clock and reads it at the 8fsc system clock to obtain the 8fsc shown in or of FIG.
The color difference signal data having the clock rate is output.

The color difference signal data output from the line memory 1 is input to D flip-flops (hereinafter, D-FF) 4 and 5 for demultiplexing. One D
6 is output to the FF4 from the 1/2 divider circuit 2.
The 4 fsc clock shown in (F) is input, and the 4 fs output from the 1/2 divider circuit 2 is input to the other D-FF 5.
The inverted 4fsc clock shown in (F) of FIG. 6 which is obtained by inverting the c clock by the inverter 3 is input. D-FF
4 and 5 demultiplex into RY data and BY data by the clock shown in (F) of FIG.
Color difference signal data shown in or of FIG. 6G can be obtained.

[0006]

By the way, in the above-described line double speed conversion circuit, the input color difference signal data has a phase shown in (C) of FIG. 6 depending on whether the circuit is powered on or off. It is not certain that the phase shown in (C) of FIG. In the television receiver which does not perform the line double speed conversion processing, the color difference signal data is multiplexed by the 2fsc clock shown in or of FIG. 6B, and the 2f shown in or of FIG.
Demultiplex with sc clock. In this case, since the 2fsc clock having the common phase can be used for the multiplex and the demultiplex of the color difference signal data, the input color difference signal data has the phase shown in (C) of FIG. It does not matter whether the phase is as shown in (C).

However, in the line double speed conversion circuit,
2fs used for multiplexing color difference signal data
Since the c clock cannot be used for demultiplexing after the line double speed conversion by the line memory 1, the 4fsc clock shown in FIG. 6 (F) is used as described above. That is, it is not clear whether the color difference signal data input to the line memory 1 has the phase shown in (C) of FIG. 6 or the phase shown in (C) of FIG. The color-difference signal data after demultiplexing output from No. 5 is as shown in or in FIG. 6 (G), and RY data and BY data cannot be defined. Therefore, when the power supply of the circuit is turned on / off, the phases of the RY data and the BY data may be inverted, and there is a problem that an image is broken due to an abnormal hue.

The present invention has been made in view of the above problems, and provides a line double speed conversion circuit capable of preventing an abnormality when demultiplexing multiplexed data after double speed conversion. With the goal.

[0009]

In order to solve the above-mentioned problems of the prior art, the present invention writes data in which the first data and the second data are multiplexed and at the same time every horizontal period. By reading at a double speed, the memory for compressing and outputting the time axis and the data after the double speed conversion output from the memory are demultiplexed by the first and second clocks having a phase inversion relationship with each other. A line double-speed conversion circuit including first and second flip-flops for outputting the first data and the second data, respectively, the first data and the second data in the multiplexed data. Phase detection means for detecting the phase of the phase detection signal and generating a phase detection signal, and the phase inversion with respect to each other based on the phase detection signal output from the phase detection means. The present invention provides a line double speed conversion circuit characterized in that it is provided with a clock selection means for selectively supplying the first and second clocks concerned to the first and second flip-flops. .

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A line double speed conversion circuit of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of a line double speed conversion circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the line double speed conversion circuit of the present invention, and FIG. 3 is a clock phase detection circuit in FIG. 6 is a block diagram showing an example of the configuration of FIG. 6, and FIG. 4 is a clock selection circuit 7 in FIG.
It is a block diagram which shows an example structure. In FIG. 1, the same parts as those in FIG. 5 are designated by the same reference numerals.

The line memory 1 shown in FIG.
The multiplexed color difference signal data shown in (C) or is input. The ½ frequency divider circuit 2 is shown in FIG.
The 8 fsc system clock shown in (D) and FIG.
2 is input, the 1/2 frequency divider circuit 2 outputs the 4fsc clock shown in FIG. 2A in synchronization with the horizontal sync signal. The 4fsc clock is input to the line memory 1 as a write clock, and the 8fsc system clock is input to the line memory 1 as a read clock. The line memory 1 writes the color difference signal data at the 4fsc clock and reads the color difference signal data at the 8fsc system clock to output the color difference signal data at the 8fsc clock rate shown in or of FIG.

The color difference signal data output from the line memory 1 is D-FF 4, 5 for demultiplexing.
Is input to The D-FFs 4 and 5 are in a phase-inverted relationship with each other, and are demultiplexed into RY data and BY data by the 4fsc clock shown in (I) of FIG. Output signal data. Here, 4fsc input to D-FF4, 5
The clock is determined by the clock phase detection circuit 6 and the clock selection circuit 7 provided by the present invention as follows.

The 2fsc clock shown in or of FIG. 2B used when multiplexing the color difference signal data is a pulse having phase information of the multiplexed RY data and BY data, and this 2fsc The clock is input to the clock phase detection circuit 6. Also, 2fs
8fsc shown in FIG. 2D which is the basis of the c clock
The system clock and the horizontal sync signal shown in FIG. 2F are also input to the clock phase detection circuit 6.

As shown in FIG. 3, the clock phase detecting circuit 6 includes a quarter frequency dividing circuit 61, a delay adjusting circuit 62, and DF.
It is composed of F63. 8 in the 1/4 frequency divider circuit 61
fsc system clock and horizontal sync signal are input,
The 1/4 frequency dividing circuit 61 is reset at a timing synchronized with the horizontal synchronizing signal, generates a 2fsc clock, and outputs D
-Supply to FF63. This newly generated 2fsc
The clock is a pulse whose phase is stable even when the power is turned on / off. FIG. 2 is a pulse having phase information of multiplexed RY data and BY data.
The 2fsc clock indicated by or in (B) is input to the D-FF 63 via the delay adjustment circuit 62. DF
The F63 compares the phases of the two input 2fsc clocks and outputs a high / low phase detection signal shown by, in FIG. Note that the delay adjustment circuit 62 uses the D-FF 6
When the rising or falling edges of the two 2fsc clocks input to 3 are aligned, it is for delaying so that the edges are not aligned, and can be deleted if the edges are not aligned.

The phase detection signal thus output from the clock phase detection circuit 6 is input to the clock selection circuit 7. The clock selection circuit 7 includes a 1/2 frequency divider circuit 2
The 4fsc clock shown in FIG. 2 (A) output from the above is also input. The clock selection circuit 7 is composed of an inverter 71 and a selector 72 as shown in FIG. The 4fsc clock is input to the inverter 71, and the inverter 71 inverts the 4fsc clock and outputs the inverted 4fsc clock. Switches 721 and 72 in the selector 72
The inversion 4fsc output from the inverter 71 is applied to the terminal a of 2.
The clock is input, and the 4fsc clock output from the 1/2 frequency divider 2 is input to the terminal b. Selector 7
A phase detection signal output from the clock phase detection circuit 6 (D-FF 63) is input to 2 and switches 721 and 722 in the selector 72 selectively output two types of clocks according to the phase detection signal.

When the phase detection signal output from the clock phase detection circuit 6 is high as shown in FIG. 2 (H), the D-FF 4 in FIG. 1 has 4fs shown in FIG. 2 (I).
c clock is input, and the D-FF5 in FIG.
The switches 721 and 722 in the selector 72 are connected to the terminals b and a, respectively, as shown in the figure, so that the inverted 4fsc clock shown in FIG. In addition, the phase detection signal output from the clock phase detection circuit 6 is shown in FIG.
In the case of low as shown in, the D-FF4 in FIG.
The inverted 4fsc clock shown in (I) of FIG. 2 is input to the D-FF5 in FIG. 1 and the 4fs shown in (2) of FIG.
In order to input the c clock, the switches 721 and 722 in the selector 72 are opposite to the terminals a and
Connect to b.

As described above, in the line double speed conversion circuit of the present invention, after the double speed conversion is performed by the line memory 1, D
-When demultiplexing by FF4,5, R multiplexed by the clock phase detection circuit 6
Since the phases of −Y data and BY data are detected, and two 4fsc clocks which are inverted to each other and are inputted to the D-FFs 4 and 5 by the clock selection circuit 7 are selectively supplied, Even if the RY and BY multiplexing timings of the color difference signal data output from the circuit of FIG.
It is possible to satisfactorily solve the conventional problem that, when turned off, the phases of the RY data and the BY data are inverted and the image is broken due to an abnormal hue.

In the present embodiment, RY data and B-
The case of inputting color difference signal data in which Y data is multiplexed has been described, but the present invention can of course be applied to two different data and signal data in a multiplexed form.

[0019]

As described in detail above, the line double speed conversion circuit of the present invention writes data in which the first data and the second data are multiplexed and reads them at a double speed every horizontal period. Thus, the memory for compressing and outputting the time axis and the double-speed converted data output from the memory are demultiplexed by the first and second clocks having the phase inversion relationship with each other, and the first
In a line double-speed conversion circuit including first and second flip-flops that output the first data and the second data, respectively, and detect the phases of the first data and the second data in the multiplexed data. Based on the phase detection means for generating the phase detection signal and the phase detection signal output from the phase detection means, the first and second clocks having a phase inversion relationship to each other are supplied to the first and second flip-flops. Since the clock selecting means for selectively supplying is provided, the multiplex timing of the first and second data in the multiplexed data of the first and second data output from the circuit at the previous stage is Even under non-constant conditions, it is possible to prevent abnormalities when demultiplexing the data after double-speed conversion.
In particular, two color difference signals R- are used as the first and second data.
In the case of Y and BY, it is possible to satisfactorily solve the problem that the phases of the RY data and the BY data are inverted and the image is broken due to the abnormal hue.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the present invention.

3 is a block diagram showing an example configuration of a clock phase detection circuit 6 in FIG.

FIG. 4 is a block diagram showing an example configuration of a clock selection circuit 7 in FIG.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform diagram for explaining the operation of the conventional example.

[Explanation of symbols]

 1 line memory 2 1/2 frequency dividing circuit 4,5 D flip-flop 6 clock phase detecting circuit 7 clock selecting circuit 61 1/4 frequency dividing circuit 62 delay adjusting circuit 63 D flip-flop 71 inverter 72 selector

Claims (2)

[Claims] 1. A memory for writing data in which first data and second data are multiplexed and reading the data at a double speed for each horizontal period to compress and output the time axis thereof. Demultiplexing the output double-speed converted data by the first and second clocks having a phase inversion relationship with each other, and outputting the first data and the second data respectively. In a line double speed conversion circuit including two flip-flops, phase detecting means for detecting a phase of first data and second data in the multiplexed data, and generating a phase detection signal; Based on a phase detection signal output from the means, the first and second clocks having a phase inversion relationship with each other are supplied to the first and second flip-flops. Line double speed conversion circuit, characterized in that which is configured by providing a selectively supplying clock selection means to flop. 2. The phase detecting means divides a system clock that has generated the first and second clocks and has the same frequency as a third clock having phase information of the first and second data. A frequency divider that generates a fourth clock in synchronization with a horizontal synchronizing signal, and a flip-flop that compares the third clock and the fourth clock to detect the phase of each clock The line double speed conversion circuit according to claim 1, wherein