JPH08250769A - Optical semiconductor element - Google Patents

Abstract

PURPOSE: To provide an optical semiconductor element, which prevents reduction in the durability and deterioration in the vicinity of an electrode from being generated and has an electrode pad, which utilizes efficiently a current which is made to flow. CONSTITUTION: It is found out that an an electrode is formed by an ultrasonic machining at the time of electrode formation, a semiconductor layer under an electrode pad is subjected to damage by an ultrasonic wave and the crystallizability of a semiconductor optical element is reduced to result in a reduction of the durability of the optical element. Therefore, a high-resistance layer (an SiO2 layer) 15, which makes a current hard to flow, is formed thin in the region of a p-type layer under an electrode pad 10 having no relation directly with a light signal. By the existence of this layer 15, the current is made hard to flow under the lower part of the region of the pad 10 and is made to flow to the p-type layer which contributes to the light emission of the element. In the case of an LED, as a current to contribute to the light emission of the LED is increased, the luminous efficiency of the LED is improved. As the current does not flow so much to the region under the pad 10, the generation of a migration is inhibited, the life required as a product of the optical element is prolonged and the quality of the optical element is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical device such as a light emitting device or a photodetector having at least one pn junction, and more particularly to a semiconductor optical device having an electrode pad for wire bonding.

[0002]

2. Description of the Related Art Conventionally, a semiconductor optical device having an electrode pad for wire bonding is a semiconductor chip 500 shown in FIG.
There are many configurations shown in. That is, the side on which the electrode pads 10 and 11 are formed is used as a functional surface such as a light emitting surface or a learning surface. That is, the electrode pad 10 for bonding
Are formed in the light emitting surface (or light receiving surface) region. Normally
Since the pn junction surface serves as a light emitting surface and a light receiving surface, the electrode pad 10 is formed on a part of the surface. Since the other electrode pad 11 is connected to the lower side of the pn junction, a part of the light emitting surface is cut out and the lower semiconductor active layer is exposed. Then, a bonding wire (not shown) is connected to the electrode pads 10 and 11 by using an ultrasonic bonding device or the like, and in the case of a light emitting element (LED), a voltage for light emission is applied when used.

[0003]

However, when a semiconductor optical device having this structure is subjected to a durability test such as a room temperature continuous lighting test or a high temperature continuous lighting test, deterioration occurs in the vicinity of the electrode pad and the product quality is deteriorated. There was a deteriorating problem.

Therefore, an object of the present invention is to provide a semiconductor optical device having a wire bonding electrode that prevents deterioration in the vicinity of the electrode and efficiently utilizes the flowing current so as not to deteriorate the durability.

[0005]

The inventors of the present invention have confirmed that, at the time of wire bonding to this electrode pad, the semiconductor region immediately below the electrode pad is damaged by ultrasonic waves as a bonding means. It is determined that this damage accelerates the deterioration due to migration at the time of energization, and it is determined to prevent energization of a region hidden by the electrode pad and not contributing to light emission or light reception. Therefore, in order to solve the above problems, the structure of the present invention has an electrode pad for wire bonding, and in a semiconductor optical device having at least one pn junction, in the lower part of the electrode pad on the utilization surface of the pn junction. That is, the high-resistance layer for limiting the applied current is provided. Further, in the configuration of the related invention, the high resistance layer is formed under the transparent electrode immediately below the electrode pad. In addition, the characteristic structure is that the high resistance layer is made of silicon oxide (SiO ₂ ).
It is a layer or a silicon nitride (Si ₃ N ₄ ) layer.

[0006]

When the wire bonding electrode is formed, the wire is applied to the electrode pad and the bonding is formed by ultrasonic processing or the like. Therefore, the semiconductor layer under the electrode pad is damaged by the ultrasonic energy, and the crystallinity is deteriorated. Drop,
It was found that the region damaged by the applied current when a voltage was applied caused migration and the like, leading to a decrease in durability. Therefore, a high resistance layer or an insulating layer that makes it difficult for current to flow is formed thinly in the semiconductor region below the electrode pad that is not directly related to an optical signal such as light extraction or light detection. Due to the presence of this high resistance layer, it becomes difficult for current to flow under the electrode pad region, and the current flows through the semiconductor layer other than the electrode pad region that contributes to light emission (or light reception).

The optical element is a light emitting element, and the upper side of the semiconductor layer is p.
When it is a layer, silicon oxide (SiO ₂ ) is formed as a high resistance layer under the electrode pad formed on the layer and through the transparent electrode.
, The p-layer under the silicon oxide (SiO ₂ ) layer has almost no current flowing, and the p-region other than the electrode pad has the current flowing, and is not covered with the electrode pad. Light is emitted in the area. Thus, the high resistance layer prevents the electrodes from flowing into the semiconductor layer below the electrode pad.

[0008]

Since the current does not flow in the semiconductor layer below the electrode pad to be wire-bonded, the semiconductor layer below the electrode pad damaged in the bonding process is
Deterioration is suppressed without further increasing damage. Further, since the current does not flow under the opaque electrode but flows toward the region that contributes to the signal, the conduction current is efficiently used. In the case of an LED, the current that contributes to light emission increases, and thus the light emission efficiency improves. Since a small amount of current does not flow in the region under the electrode pad damaged by bonding, migration is suppressed, the life of the product is extended, and the quality is improved. It can be seen from the remarkable improvement obtained in the accelerated deterioration test.

[0009]

EXAMPLES The present invention will be described below based on specific examples. (First Embodiment) FIG. 1 shows the structure of a GaN-based LED 100 according to the present invention.
_{2 is} a schematic sketch of a case where a silicon oxide (SiO ₂ ) layer 15 is formed under the electrode pad 10. FIG. The substrate of the LED 100 is a sapphire substrate 1, on which a pn junction (p layer 1
3, the n layer 14) is formed in a vertical junction, the transparent electrode 12 serving as the p electrode is formed on the upper surface, and the p electrode pad 10 is formed on a part thereof. This p-electrode pad 10 and FIG.
The n electrode pad 11 as shown in FIG. 3 is electrically connected by bonding with wires (not shown), and is energized to emit light through the p layer. Both electrode pads 11, 1
At least the surface of the wire 2 is formed of a metal material such as aluminum (Al) or gold (Au) for wire bonding.

A high resistance layer 15 of silicon oxide (SiO ₂ ) is formed under the p electrode pad 10, and the p electrode pad 10 (to be exact, in a semiconductor layer region below the high resistance layer 15). No current flows from the transparent electrode 12). Since the current does not pass through the high resistance layer 15 of silicon oxide (SiO ₂ ), it flows through the transparent electrode 12 to the periphery of the high resistance layer 15. After all, as the LED 100, almost all of the current flows to the light emitting surface side where the electrode pad 10 is not provided, and almost all the current flows to the region contributing to light emission.

In the above embodiment, the insulating film is made of silicon oxide (SiO 2
₂ ), but other insulators such as silicon nitride
Of course, an insulating film such as (Si ₃ N ₄ ) may be used.

(Manufacturing Method) A manufacturing method for forming the high resistance layer 15 below the transparent electrode 12 directly below the p electrode pad 10 will be described with reference to FIG. (1) In FIG. 2 (a), each chip in a wafer state is formed by RIE etching into a shape serving as a p region of a light emitting portion of the chip (a shape having a rectangular cutout). The inside of the frame shown in the figure is a portion (p region) left as a light emitting surface in the non-etching region. Here, two chips are shown side by side. An area for separating the two chips is provided. (2) Next, the silicon oxide (SiO ₂ ) layer 15 is formed in the area where the p-electrode pad 10 is to be formed (the rectangular cutout in the lower right of the figure) (FIG. 2 (b)). This is formed using a mask. Then, in some cases, a thin film of titanium (Ti) or chromium (Cr) for contact is formed on the upper surface of the silicon oxide (SiO ₂ ) layer 15. (3) Next, nickel (Ni) was
Å, and the transparent electrode 12 of about 50 Å is formed thereon by gold (Au) by a vapor deposition method or the like (FIG. 2 (c)). (4) Then, the electrode pads 10 and 11 are formed on the p-electrode and the n-electrode, and gold (Au) or aluminum (Al) or nickel (N
Formed in i) to a thickness of about 1.7 μm. When the transparent electrode 12 is made of the same material, only the electrode pad portion is thickly formed. If the material is not the same as that of the transparent electrode 12, an electrode pad is formed by forming a barrier layer as necessary so that the connection surface has ohmic properties (FIG. 2D).

With this structure, the current flowing through the p-electrode pad 10 does not flow in the region under the p-electrode pad 10 but flows through the transparent electrode 12 into the region that contributes to the light emission of the pn junction, and therefore the current is supplied. It is possible to prevent the damage immediately under the electrode pad from increasing or the deterioration of the durability.

(Second Embodiment) FIG. 3 shows a p-electrode pad 10
FIG. 3 is a schematic structural cross-sectional view of the portion of FIG. In FIG. 1, a part of the p layer is cut out to form a silicon oxide (SiO ₂ ) layer 15, but here, a silicon oxide (SiO ₂ ) layer 16 is formed on the p layer 13 to form an insulating layer (high resistance layer). ) Is used as an example.
In this case, the silicon oxide (SiO ₂ ) layer (high resistance layer) used 1
6 does not need to be formed thick (note that FIG. 3 does not reflect the film thickness ratio). However, this silicon oxide (SiO ₂ ) layer 16
Exists as a mask for blocking the electron beam when the semiconductor layer 13 is irradiated with the electron beam to form the p-conductivity type, and therefore the portion below the silicon oxide (SiO ₂ ) layer 16 of the semiconductor layer 13 is a region without a mask. Carrier concentration is lower than that. That is, the resistance remains high. Then, the transparent electrode 12 is formed on the p layer 13 including the region above this. In some cases,
As illustrated, a barrier layer 17 of titanium (Ti) or chromium (Cr) that prevents the formation of silicide may be thinly formed on the silicon oxide (SiO ₂ ) layer 16.

Then, the p electrode pad 10 is formed on the transparent electrode 12 on the region where the silicon oxide (SiO ₂ ) layer 16 is formed by vapor deposition or the like. Even if the high resistance layer 16 is formed in this manner, the current flowing through the p electrode is small because the p layer 13 is thin.
The p-layer 13 does not go under the electrode pad 10 and flows in a region that contributes to light emission. A silicon nitride (Si ₃ N ₄ ) layer or another insulating layer may be used instead of the silicon oxide (SiO ₂ ) layer.

(Third Embodiment) FIG. 4 is a schematic sectional view showing the cross section of the p-electrode portion of the GaN-based LED 200. This LED 200 has a p-AlGaN (Mg-doped) layer 36 and a GaN (Mg-doped) layer which are clad layers when a p-layer is formed on the upper side.
The layer 37 is obtained by electron beam irradiation. Here, the electron beam irradiation is not applied to all the regions, and the p-electrode pad 1 is formed with the silicon oxide (SiO ₂ ) mask 38 as shown in FIG.
The region where 0 is formed is covered so that the electron beam is not irradiated. By doing so, the cladding layer 36 and the GaN
Layer 37 does not become p-conducting and remains highly resistive. After that, if the mask 38 is removed and the transparent electrode 12 is formed on the mask 38, the high-resistance layer remains formed in the lower region of the p electrode pad 10 (hatched portions 36 and 37 in FIG. 4). Therefore, even if this area is damaged by bonding, this area is hardly energized and damage is unlikely to increase, and the life of the LED can be extended.

[Brief description of drawings]

FIG. 1 is a schematic configuration sketch of a semiconductor optical device (GaN-based LED) of the present invention.

FIG. 2 is a method for forming the configuration of the semiconductor optical device of the present invention.

FIG. 3 is a schematic configuration sectional view of a GaN-based LED (a part) of the second embodiment.

FIG. 4 is a schematic configuration cross-sectional view of a GaN-based LED (a part) of the third embodiment.

FIG. 5 is a schematic diagram of a conventional semiconductor optical device.

[Explanation of symbols]

100, 200 Semiconductor optical device (nitrogen compound semiconductor light emitting device) 1 Sapphire substrate 10 p electrode pad 11 n electrode pad 12 transparent electrode 13 p layer (semiconductor active layer) 14 n layer (semiconductor active layer) 15 high resistance layer (oxidation) Silicon (SiO ₂ ) insulating layer 16 High resistance layer (silicon oxide (SiO ₂ ) insulating layer) 17 Barrier layer (titanium (Ti), chromium (Cr), etc.) 35 Bonding layer other than p layer (i layer and n layer) ) 36 clad layer (AlGaN (P, Mg-doped)) 37 GaN (P, Mg-doped) layer 38 mask (silicon oxide (SiO ₂ ))

Claims (3)

[Claims] 1. A semiconductor optical device having an electrode pad for wire bonding and having at least one pn junction, wherein a high resistance layer for limiting a current flowing is provided below the electrode pad on a utilization surface of the pn junction. A semiconductor light emitting device characterized by the above. 2. The high resistance layer is formed under a transparent electrode immediately below the electrode pad.
The semiconductor light-emitting device according to. 3. The semiconductor light emitting device according to claim 1, wherein the high resistance layer is a silicon oxide (SiO ₂ ) layer or a silicon nitride (Si ₃ N ₄ ) layer.