JP3841460B2 - Semiconductor optical device - Google Patents

Semiconductor optical device Download PDF

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JP3841460B2
JP3841460B2 JP8194995A JP8194995A JP3841460B2 JP 3841460 B2 JP3841460 B2 JP 3841460B2 JP 8194995 A JP8194995 A JP 8194995A JP 8194995 A JP8194995 A JP 8194995A JP 3841460 B2 JP3841460 B2 JP 3841460B2
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layer
electrode
electrode pad
optical device
semiconductor optical
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JPH08250769A (en
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典克 小出
潤一 梅崎
正巳 山田
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Toyoda Gosei Co Ltd
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Toyoda Gosei Co Ltd
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【０００１】
【産業上の利用分野】
本発明は、pn接合を少なくとも一つ有する発光素子あるいは光検出素子等の半導体光素子に関し、特に、ワイヤボンディング用の電極パッドを有する半導体光素子に関する。
【０００２】
【従来の技術】
従来、ワイヤボンディング用の電極パッドを有する半導体光素子は、図５の半導体チップ５００で示される構成が多い。即ち、電極パッド１０、１１が形成された側が発光面または受光面という機能面として利用される。つまり、ボンディング用の電極パッド１０を発光面（または受光面）領域に形成している。通常はpn接合面が発光面、受光面となるので、その面の一部の上に電極パッド１０を形成した構成としている。またもう一方の電極パッド１１は、pn接合の下側と接続するため、発光面の一部を切り欠き、下側の半導体活性層を露出させて形成してある。そして電極パッド１０、１１の上に、超音波ボンディング装置等を用いて図示しないボンディングワイヤを接続させ、発光素子（ LED）の場合では、利用する際に発光のための電圧を印加する。
【０００３】
【発明が解決しようとする課題】
しかしながら、この構造の半導体光素子において、室温連続点灯試験や高温連続点灯試験などの耐久試験を実施すると、電極パッド付近で劣化が生じて、製品としての品質を低下させている問題があった。
【０００４】
従って本発明の目的は、耐久性を低下させないために、電極付近の劣化を防ぎ、流れる電流を効率良く利用するワイヤボンディング電極を有する半導体光素子を提供することである。
【０００５】
【課題を解決するための手段】
発明者らは、この電極パッドにワイヤボンディングする際に、電極パッド直下の半導体領域に、ボンディング手段である超音波によってダメージが与えられていることを確認したので、このダメージが、通電時にマイグレーションとして劣化を早めていると判定し、電極パッドに隠れて発光または受光に寄与しない領域を通電させないようにすることが解決する手段と判断した。そこで、上記の課題を解決するため本発明の構成は、
pn接合を少なくとも一つ有し、ワイヤボンディング用のｐ及びｎの電極パッドをpn接合の利用面側に両方とも有する半導体光素子において、ｐ及びｎの電極パッドは矩形状の素子の対角の位置に配設されるものであり、この半導体光素子はGaN系半導体を積層して形成され、 pn接合の利用面の上部を覆う透明電極が形成されており、透明電極の下部において 、ｐの電極パッドが配設されるべき矩形状の素子の一角に通電電流を制限する、上面に透明電極のシリサイドの形成を防ぐチタン又はクロムから成るバリア層を有する酸化シリコン (SiO 2 ) または窒化シリコン (Si 3 N 4 ) から成る高抵抗層を有し、透明電極の上であって、高抵抗層の上部にｐの電極パッドを設けたことである。
【０００６】
【作用】
ワイヤボンディング電極を形成する際に、ワイヤを電極パッドにあてて超音波加工等によりボンディングを形成することから、電極パッド下のGaN系半導体層が超音波のエネルギーでダメージを受け、結晶性が低下して、電圧を印加した際の通電電流によってダメージを受けた領域がマイグレージョン等を引き起こし、耐久性低下につながっていることが判明した。そのため、光取り出しまたは光検出等の光信号に直接関係しない電極パッド下部のGaN系半導体領域に、電流を流しにくくする高抵抗層もしくは絶縁層を薄く形成する。この高抵抗層の存在によって電流は電極パッド領域下部には流れにくくなり、電極パッド領域以外の発光（もしくは受光）に寄与するGaN系半導体層に流れる。
【０００７】
光素子が発光素子で、GaN系半導体層の上側がｐ層である時、その上に形成される電極パッドの下部、透明電極を介した下に高抵抗層として酸化シリコン(SiO2)が形成してある場合、この酸化シリコン(SiO2)層の下のｐ層にはほとんど電流が流れず、電極パッドが形成された以外のｐ領域で電流が流れ、電極パッドで覆われていない領域で発光される。このように、高抵抗層は電極パッドの下のGaN系半導体層に電極を流さないようにする。
【０００８】
【発明の効果】
ワイヤボンディングされる電極パッドの下部のGaN系半導体層に電流が流れないので、ボンディング工程でダメージを受けた、電極パッド下部のGaN系半導体層が、それ以上ダメージを増大させず、劣化が抑制される。また不透明な電極の下部には電流が流れず、信号に寄与する領域側に流れるので、通電電流が効率的に利用される。 LEDの場合、発光に寄与する電流が多くなることから、発光効率が向上する。ボンディングでダメージを受けている電極パッド下の領域にはあまり電流が流れないため、マイグレーションが抑制され、製品としての寿命が長くなり、品質が向上する。それは加速劣化試験において、著しい改善が得られていることからも判る。
【０００９】
【実施例】
以下、本発明を具体的な実施例に基づいて説明する。
（第一実施例）
図１は、本発明をGaN 系LED １００のｐ電極パッド１０の下部に酸化シリコン(SiO2)層１５を形成した場合の模式的見取り図である。LED １００の基板はサファイヤ基板１であり、その上にpn接合（ｐ層１３、ｎ層１４）が縦型接合に形成され、上面にｐ電極となる透明電極１２が形成され、その一部にｐ電極パッド１０が形成されている。このｐ電極パッド１０と、図１に示すようなｎ電極パッド１１とに、それぞれ図示しないワイヤでボンディングされて電気的接続がなされ、通電してｐ層を通して発光させる。両電極パッド１１、１２はワイヤボンディングするために少なくともその表面がアルミ(Al)や金(Au)などの金属材料で形成されている。
【００１０】
このｐ電極パッド１０の下に、酸化シリコン(SiO2)の高抵抗層１５が形成してあり、その高抵抗層１５から下の半導体層領域にはｐ電極パッド１０（正確には透明電極１２）から電流が流れないようになっている。電流は酸化シリコン(SiO2)の高抵抗層１５を通過しないため、透明電極１２を介して高抵抗層１５の周辺に流れる。結局、 LED１００として、電極パッド１０のない発光面側にほとんど流れ、電流が発光に寄与する領域へほとんど流れる。
【００１１】
上の実施例では絶縁膜を酸化シリコン(SiO2)で示したが、これ以外の絶縁体、例えば窒化シリコン(Si3N4) などの絶縁膜でももちろん構わない。
【００１２】
（製法）
ここでｐ電極パッド１０直下で透明電極１２の下部に高抵抗層１５を形成する製造方法を図２を用いて説明する。
(1) 図２(a) でウエハ状態の各チップにＲＩＥエッチングによってチップの発光部分のｐ領域となる形状（矩形に一部切り欠きを有する形状）を形成する。図に示した枠内は非エッチング領域で発光面として残す部分（ｐ領域）である。ここでは各チップが二つ並んでいる所を示してある。二つのチップの間は分離するための領域である。
(2) 次に、ｐ電極パッド１０を形成する範囲（図の右下の矩形切り欠き部）に酸化シリコン(SiO2)層１５を形成する（図２(b))。これはマスクを用いて形成する。そして場合によっては、その酸化シリコン(SiO2)層１５上面に、コンタクト用のチタン(Ti)もしくはクロム(Cr)の薄膜を形成する。
(3) 次にこのｐ領域全体にわたってニッケル(Ni)を20Å、その上に金(Au)を50Å程度の透明電極１２を蒸着法などで形成する（図２(c))。
(4) そしてその上に電極パッド１０および１１をｐ電極とｎ電極に、金(Au)またはアルミ(Al)またはニッケル(Ni)で 1.7μｍ程度の厚さに形成する。透明電極１２と同じ材料で形成する場合、電極パッド部分だけを厚く形成する形になる。透明電極１２と同一でない材料の場合は、接続面がオーミック性を持つように、必要に応じてバリア層を形成するなどして電極パッドを形成する（図２(d))。
【００１３】
このような構成とすることで、ｐ電極パッド１０を流れる電流はｐ電極パッド１０下部の領域を流れずに、透明電極１２を通じてpn接合の発光に寄与する領域へと流れるため、通電による電極パッド直下部分のダメージ拡大、あるいは耐久性低下が抑制される。
【００１４】
（第二実施例）
図３は、ｐ電極パッド１０の部分を横から見た模式的構造断面図である。図１ではｐ層の一部を切り欠いて酸化シリコン(SiO2)層１５としたが、ここでは酸化シリコン(SiO2)層１６をｐ層１３の上に形成して絶縁層（高抵抗層）として使う例である。この場合、用いる酸化シリコン(SiO2)層（高抵抗層）１６は厚く形成する必要はない（なお図３は膜厚の比を反映していない）。しかしこの酸化シリコン(SiO2)層１６は、電子線照射して半導体層１３をｐ伝導型に形成する際に電子線を遮るマスクとして存在するので、半導体層１３の酸化シリコン(SiO2)層１６の下の部分はマスクのない領域よりはキャリア濃度が少ない。すなわち高抵抗のままとなる。そしてこの上の領域も含めてｐ層１３の上に透明電極１２を形成する。なお、場合によっては、図示したように、酸化シリコン(SiO2)層１６の上にシリサイドの形成を防ぐチタン(Ti)やクロム(Cr)のバリア層１７を薄く形成しても良い。
【００１５】
そして透明電極１２の上から、酸化シリコン(SiO2)層１６を形成した領域上にｐ電極パッド１０を蒸着等で形成する。このように高抵抗層１６を形成してもｐ電極を流れる電流は、ｐ層１３の厚さが薄いので、ｐ層１３の電極パッド１０の下側には回り込まず、発光に寄与する領域を流れる。なお酸化シリコン(SiO2)層の代わりに窒化シリコン(Si3N4) 層や他の絶縁層を用いても良い。
【００１６】
（第三実施例）
図４はGaN 系LED ２００におけるｐ電極部分の断面を示した模式的構成断面図である。この LED２００は上側にｐ層を形成する際にクラッド層である p-AlGaN(Mg-doped)層３６とGaN(Mg-doped) 層３７に電子線照射して得ている。ここで電子線照射を全ての領域に施さないで、図３に示すようなイメージで、酸化シリコン(SiO2)のマスク３８でｐ電極パッド１０が形成される領域を覆って電子線が照射されないようにする。そうすることで、クラッド層３６、およびGaN 層３７はｐ伝導型とならず高抵抗のままとなる。その後、マスク３８を除去して、その上に透明電極１２を形成すれば、ｐ電極パッド１０の下側領域には高抵抗な層が形成されたまま（図４の３６、３７のハッチング部分）となり、ボンディングによってこの領域がダメージを受けたとしても、この領域にはほとんど通電されずにダメージを増大しにくく、LED の寿命を伸ばすことができる。
【図面の簡単な説明】
【図１】 本発明の半導体光素子(GaN系LED)の模式的構成見取り図。
【図２】 本発明の半導体光素子の構成の形成方法。
【図３】 第二実施例のGaN 系LED(一部）の模式的構成断面図。
【図４】 第三実施例のGaN 系LED(一部）の模式的構成断面図。
【図５】 従来の半導体光素子の模式的構成見取り図。
【符号の説明】
１００、２００ 半導体光素子（窒素化合物系半導体発光素子）
１ サファイヤ基板
１０ ｐ電極パッド
１１ ｎ電極パッド
１２ 透明電極
１３ ｐ層（半導体活性層）
１４ ｎ層（半導体活性層）
１５ 高抵抗層（酸化シリコン(SiO2)絶縁層）
１６ 高抵抗層（酸化シリコン(SiO2)絶縁層）
１７ バリア層（チタン(Ti)やクロム(Cr)など）
３５ ｐ層以外の接合層（ｉ層およびｎ層）
３６ クラッド層（AlGaN(P,Mg-doped))
３７ GaN( P, Mg-doped) 層
３８ マスク（酸化シリコン(SiO2)）[0001]
[Industrial application fields]
The present invention relates to a semiconductor optical device such as a light emitting device or a light detection device having at least one pn junction, and more particularly to a semiconductor optical device having an electrode pad for wire bonding.
[0002]
[Prior art]
Conventionally, a semiconductor optical device having an electrode pad for wire bonding has many configurations shown by a semiconductor chip 500 in FIG. That is, the side on which the electrode pads 10 and 11 are formed is used as a functional surface called a light emitting surface or a light receiving surface. That is, the electrode pad 10 for bonding is formed in the light emitting surface (or light receiving surface) region. Usually, since the pn junction surface becomes a light emitting surface and a light receiving surface, the electrode pad 10 is formed on a part of the surface. The other electrode pad 11 is formed by notching part of the light emitting surface and exposing the lower semiconductor active layer in order to connect to the lower side of the pn junction. A bonding wire (not shown) is connected to the electrode pads 10 and 11 using an ultrasonic bonding apparatus or the like, and in the case of a light emitting element (LED), a voltage for light emission is applied when used.
[0003]
[Problems to be solved by the invention]
However, when a semiconductor optical device having this structure is subjected to an endurance test such as a room temperature continuous lighting test or a high temperature continuous lighting test, there is a problem that deterioration occurs in the vicinity of the electrode pad and the quality as a product is lowered.
[0004]
Accordingly, an object of the present invention is to provide a semiconductor optical device having a wire bonding electrode that prevents deterioration near the electrode and efficiently uses a flowing current so as not to lower the durability.
[0005]
[Means for Solving the Problems]
The inventors have confirmed that, when wire bonding to this electrode pad, the semiconductor region immediately below the electrode pad is damaged by the ultrasonic wave that is a bonding means. It was determined that the deterioration was accelerated, and it was determined as a means to solve the problem that the region hidden behind the electrode pad and not contributing to light emission or light reception was not energized. Therefore, in order to solve the above problems, the configuration of the present invention is as follows.
having at least one pn junction, the semiconductor optical device having both an electrode pad of the p and n for wire bonding to the use surface side of the pn junction, the electrode pads of the p and n diagonal of the rectangular element is intended to be disposed at a position, the semiconductor optical device is formed by stacking a GaN-based semiconductor, and a transparent electrode covering the upper portion of the usage surface of the pn junction is formed in the lower portion of the transparent electrode, the p Silicon oxide (SiO 2 ) or silicon nitride with a barrier layer made of titanium or chromium that limits the conduction current to one corner of the rectangular element in which the electrode pad is to be disposed and prevents the formation of a transparent electrode silicide on the upper surface ( It has a high resistance layer made of Si 3 N 4 ) and is provided with a p electrode pad on the transparent electrode and on the high resistance layer.
[0006]
[Action]
When forming a wire bonding electrode, the wire is applied to the electrode pad and bonding is performed by ultrasonic processing, etc., so the GaN-based semiconductor layer under the electrode pad is damaged by ultrasonic energy and the crystallinity is lowered. Thus, it was found that the area damaged by the energization current when the voltage was applied caused migration and the like, leading to a decrease in durability. Therefore, a high-resistance layer or insulating layer that makes it difficult for current to flow is formed thinly in a GaN-based semiconductor region under the electrode pad that is not directly related to an optical signal such as light extraction or light detection. Due to the presence of the high resistance layer, current hardly flows below the electrode pad region and flows to the GaN-based semiconductor layer contributing to light emission (or light reception) other than the electrode pad region.
[0007]
When the optical element is a light-emitting element and the upper side of the GaN-based semiconductor layer is a p-layer, silicon oxide (SiO 2 ) is formed as a high resistance layer under the electrode pad formed on the upper side and below the transparent electrode In this case, almost no current flows in the p layer under the silicon oxide (SiO 2 ) layer, and the current flows in the p region other than the electrode pad formed, and is not covered with the electrode pad. Emits light. Thus, the high resistance layer prevents the electrode from flowing through the GaN-based semiconductor layer under the electrode pad.
[0008]
【The invention's effect】
Since no current flows through the GaN-based semiconductor layer under the electrode pad to be wire-bonded, the GaN-based semiconductor layer under the electrode pad that was damaged during the bonding process does not increase further damage and suppress deterioration. The In addition, current does not flow below the opaque electrode, but flows to the region that contributes to the signal, so that the energized current is efficiently used. In the case of an LED, since the current contributing to light emission increases, the light emission efficiency is improved. Since current does not flow so much in the region under the electrode pad that is damaged by bonding, migration is suppressed, the product life is extended, and the quality is improved. This can also be seen from the fact that significant improvements have been obtained in the accelerated deterioration test.
[0009]
【Example】
Hereinafter, the present invention will be described based on specific examples.
(First Example)
FIG. 1 is a schematic sketch of the present invention when a silicon oxide (SiO 2 ) layer 15 is formed under a p-electrode pad 10 of a GaN-based LED 100. The substrate of the LED 100 is a sapphire substrate 1, on which a pn junction (p layer 13 and n layer 14) is formed as a vertical junction, a transparent electrode 12 serving as a p electrode is formed on the upper surface, and a part thereof A p-electrode pad 10 is formed. The p-electrode pad 10 and the n-electrode pad 11 as shown in FIG. 1 are bonded to each other by wires (not shown) to be electrically connected, and energized to emit light through the p-layer. Both electrode pads 11 and 12 are formed of a metal material such as aluminum (Al) or gold (Au) at least on the surface for wire bonding.
[0010]
A high resistance layer 15 of silicon oxide (SiO 2 ) is formed under the p electrode pad 10, and the p electrode pad 10 (precisely, the transparent electrode 12) is formed in the semiconductor layer region below the high resistance layer 15. ) Current does not flow from. Since the current does not pass through the high resistance layer 15 of silicon oxide (SiO 2 ), it flows to the periphery of the high resistance layer 15 via the transparent electrode 12. Eventually, the LED 100 almost flows to the light emitting surface side without the electrode pad 10, and the current almost flows to a region contributing to light emission.
[0011]
In the above embodiment, the insulating film is shown by silicon oxide (SiO 2 ), but other insulating materials such as silicon nitride (Si 3 N 4 ) may of course be used.
[0012]
(Manufacturing method)
A manufacturing method for forming the high resistance layer 15 directly below the p electrode pad 10 and below the transparent electrode 12 will be described with reference to FIG.
(1) In FIG. 2 (a), each chip in the wafer state is formed by RIE etching to form a p-region of the light emitting portion of the chip (a shape having a partially cutout rectangle). The inside of the frame shown in the figure is a portion (p region) left as a light emitting surface in the non-etched region. Here, two chips are shown side by side. An area for separating the two chips.
(2) Next, a silicon oxide (SiO 2 ) layer 15 is formed in the area where the p-electrode pad 10 is to be formed (the rectangular cutout at the lower right in the figure) (FIG. 2 (b)). This is formed using a mask. In some cases, a thin film of contact titanium (Ti) or chromium (Cr) is formed on the upper surface of the silicon oxide (SiO 2 ) layer 15.
(3) Next, a transparent electrode 12 of about 20 mm of nickel (Ni) and about 50 mm of gold (Au) is formed over the entire p region by vapor deposition (FIG. 2 (c)).
(4) Then, electrode pads 10 and 11 are formed thereon with gold (Au), aluminum (Al) or nickel (Ni) to a thickness of about 1.7 μm on the p electrode and the n electrode. When the transparent electrode 12 is formed from the same material, only the electrode pad portion is formed thick. In the case of a material that is not the same as that of the transparent electrode 12, an electrode pad is formed by forming a barrier layer as necessary so that the connection surface has ohmic properties (FIG. 2 (d)).
[0013]
With this configuration, the current flowing through the p-electrode pad 10 does not flow through the region below the p-electrode pad 10, but flows through the transparent electrode 12 to a region contributing to light emission of the pn junction. The expansion of damage directly underneath or the decrease in durability are suppressed.
[0014]
(Second embodiment)
FIG. 3 is a schematic structural cross-sectional view of the p-electrode pad 10 viewed from the side. In FIG. 1, a part of the p layer is notched to form a silicon oxide (SiO 2 ) layer 15, but here a silicon oxide (SiO 2 ) layer 16 is formed on the p layer 13 to form an insulating layer (high resistance layer). ). In this case, the silicon oxide (SiO 2 ) layer (high resistance layer) 16 to be used need not be formed thick (note that FIG. 3 does not reflect the film thickness ratio). However, this silicon oxide (SiO 2) layer 16, since there as a mask to block the electron beam in forming the p conductivity type semiconductor layer 13 by irradiating an electron beam, a silicon oxide (SiO 2) of the semiconductor layer 13 layer The portion below 16 has a lower carrier concentration than the area without the mask. That is, the high resistance remains. Then, the transparent electrode 12 is formed on the p layer 13 including the region above this. In some cases, as shown in the drawing, a barrier layer 17 of titanium (Ti) or chromium (Cr) for preventing the formation of silicide may be formed thinly on the silicon oxide (SiO 2 ) layer 16.
[0015]
Then, a p-electrode pad 10 is formed on the transparent electrode 12 by vapor deposition or the like on the region where the silicon oxide (SiO 2 ) layer 16 is formed. Even if the high resistance layer 16 is formed in this way, the current flowing through the p-electrode does not go under the electrode pad 10 of the p-layer 13 because the thickness of the p-layer 13 is thin, and a region contributing to light emission is not formed. Flowing. Note that a silicon nitride (Si 3 N 4 ) layer or another insulating layer may be used instead of the silicon oxide (SiO 2 ) layer.
[0016]
(Third embodiment)
FIG. 4 is a schematic cross-sectional view showing a cross-section of the p-electrode portion in the GaN-based LED 200. The LED 200 is obtained by irradiating a p-AlGaN (Mg-doped) layer 36 and a GaN (Mg-doped) layer 37, which are cladding layers, with an electron beam when a p-layer is formed on the upper side. Here, the electron beam irradiation is not performed on the entire region, and the image shown in FIG. 3 is not irradiated with the electron beam so as to cover the region where the p-electrode pad 10 is formed with the mask 38 of silicon oxide (SiO 2 ). Like that. By doing so, the cladding layer 36 and the GaN layer 37 do not become p-conductivity type and remain high resistance. After that, if the mask 38 is removed and the transparent electrode 12 is formed thereon, a high resistance layer is still formed in the lower region of the p-electrode pad 10 (hatched portions 36 and 37 in FIG. 4). Thus, even if this area is damaged by bonding, the area is hardly energized and the damage is hardly increased, and the life of the LED can be extended.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a configuration of a semiconductor optical device (GaN-based LED) according to the present invention.
FIG. 2 shows a method for forming a structure of a semiconductor optical device according to the present invention.
FIG. 3 is a schematic sectional view of a GaN-based LED (partially) according to a second embodiment.
FIG. 4 is a schematic sectional view of a GaN-based LED (partially) according to a third embodiment.
FIG. 5 is a schematic configuration diagram of a conventional semiconductor optical device.
[Explanation of symbols]
100, 200 Semiconductor optical device (nitrogen compound semiconductor light emitting device)
1 Sapphire substrate
10 p electrode pad
11 n electrode pad
12 Transparent electrode
13 p layer (semiconductor active layer)
14 n layer (semiconductor active layer)
15 High resistance layer (silicon oxide (SiO 2 ) insulating layer)
16 High resistance layer (silicon oxide (SiO 2 ) insulating layer)
17 Barrier layer (titanium (Ti), chromium (Cr), etc.)
Joining layer other than 35 p layer (i layer and n layer)
36 Clad layer (AlGaN (P, Mg-doped))
37 GaN (P, Mg-doped) layer
38 Mask (Silicon oxide (SiO 2 ))

Claims (1)

pn接合を少なくとも一つ有し、ワイヤボンディング用のｐ及びｎの電極パッドを前記pn接合の利用面側に両方とも有する半導体光素子において、
前記ｐ及びｎの電極パッドは矩形状の素子の対角の位置に配設されるものであり、
当該半導体光素子はGaN系半導体を積層して形成され、
前記pn接合の利用面の上部を覆う透明電極が形成されており、
前記透明電極の下部において、前記ｐの電極パッドが配設されるべき矩形状の素子の一角に通電電流を制限する、上面に前記透明電極のシリサイドの形成を防ぐチタン又はクロムから成るバリア層を有する酸化シリコン (SiO 2 ) または窒化シリコン (Si 3 N 4 ) から成る高抵抗層を有し、
前記透明電極の上であって、前記高抵抗層の上部にｐの電極パッドを設けた
ことを特徴とする半導体光素子。In a semiconductor optical device having at least one pn junction and having both p and n electrode pads for wire bonding on the use surface side of the pn junction,
The p and n electrode pads are arranged at diagonal positions of a rectangular element,
The semiconductor optical device is formed by stacking GaN-based semiconductors,
A transparent electrode is formed to cover the upper part of the use surface of the pn junction,
Under the transparent electrode, a barrier layer made of titanium or chromium is formed on the upper surface to limit the conduction current to one corner of the rectangular element in which the electrode pad of p is to be disposed, and to prevent silicide formation of the transparent electrode. Having a high resistance layer consisting of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) ,
A semiconductor optical device, wherein a p-electrode pad is provided on the transparent electrode and on the high resistance layer.
JP8194995A 1995-03-13 1995-03-13 Semiconductor optical device Expired - Lifetime JP3841460B2 (en)

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