JPH08249089A - Device provided with reset control circuit - Google Patents

Abstract

PURPOSE: To stably reset each circuit without increasing the number of signal lines by providing a first reset signal line, which transmits a reset operation start signal to plural circuits, and a second reset signal line which transmits a reset operation continuing signal to plural circuits. CONSTITUTION: A reset control circuit 10 transmits the first reset signal and the second reset signal to circuits 11 to 1n through signal lines 110 and 111. Each of circuits 11 to 1n receives the first reset signal; and if an internal circuit 105 can be reset, a reset response signal is transmitted through a signal line 121, and the internal circuit 105 is reset. After continuing the transmission of the first reset for a prescribed time by the reset response signal whose transmission is terminated last out of reset response signals, the reset control circuit 10 terminates the transmission. The reset control circuit 10 detects the end of transmission of the last reset response signal to terminate the transmission of the second reset signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device having a reset control circuit, and more particularly to a device having a circuit for performing control when resetting a plurality of circuits in the device.

[0002]

2. Description of the Related Art Conventionally, in an information processing device, when the power of the device is turned on, when the device malfunctions, and when the device malfunctions, a reset signal from a reset control circuit is distributed to each circuit in the device to operate the device. Is being stabilized.

However, in the conventional method, since the signal flow is only in one direction and the reset control circuit cannot detect the state of each circuit, resetting of the device may be incomplete. . That is, the reset control circuit cannot know whether or not the reset signal has properly reached each circuit.

For this reason, a method has been proposed in which, in addition to the reset signal, a reset response signal from each circuit is provided to perform stable resetting by the handshake of these two signal lines.

FIG. 6 is a diagram showing an apparatus having the reset method by the handshake. In the reset control circuit 60, the timing control means 603 responds to the connected circuit 61 by a reset request from an abnormality detection means 601 for detecting an abnormality in voltage and a reset request detection means 602 for detecting a reset request from the outside. Then, the reset signal 610 is output.

The circuit 61 receives the reset signal 610 by the timing control means 604, and the internal circuit 605.
Reset response signal 62
0 is output to the reset control circuit 60 to reset the internal circuit 605.

When the internal circuit 605 includes a memory or the like,
Since it is necessary to back up the contents before resetting, the internal circuit 605 is received immediately after receiving the reset signal.
Cannot be reset. In this way, if the reset of the internal circuit 605 is impossible at the time of receiving the reset signal, the timing control unit 604.
Instructs the internal circuit 605 to satisfy a condition enabling resetting, and after the internal circuit 605 satisfies the condition, outputs a reset response signal 620 to the reset control circuit to reset the internal circuit 605.

By receiving the reset response signal 620, the reset control circuit 60 can know that the reset signal 610 has been accepted by the circuit 61.

When ending the reset, the reset control circuit 60 invalidates the reset signal 610.

When the circuit 61 detects that the reset signal 610 has become invalid, the circuit 61 prepares for ending the reset.
For example, when the internal circuit 605 includes a memory having a backup function, a procedure for restoring the backed up contents is necessary.

When the preparation for ending the reset is completed, the circuit 61
Resets the reset response signal 620 and performs normal operation.

[0012]

However, the conventional method has a drawback that it cannot cope with a complicated and large-scale apparatus.

In the above-mentioned conventional example, the reset control circuit and the circuit are made to correspond one-to-one, but in an actually used device, the whole is more complicated and large-scale, and therefore, it is connected to the reset control circuit. It is necessary to divide the circuit to be reset and perform the reset with a one-to-n configuration of one reset control circuit and a plurality of circuits.

In this case, the handshake method is as follows:
Since one set of reset signal line and one set of reset response signal line are required for a plurality of circuits, if there are n connected circuits, 2 × n signal lines are required.

Further, since the respective handshakes are performed asynchronously, the timings at which the respective circuits return to the normal operation after completion of the reset are different from each other, and a means for synchronizing all the circuits is further required.

The present invention has been made to solve the above problems, and provides an apparatus including a reset control circuit capable of stably resetting each circuit in the apparatus without increasing the number of signal lines to be connected. The purpose is to provide.

[0017]

According to the present invention, the aforementioned object is an apparatus including a plurality of circuits and a reset control circuit for controlling a reset operation of the plurality of circuits, wherein the plurality of circuits and the reset control circuit are provided. The control circuit includes a first reset signal line for transmitting a first reset signal for starting a reset operation from the control circuit to the plurality of circuits, and starting and ending the reset operation from each of the plurality of circuits. A reset response signal line for individually transmitting a reset response signal indicating to the control circuit, and a second reset signal for transmitting a second reset signal for continuing the reset operation from the control circuit to the plurality of circuits. It is achieved by an apparatus comprising a reset control circuit according to claim 1, characterized in that they are connected by a signal line.

According to the present invention, for the above-mentioned object, the control circuit detects the start and end of the reset operation of the plurality of circuits individually by the reset response signal, and the first reset signal. Setting means for setting a predetermined time until the end of the transmission of, and the predetermined time when the start of the reset operation of the plurality of circuits is all detected by simultaneously transmitting the first and second reset signals. When the transmission of the first reset signal is completed after the passage of time and all of the reset operations of the plurality of circuits are detected, the second reset signal is detected.
And a means for terminating the transmission of the reset signal according to claim 1, wherein the reset control circuit according to claim 2 is provided.

According to the present invention, for the above-mentioned object, the control circuit individually detects the start and end of the reset operation of the plurality of circuits by the reset response signal, and the first reset signal. And a means for transmitting the second reset signal when all the start of reset operations of the plurality of circuits are detected by the device including the reset control circuit according to claim 3. To be achieved.

According to the present invention, for the above-mentioned purpose, the control circuit transmits the second reset signal, and a setting means for setting a predetermined time until the transmission of the first reset signal is completed. And ending the transmission of the first reset signal after the elapse of the predetermined time, and ending the transmission of the second reset signal when all the reset operations of the plurality of circuits are detected. The present invention is achieved by an apparatus including a reset control circuit according to claim 4, further comprising:

According to the present invention, for the above-mentioned purpose, one end of the reset response signal line is connected to each of the plurality of circuits, and the other end is wired-OR connection to form one signal line as the control signal. A device comprising a reset control circuit according to claim 5, characterized in that it is connected to a circuit.

According to the present invention, for the above-mentioned purpose, the control circuit sets the predetermined time until the transmission of the first reset signal is completed, and the first and second setting means.
Reset signals are transmitted at the same time, and when the start of the reset operation is detected by the reset response signal line, the transmission of the first reset signal is ended after the elapse of the predetermined time, and the reset operation is performed by the reset response signal line. Means for terminating the transmission of the second reset signal when the end of the reset signal is detected.

According to the present invention, for the above-mentioned object, the control circuit transmits the first reset signal, and when the start of the reset operation is detected by the reset response signal line, the second reset signal is detected. A device comprising a reset control circuit according to claim 7, characterized in that it comprises means for transmitting a signal.

According to the present invention, for the above-mentioned purpose, the control circuit sets a predetermined time until the transmission of the first reset signal is completed, and the first and second control circuits.
Reset signals are transmitted at the same time, and when the start of the reset operation is detected by the reset response signal line, the transmission of the first reset signal is ended after the elapse of the predetermined time, and the reset operation is performed by the reset response signal line. Means for terminating the transmission of the second reset signal upon detection of the end of the reset control circuit according to claim 8.

According to the present invention, the above-mentioned object is characterized in that the setting means includes means for detecting an abnormality in the power supply voltage, means for detecting a reset request from the outside, and clock means. It is achieved by an apparatus comprising a reset control circuit according to claim 9.

[0026]

In the device provided with the reset control circuit according to claim 1, the first reset signal line sends a first reset signal for initiating a reset operation from the control circuit to the plurality of circuits, and the reset response signal line. Causes the plurality of circuits to separately send reset response signals indicating the start and end of the reset operation to the control circuit, and the second reset signal line causes the second reset signal for continuing the reset operation from the control circuit to the plurality of circuits. Sent. This allows
The start and end of the reset operation of each connected circuit can be transmitted to the control circuit by one signal line by the reset response signal, and when the device includes n circuits, the control circuit and each The number of signal lines connecting to the circuit is n + 2.

In the device including the reset control circuit according to the second aspect, the first and second reset signals are simultaneously transmitted by the control circuit, and the predetermined operation is performed when the start of the reset operation of the plurality of circuits is detected. After the passage of time
Of the second reset signal is completed, and when the completion of the reset operation of the plurality of circuits is detected, the transmission of the second reset signal is completed. As a result, a reliable reset control can be performed, and after the transmission of the second reset signal is completed, a plurality of circuits can return to normal operation at the same time, and a means for synchronizing the timing after reset is unnecessary. Become. Further, since the detection circuit detects the start and end of the reset operation of the plurality of circuits, it becomes possible for the control circuit to monitor the state of each circuit.

In the device including the reset control circuit according to the third aspect, the second reset signal is transmitted when the control circuit transmits the first reset signal and all reset operations of the plurality of circuits are detected. To be done. As a result, reliable reset control can be executed. Further, since the detection circuit detects the start and end of the reset operation of the plurality of circuits, it becomes possible for the control circuit to monitor the state of each circuit.

In the device including the reset control circuit according to the fourth aspect, after the second reset signal is transmitted and a predetermined time has elapsed, the transmission of the first reset signal is ended, and the reset operation of the plurality of circuits is performed. The transmission of the second reset signal is completed when the completion of all the is confirmed. As a result, a reliable reset control can be performed, and after the transmission of the second reset signal is completed, a plurality of circuits can return to normal operation at the same time, and a means for synchronizing the timing after reset is unnecessary. Become.

In the device including the reset control circuit according to the fifth aspect, one end of the reset response signal line is connected to each of the plurality of circuits, and the other end is wired or connected to form a single signal line in the control circuit. Connected. As a result, the number of signal lines connecting the control circuit and the plurality of circuits becomes three regardless of the number of circuits. The control circuit can detect the end of the reset operation of the plurality of circuits by monitoring one signal line.

In the device including the reset control circuit according to the sixth aspect, the first and second reset signals are simultaneously transmitted by the control circuit, and the start of the reset operation is detected by the reset response signal line connected by the wired OR. Then, the transmission of the first reset signal is terminated after a predetermined time has passed, and the second reset signal signal is detected by the wired OR connected reset response signal line when the termination of the reset operation is detected.
The transmission of the reset signal of is ended. This makes it possible to execute reliable reset control by monitoring one signal line, and at the same time, it is possible for a plurality of circuits to return to normal operation at the same time after the transmission of the second reset signal is completed. No means for synchronizing is required.

In a device including a reset control circuit according to a seventh aspect of the present invention, when the reset operation is detected by the reset response signal line which is wired or connected after transmitting the first reset signal by the control circuit, the second operation is performed. Reset signal is transmitted. Thereby, reliable reset control can be executed by monitoring one signal line.

According to another aspect of the present invention, in the device including the reset control circuit, the second reset signal is transmitted, and after the elapse of a predetermined time, the transmission of the first reset signal is completed, and the wired OR connection is reset. The transmission of the second reset signal is ended when the end of the reset operation is detected by the response signal line. This makes it possible to execute reliable reset control by monitoring one signal line, and at the same time, it is possible for a plurality of circuits to return to normal operation at the same time after the transmission of the second reset signal is completed. No means for synchronizing is required.

In the device provided with the reset control circuit according to the ninth aspect, the first means is set based on the abnormality of the power supply voltage by the setting means, the reset request from the outside, and the time measured.
A predetermined time until the end of transmission of the reset signal of is set. As a result, the reset process can be reliably controlled even when an abnormality in the power supply voltage or a reset request from the outside occurs.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of an apparatus having a reset control circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of an apparatus including the reset control circuit of this embodiment. Reset including abnormality detection means 101 for detecting abnormality of power supply voltage, reset request detection means 102 for detecting reset request from the outside, and timing control means 103 for controlling timing of transmission of reset signal and reception of response signal The control circuit 10 includes a first reset signal line 110 and a second reset signal line 110.
A circuit 11 including a timing control means 104 for controlling the timing of receiving a reset signal and transmitting a response signal via the reset signal line 111 and a plurality of reset response signal lines 121 to 12n, and an internal circuit 105,
12 ,. ． ． , 1n, respectively.

The timing control means 104 and the internal circuit 105 described inside the circuit 11 include the other circuits 12 ,. ． ． It is assumed that it also exists inside 1n.

The operation of this embodiment will be described below.

The reset control circuit 10 includes the abnormality detecting means 1
01 or a reset request from the reset request detection means 102, the timing control means 103 causes the circuits 11, 12 ,. ． ． 1n, the first reset signal and the second reset signal are transmitted via the signal lines 110 and 111.

The circuit 11 receives the first reset signal by the timing control means 104 via the signal line 110, and transmits the reset response signal via the signal line 121 when the internal circuit 105 can be reset. Then, the reset control circuit 10 is notified that the circuit can be reset, and the internal circuit 105 is reset.

If the reset of the internal circuit 105 is impossible at the time of receiving the first reset signal, the timing control means 104 instructs the internal circuit 105 to satisfy the condition for enabling the reset. After satisfying the conditions, a reset response signal is transmitted via the signal line 121 to reset the internal circuit 105.

The circuits 11, 12 ,. ． ． Since it is considered that the states of 1n are different in each circuit, it is naturally assumed that the timings at which the reset response signals are transmitted from each circuit also differ. Among the reset response signals transmitted at different timings, the reset response signal that has been transmitted last is recognized by the reset control circuit 10 that all the circuits have received the reset signal, and the predetermined period Only after continuing the transmission of the first reset signal, the transmission of the first reset signal is ended.

The circuits 11, 12 ,. ． ． After confirming the end of transmission of the first reset signal by each timing control means 104, 1n prepares for the end of reset and ends the transmission of each reset response signal.

The reset control circuit 10 detects the end of transmission of the last reset response signal among the reset response signals whose transmission is terminated at different timings, and prepares for reset termination in all the circuits. Then, the transmission of the second reset signal is terminated.

The circuits 11, 12 ,. ． ． 1n detects the end of transmission of the second reset signal, ends the reset operation, and performs normal processing.

FIG. 2 is a diagram showing a timing chart of this embodiment. In FIG. 2, each signal is represented by negative logic. In the present embodiment, as shown in FIG. 2A, the case where the first reset signal and the second reset signal are transmitted at the same time has been described. However, as shown in FIG. Even if the second reset signal is transmitted after receiving, the handshake is possible and the reset operation can be performed similarly.

FIG. 3 shows the reset control circuit 10 of this embodiment.
It is a figure which shows the transition of the state of the apparatus provided with. As shown in FIG. 3, in this embodiment, the normal operation state 31 shifts to the reset start preparation state 32 in response to a request from the abnormality detection means 101 or the reset request means 102, and each circuit 11,
12 ,. ． ． 1n confirms that the internal circuits can be reset, transmits a reset response signal, and shifts to the reset state 33. The reset control circuit 1 indicates that the transmission of the reset response signals of all the connected circuits is completed.
When the timing control circuit 103 of 0 detects, the state shifts to the reset completion preparation state, the timing control circuit 103 terminates the output of the second reset signal, and each circuit returns to the normal operation state 31.

A second embodiment of the device having the reset control circuit of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the arrangement of an apparatus including the reset control circuit of this embodiment. Reset including abnormality detection means 401 for detecting abnormality of power supply voltage, reset request detection means 402 for detecting reset request from the outside, and timing control means 403 for controlling timing of transmission of reset signal and reception of response signal The control circuit 40 controls the timing of receiving the reset signal and transmitting the response signal via the first reset signal line 410, the second reset signal line 411, and the reset response signal line 420.
And internal circuits 405, circuits 41, 42 ,. ． ． ,
4n, respectively.

The timing control means 404 and the internal circuit 405 described inside the circuit 41 are used for the other circuits 42 ,. ． ． 4n is also present in the same manner.

Unlike the first embodiment, the reset response signal line of each circuit is wired-OR connected, and is connected to the reset control circuit 40 by one signal line 420.

The operation of this embodiment will be described below.

The reset control circuit 40 includes the abnormality detecting means 4
01 or a reset request from the reset request detection means 402, the timing control means 403 causes the circuits 41, 42 ,. ． ． 4n, the first reset signal and the second reset signal are transmitted via the signal lines 410 and 411.

The circuit 41 receives the first reset signal by the timing control means 404 via the signal line 410, and when the internal circuit 405 can be reset, transmits the reset response signal via the signal line 420. Then, the reset control circuit 40 is notified that the circuit can be reset, and the internal circuit 405 is reset.

When the reset of the internal circuit 405 is impossible at the time of receiving the first reset signal, the timing control means 404 instructs the internal circuit 405 to satisfy the condition for enabling the reset. After satisfying the conditions, a reset response signal is transmitted via the signal line 420 to reset the internal circuit 405.

The reset response signal line from each circuit is wired-OR connected and connected to the timing control circuit 403 by one signal line 420, so that the reset control circuit 40 uses this signal line 420 for all circuits. After recognizing that the reset signal has been received, the transmission of the first reset signal is continued for a predetermined period, and then the transmission of the first reset signal is ended.

The circuits 41, 42 ,. ． ． After confirming the end of the transmission of the first reset signal by each timing control means 404, 4n prepares for the end of reset and end the transmission of each reset response signal.

The reset control circuit 40 detects that the transmission of all reset response signals has been completed by the signal line 420, recognizes that each circuit is ready to complete the reset, and the second reset Ends signal transmission.

The circuits 41, 42 ,. ． ． 4n detects the end of transmission of the second reset signal, ends the reset operation, and performs normal processing.

FIG. 5 is a diagram showing a timing chart of this embodiment. In FIG. 5, each signal is represented by negative logic. In the present embodiment, as shown in FIG. 5A, the case where the first reset signal and the second reset signal are transmitted at the same time has been described. However, as shown in FIG. Even if the second reset signal is transmitted after receiving, the handshake is possible and the reset operation can be performed similarly.

[0061]

According to the device having the reset control circuit according to the first aspect of the invention, when the device includes n circuits, the number of signal lines connecting the control circuit and each circuit is n + 2. .

According to the device having the reset control circuit of the second aspect, it is possible to execute the reliable reset control, and the means for synchronizing the timing after the reset is not necessary, and the state of each circuit is controlled by the control circuit. Can be monitored.

According to the apparatus including the reset control circuit of the third aspect, it is possible to execute a reliable reset control and to monitor the state of each circuit from the control circuit.

According to the apparatus having the reset control circuit of the fourth aspect, it is possible to perform a reliable reset control and to eliminate the need for a means for synchronizing the timing after reset.

According to the device having the reset control circuit of the fifth aspect, the number of signal lines connecting the control circuit and the plurality of circuits is three regardless of the number of circuits. Further, by monitoring one signal line, it is possible to detect the end of the reset operation of a plurality of circuits.

According to the apparatus having the reset control circuit of the sixth aspect, it is possible to execute reliable reset control by monitoring one signal line, and there is no need for means for synchronizing the timing after reset. Becomes

According to the device having the reset control circuit described in claim 7, reliable reset control can be executed by monitoring one signal line.

According to the apparatus including the reset control circuit of the eighth aspect, it is possible to execute reliable reset control by monitoring one signal line, and there is no need for means for synchronizing the timing after reset.

According to the device including the reset control circuit of the ninth aspect, the reset process can be surely controlled even when the power supply voltage is abnormal or a reset request is generated from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of an apparatus including a reset control circuit according to the present invention.

FIG. 2 is a timing chart of each signal in FIG.

FIG. 3 is a state transition diagram of the apparatus of FIG.

FIG. 4 is a block diagram of a second embodiment of an apparatus including a reset control circuit according to the present invention.

5 is a timing chart of each signal in FIG.

FIG. 6 is a block diagram of an apparatus including a conventional reset control circuit.

[Explanation of symbols]

 10 reset control circuit 11, 12 ,. ． ． 1n circuit 101 voltage abnormality detection means 102 external reset request detection means 103, 104 timing control means 105 internal circuit 110 first reset signal 111 second reset signal 121, 122 ,. ． ． , 12n Reset response signal

Claims (9)

[Claims] 1. A device comprising a plurality of circuits and a reset control circuit for controlling a reset operation of the plurality of circuits,
The plurality of circuits and the control circuit include a first reset signal line for transmitting a first reset signal for starting a reset operation from the control circuit to the plurality of circuits, and a plurality of circuits from each of the plurality of circuits. A reset response signal line for individually transmitting a reset response signal indicating the start and end of the reset operation to the control circuit, and a second reset signal for continuing the reset operation from the control circuit to the plurality of circuits. And a second reset signal line for connecting the reset control circuit. 2. The control circuit individually detects a start and an end of a reset operation of the plurality of circuits by the reset response signal, and a predetermined means for ending the transmission of the first reset signal. Setting means for setting a time and the first reset signal after the lapse of the predetermined time when all of the first and second reset signals are transmitted at the same time to detect the start of the reset operation of the plurality of circuits Reset control circuit according to claim 1, further comprising: means for ending the transmission of the second reset signal when all the reset operations of the plurality of circuits are detected. A device comprising. 3. The control circuit detects the start and end of the reset operation of the plurality of circuits individually by the reset response signal, and the control circuit transmits the first reset signal to detect the plurality of circuits. An apparatus including the reset control circuit according to claim 1, further comprising: a unit that transmits the second reset signal when the start of the reset operation is completely detected. 4. The control circuit sets a predetermined time until the transmission of the first reset signal is completed, and the control circuit transmits the second reset signal, and after the predetermined time elapses. Ending the transmission of the first reset signal,
The device having a reset control circuit according to claim 3, further comprising means for ending the transmission of the second reset signal when all the reset operations of the plurality of circuits are detected. 5. The reset response signal line has one end connected to each of the plurality of circuits, and the other end connected by wired OR to be connected to the control circuit as one signal line. An apparatus comprising the reset control circuit according to claim 1. 6. The reset circuit, wherein the control circuit simultaneously transmits the setting means for setting a predetermined time until the transmission of the first reset signal is finished and the first and second reset signals. When the start of the reset operation is detected by the signal line, the transmission of the first reset signal is ended after the lapse of the predetermined time, and when the end of the reset operation is detected by the reset response signal line, the second reset signal is detected. 6. A device comprising a reset control circuit according to claim 5, comprising means for ending the transmission of a reset signal. 7. The control circuit comprises means for transmitting the first reset signal and transmitting the second reset signal when the start of a reset operation is detected by the reset response signal line. An apparatus comprising the reset control circuit of claim 5. 8. The control circuit sets a predetermined time until the transmission of the first reset signal is finished, and transmits the second reset signal after a lapse of the predetermined time. Ending the transmission of the first reset signal,
8. The device including the reset control circuit according to claim 7, further comprising: a unit that terminates the transmission of the second reset signal when the termination of the reset operation is detected by the reset response signal line. 9. The setting means comprises means for detecting an abnormality in the power supply voltage, means for detecting a reset request from the outside, and time measuring means.
An apparatus comprising the reset control circuit according to any one of 4, 6, and 8.