JPH01126046A - Data transmission and reception system - Google Patents

Abstract

PURPOSE:To expand the function of a reception unit by leading the phase of reception when the timing of the reception unit and that of the transmission unit using a microprocessor, a hardware and a monitor program in common are overlapped. CONSTITUTION:The microprocessor 4 the relevant hardware and monitor program are used in common for the reception and transmission units. A reception control counter section 1 commands which phase of the specified transmission reception procedure is to be processed, the result is given to a reception timing discrimination section 2 thereby discriminating whether a correct control signal DC/CLK is obtained at the designated phase. A shift control section 3 receives the result of discrimination from the reception timing discrimination section 2 and checks again the DC/CLK after a prescribed time elapses and the reception procedure is advanced forcibly when the state is not equal to the discrimination just before. Thus, a monitor program with wide application is adopted for the reception unit to expand the function of the reception unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission/reception system in a device that connects a plurality of separate units to configure one system for transmitting and receiving data.

[Summary of the invention]

When data transmitted using a specified periodic transmission timing and handshake procedure is received by a receiving unit configured with the same microprocessor, hardware, and program (hereinafter referred to as a monitor program) with the same structure as the transmitting unit, If the timings of the transmitting side and the receiving side overlap, there is a possibility that normal reception may not be possible.

Therefore, the receiving unit detects the timing overlap with the transmitting unit twice before and after a predetermined unit time (predetermined fixed time), and if the 9 judgment results are the same, the normal procedure is used, and if there is a change, the handshake procedure is performed once. Control is performed so as to proceed forward, and thereafter control is performed such that reception is performed at timings shifted by a predetermined unit time value.

As a result, the microprocessor, hardware, and monitor program of both the transmitting and receiving units can be shared, reducing development costs, and by employing the monitor program, it is possible to increase the expandability of the functions of the receiving unit.

[Conventional technology]

FIG. 3 shows a conventional example. The signal that connects the transmitting side unit and the receiving unit is the direction control signal (hereinafter referred to as D
C)/clock signal (hereinafter abbreviated as CLK) 2.1
and a data signal (hereinafter abbreviated as DATA) 5.2 in parallel. From the transmitting unit, the transmission timing shown in Figure 2, D
It is transmitted using the timing and procedure shown by C, CLK, and DATA.

Address, data, idle data DATA and CL
K is counter 8, 6.4 corresponding to counter value 9 to 0.
will be sent at the timing of During standby, the reception control counter section l receives an initial signal 5 from the microprocessor 5.
When the reception operation starts, the update signals 5 and 4 are applied from the microprocessor 5 to the reception control counter unit 1, and the reception timing is determined by the counter 7.5.3 to determine the data input timing. Give to part 2.

In order to detect DC=High indicating the start of transmission, the microprocessor 5 sends DC:=High, CLK=
High DC/CLK signals 5.5 are applied to the reception timing determination section 2 and compared with DC/CLK input signals 2.1. When both signals 5.5 and 2.10 match at a predetermined timing specified by the reception control section counter, the DATA input activation signal 2.2 is added to the microprocessor 5, and the interrupt signal 5 is generated which is sufficiently faster than the transmission timing. When starting signal 2.2 is detected corresponding to the bow, DATA5.2
Enter. After detecting the start of transmission, input the address at the falling edge of CLK at the counter = 7 position according to signals 1 and 1 of the reception control counter section 1, input data at the rising edge of CLK at the counter = 5 position, and input the data at the rising edge of CLK at the counter = 3 position. The procedure for inputting idle data at the falling edge of CLK at the position is similar to the detection of the start of transmission, and the interrupt signal 5 is sufficiently fast in response to the change in CLK.
・Do this in response to 1.

[Problem that the invention seeks to solve]

In the prior art described above, the data p'v from the transmitting unit
It is necessary to perform reception detection processing at a timing sufficiently earlier than the transmission timing so as not to miss the transmission timing, and the program of the microprocessor 5 becomes a program for each receiving unit. This is not a problem in the form of a device in which the receiving unit is subordinate to the transmitting unit, but it has a drawback that it cannot be used in applications where the functions of the receiving unit are expanded. SUMMARY OF THE INVENTION In order to solve this problem, it is an object of the present invention to share a microprocessor, hardware, and monitor program with the transmitting unit, thereby reducing development costs and ensuring extensibility of the receiving unit's functions.

[Means for solving problems]

In order to achieve the above object, the present invention uses signals of the same nature for transmission timing and reception timing, as shown in FIG. In order to deal with reception failures that occur when the reception timing overlaps with the transmission timing, it is assumed that the transmission timing and transmission procedure occur at the exact period specified by the interrupt, and the DC/CLK signal is set at the timing of counter = 7. Compare the state of DC/CLK with the state of DC/CLK checked again after a predetermined unit time, and find a match.

Due to the discrepancy, it is determined whether the reception timing is normal or D should be corrected, and if it is necessary to correct it, the operation for managing counters 9 to O is forcibly advanced by one and subsequent operations are made normal by shifting the timing by the unit time. This allows for easy reception.

[Effect]

To explain the operation of the present invention using FIGS. 1 and 2, the timing movement control section 3 detects a counter 8 whose reception timing of the reception unit is delayed by one clock with respect to the rise of DC corresponding to the transmission timing of the transmission unit. By monitoring the status of DC/CLK twice before and after a predetermined unit time, we detect cases close to Can complete the action.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. 1 is a reception control counter section which indicates which phase of the specified transmission and reception procedure should be processed. Reference numeral 2 denotes a reception timing determination unit which determines whether or not the correct control signal DC/CLK is obtained at the phase designated by the reception control counter unit 1. 3 is a timing movement control unit which, after receiving the judgment result from the reception timing judgment unit 20, checks the state of DC/CLK again after a predetermined unit time has elapsed, and if it matches the previous judgment result, the reception timing is changed. It is judged as correct and normal processing continues.

If it does not match the previous determination result, it is determined that the reception timing has a small margin, and the reception procedure is forcibly advanced by one step, and from then on, reception processing is performed at a timing that is shifted by the unit time from its own reception timing. 4
is a microprocessor, which determines the accurate reception timing obtained by multiplying the interrupt signal by an integer in response to the interrupt signal obtained from the outside, and also controls the timing movement control unit 3.
．． Upon receiving the activation signal from the controller, it inputs address, data, and idle data and performs reception processing. This operation will be explained below. The reception control counter section 1 is set to 0 by the initialization signal 4.3 and enters a standby state. The microprocessor 4 supplies determination signals 4 and 5 such that DC=High/CLK=High to the reception timing determination section 2 in order to detect the start of transmission from the transmission unit. The reception timing of the receiving unit is the same as the transmission timing as shown in FIG. This is based on this method in which the microprocessor hardware and monitor program of the transmitting and receiving units are the same, and the reception timing signals 4 are sent from the microprocessor 4 via the reception control counter section 1 to the reception timing judgment section. 2, each signal is detected in the procedure shown in FIG. Since the transmission and reception timings are the same, the reception unit, which is delayed by about one clock, detects the DC=High data that the transmission unit outputs at the counter 9 position at a timing close to the counter 8, resulting in a reception failure. there is a possibility. The reception timing determination unit 2 determines the next reception timing, that is, the counter 7VC near I' 4 Mi7 f TeDC=H
After determining that high/CLK=High, after a predetermined time has elapsed using the timer of the timing movement control unit 3, the DC/CLK is determined again using restart signals 2 and 3, and reception is activated only if they do not match. The microprocessor generates the signal 3.2 and receives 1 address data from the data line 4.2. Also, the timing shift control section 3 outputs a forced count-up signal 3.1 to the reception control counter section. At each subsequent reception timing, data at a phase corresponding to counter=5 in FIG. 2 and idle data at a phase corresponding to counter=3 in FIG. 2 are similarly received at timings shifted by the unit time of the timing movement control section 3. As a result, one procedure of data reception during DC=H+gh is completed.

〔Effect of the invention〕

According to the present invention, it is possible to realize data transmission and reception control using transmission and reception timing signals of the same nature by sharing the microprocessor hardware and monitor program for each transmission and reception unit. Since costs can be reduced and a monitor program with a wide range of applications can be adopted in the receiving unit, the functionality of the receiving unit can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart showing a data transmission/reception procedure in the present invention, and FIG. 3 is a block diagram showing an example of the conventional method. 1: Reception control counter unit, 2: Reception timing determination unit,
3: timing movement control section, 4: microprocessor.

Claims (1)

[Claims] 1. A reception control counter section that specifies the data reception procedure to connect both the transmission and reception units with multiple control signals and parallel data signals to transmit and receive data according to a specified procedure, and verifies the timing of reception from the control signal. Update processing of the reception timing judgment section, timing movement control section that controls movement of reception timing by unit time, and reception control counter section, setting of judgment data to the reception timing judgment section, and data reception according to the activation signal of the timing movement control section. After the first control signal is determined by the reception timing determination section at a predetermined phase specified by the reception control counter section, the second control signal is determined after the unit time of the timing movement control section has elapsed. If the two judgments match, a start signal is given to the microprocessor at the normal timing, and if they do not match, the reception control counter section advances one reception procedure, and the subsequent movement control unit executes the reception operation at the unit time. A data transmission/reception method characterized by a shift operation.