JP2007072662A - Bus failure detection system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus failure detection system for quickly selecting components to be exchanged by detecting the failure of the data transmission path of a common bus, and pointing a defective site. <P>SOLUTION: In a bus failure detection system, a sampling circuit 6 for collecting the status of a bus is added to the connection points of an initiator 11, a cable 2, a back plane 31 and input/output devices 4 and 5 configuring the transmission path of a common bus, and the sampled data are collected and compared by a bus failure detection circuit 7 so that it is possible to detect the failure of the common bus, and to point a defective site from the location of the sampling circuit 6 determined to be defective. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bus failure detection system for detecting a failure in a data transmission path and specifying a part in an information processing system that performs data transfer using a common bus, and is particularly applicable to failure detection of a common bus. And effective technology.

  As a conventional common bus failure detection method, for example, there is a method of detecting a failure on the transmission side in a device connected to the common bus as disclosed in Patent Document 1.

  That is, in this method, the data output to the buffer of the device and the data output from the buffer can be input to the comparison unit, and the data is compared within the period when the buffer is controlled to the output side. Verify whether data is correctly output to the common bus.

  In addition, when a failure occurs in the common bus as disclosed in Patent Document 2, there is a method in which a device having the right to use the bus at that time points out as a failure part.

In other words, when using a common bus, this method is used when each device connected to the bus has the right to use the bus as a result of arbitration and performs data transfer. Determines that the device having the right to use the bus is the faulty part.
JP 9-46360 A JP 2000-222293 A

  In general, a system using a common bus includes an initiator having a bus arbitration circuit, a bus transmission path, and an input / output device connected to the bus.

  In addition, the bus transmission path is configured by inserting a plurality of disk devices into the backplane structure of an initiator device, a cable for connecting an input / output device, and a disk device, and is composed of a plurality of components. .

  When a failure occurs in the transmission path, the failure detection method disclosed in Patent Document 1 can detect a failure with a transmission-side device connected to the common bus.

  However, it cannot be pointed out in which part of the data transmission path the failure occurred.

  Further, in the failure detection method disclosed in Patent Document 2, since a device having the right to use the bus is pointed out as a failure portion when a common bus failure occurs, the failure portion of the data transmission path is pointed out. Can not.

  For this reason, when a failure occurs in a transmission path of a common bus that spans a plurality of components and devices, the conventional technology cannot detect the failure site even if the failure can be detected. For this reason, it is impossible to identify the parts to be replaced, and it is necessary to perform a wide range of parts replacement for system recovery, which increases the number of parts and the recovery time.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a bus failure detection system capable of quickly selecting a replacement part by detecting a failure related to a transmission path of a common bus and pointing out the failure portion.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A bus failure detection system according to the present invention includes a plurality of sampling circuits that sample a state of a common bus added to a connection point of components constituting a common bus of an information processing system, a sampling start instruction to the plurality of sampling circuits, and It has a bus failure detection circuit that collects and compares data sampled by multiple sampling circuits. The bus failure detection circuit detects a bus failure based on the data comparison result, and the failure is detected from the position of the sampling circuit that detected the failure. This is to identify the part.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, by comparing the state of the bus collected by the sampling circuit added to each point of the transmission path of the common bus, the failure of the transmission path is detected, and from the location of the sampling circuit determined to be a failure, It is possible to identify where the failure has occurred.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<Configuration of bus failure detection system>
The configuration of the bus failure detection system according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of an information processing system including a bus failure detection system according to an embodiment of the present invention, and FIG. 2 shows a configuration of a sampling circuit of the bus failure detection system according to an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the bus fault detection circuit of the bus fault detection system according to one embodiment of the present invention.

  The transmission path of the common bus is composed of various parts such as the cable 2, the device, and the backplane 31. In this embodiment, the purpose of detecting a failure in the bus transmission path and pointing out the location of the failure is realized without changing the specifications of the common bus.

  The information processing system shown in FIG. 1 includes a host 1, an expansion device 3, and input / output devices 4 and 5.

  The host 1 and the expansion device 3 are connected by a cable 2, and the input / output devices 4 and 5 are connected in a form of being inserted into a connector of the back plane 31 of the expansion device 3.

  In the system of FIG. 1, the common bus is a transmission path from the initiator 11 to the cable 2 in the host 1, a transmission path of the cable 2, a transmission path of the backplane 31, and a transmission path between the backplane 31 and the input / output devices 4 and 5. Formed from.

  In this way, in addition to the general configuration of the information processing system, the sampling circuit 6 is added to the transmission path of the common bus in this embodiment.

  In the example shown in FIG. 1, the sampling circuit 6 (1) is connected to the transmission path from the initiator 11 to the cable 2 in the host 1, the sampling circuit 6 (2) is connected to the transmission path at the connection point between the cable 2 and the backplane 31, and the backplane. The sampling circuit 6 (3) is added to the transmission path at the connection point between the I / O device 4 and the input / output device 4, and the sampling circuit 6 (4) is added to the transmission path at the connection point between the backplane 31 and the I / O device 5.

  In addition, a bus failure detection circuit 7 that controls the sampling circuit 6 (1), the sampling circuit 6 (2), the sampling circuit 6 (3), and the sampling circuit 6 (4) is added in the host 1.

  Sampling circuit 6 (1), sampling circuit 6 (2), sampling circuit 6 (3), sampling circuit 6 (4), and bus fault detection circuit 7 constitute a bus fault detection system.

  Sampling circuit 6 (1), sampling circuit 6 (2), sampling circuit 6 (3), and sampling circuit 6 (4) all have the same structure, and as shown in FIG. 2, controller 61, latch group 62, trigger generation The circuit 63 is configured.

  The controller 61 is connected to the bus failure detection circuit 7 through a dedicated interface 64, and processes setting of the operation mode of the sampling circuit 6, transfer of sampling data, and the like.

  Since the controller 61 and the bus failure detection circuit 7 are connected on a one-to-one basis, they are connected with an interface having a small number of signal lines such as a serial interface.

  In addition, since it is an additional circuit for detecting a failure, it is best to operate at a low speed and perform transfer with a sufficient margin.

  In the present embodiment, since the bus failure is not detected in real time, the transfer between the controller 6 and the bus failure detection circuit 7 may be performed at a low speed.

  The latch group 62 is connected to the common bus, and records the state of the common bus with a trigger signal from the trigger generation circuit 63. The recorded state of the common bus is sent to the bus failure detection circuit 7 via the controller 61.

  The trigger generation circuit 63 has a trigger delay time and trigger condition setting function, and is set from the bus failure detection circuit 7 via the controller 61.

  A trigger enable signal 65 from the bus failure detection circuit 7 is connected to the trigger generation circuit 63. The trigger generation circuit 63 sends a trigger signal to the latch group 62 when the trigger condition is satisfied after the set trigger delay time has elapsed after receiving the trigger enable signal 65.

  The dedicated interface 64 between the bus failure detection circuit 7 and the sampling circuit 6 and the trigger enable signal 65 need to have the same length.

  The bus failure detection circuit 7 includes a controller 71 and a comparison unit 72 as shown in FIG.

  The controller 71 and the comparison unit 72 are connected to the sampling circuit 6 through a dedicated interface.

  A trigger enable signal 65 is output from the controller 71, and is commonly connected to the sampling circuit 6 (1), the sampling circuit 6 (2), the sampling circuit 6 (3), and the sampling circuit 6 (4).

  The controller 71 has an interface with the host 1, and performs setting of the operation mode of the sampling circuit 6, transmission of information when a failure is detected, and the like.

  The comparison unit 72 has a function of receiving and comparing sampling data of the common bus of the sampling circuit 6. The comparison result is transmitted to the controller 71, and information is transmitted from the controller 71 to the host 1 when a failure is detected.

<Operation of bus failure detection system>
Next, the operation of the bus failure detection system according to the embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram illustrating the operation of the bus failure detection system according to the embodiment of the present invention, and FIG. 5 illustrates the trigger signal loop back mode of the sampling circuit of the bus failure detection system according to the embodiment of the present invention. FIG. 6 is a diagram showing an example of a result obtained by the bus failure detection circuit of the bus failure detection system according to the embodiment of the present invention.

  In FIG. 4, the processing between the sampling circuit 6 and the bus failure detection circuit 7 is shown with the time axis in the vertical direction.

  In order for the bus failure detection system to start detecting a failure in the common bus, the bus failure detection circuit 7 instructs the sampling circuit 6 in a loopback mode in which the trigger enable signal is looped back (step S100). The sampling circuit 6 sets the operation mode to a loopback mode for looping back the trigger enable signal as shown in FIG.

  In the loopback mode in which the trigger enable signal is looped back, the trigger enable signal 65 output from the bus failure detection circuit 7 is input to the sampling circuit 6 and input to the trigger generation circuit 63.

  The trigger generation circuit 63 transmits the trigger enable signal 65 directly to the controller 61, and the controller 61 also transmits the trigger enable signal 65 directly to the bus failure detection circuit 7.

  The bus failure detection circuit 7 turns on the trigger enable signal 65 (step S101), measures the delay time (arrival time) of the trigger enable signal that loops back from the sampling circuit 6, and determines the measured delay time of the trigger enable signal. First, a trigger delay time is set in the sampling circuit 6 (step S102).

  The sampling circuit that has the maximum delay time of the trigger enable signal sets the trigger delay time to zero.

  The other sampling circuits adjust each of the trigger enable signals so that the sum of the delay time of the trigger enable signal and the set trigger delay time becomes 1/2 of the maximum delay time of the trigger enable signal (step). S103).

  The delay time of the trigger enable signal is halved because the measurement time is the round trip time of the trigger enable signal.

When the setting of the trigger delay time is completed, the bus failure detection circuit 7 instructs the sampling circuit 6 to cancel the trigger enable signal loopback mode.
The bus failure detection circuit 7 sets a trigger condition in accordance with the bus specification in the sampling circuit 6 (step S104).

  Here, as an example, SEL # assertion and BSY # negate when the bus use right of the SCSI bus is established are set (step S105).

  When the setting of the trigger condition is completed, the bus failure detection circuit 7 turns on the trigger enable signal (step S106).

  When the trigger enable signal is turned on, all the sampling circuits 6 are simultaneously in a waiting state for the trigger according to the setting of the trigger delay time.

  When the set trigger condition is satisfied, the common bus is sampled (step S107).

  When the sampling of the common bus is completed, the sampling circuit 6 reports the sampling completion to the bus failure detection circuit 7 (step S108).

  The bus failure detection circuit 7 waits for a predetermined time for completion reports from all the sampling circuits 6 after receiving the completion report of the first sampling circuit.

  The completion report waiting time is a value that covers the transmission time for the length of the signal path of the common bus.

  In the sampling circuit 6 in which the completion report is not performed for a predetermined time, it is determined as a point where a failure has occurred (step S109).

  The bus failure detection circuit 7 instructs the sampling circuit 6 to transmit sampling data (S110).

  The sampling circuit 6 sends the sampling data of the common bus recorded in the latch group 62 to the bus failure detection circuit 7 via the controller 61 and the dedicated interface 64.

  The bus failure detection circuit 7 records the received sampling data in the comparison unit 72.

  When the sampling data is received from all the sampling circuits 6, the comparison unit 72 collates the data.

  In the present embodiment, data verification is performed based on the data of the sampling circuit 6 (1). For example, when there is no sampling completion report from the sampling circuit 6 (1), collation is performed based on the data of the sampling circuit 6 (2).

  As a result of comparison with the reference data, a match / mismatch is determined and recorded (step S112).

  FIG. 6 shows an example of a result obtained by the operation (step S100 to step S112) described in FIG. 4 in the configuration shown in FIG.

  Case (T10) is a case where the data of the sampling circuit 6 (2), the sampling circuit 6 (3), and the sampling circuit 6 (4) do not match the data of the sampling circuit 6 (1).

  In the case (T10), all the transmission paths after the sampling circuit 6 (1) are inconsistent, so that it can be determined that a failure has occurred in the cable 2.

  Case (T11) is a case where the sampling circuit 6 (2) matches the data of the sampling circuit 6 (1), and the data of the sampling circuit 6 (3) and the sampling circuit 6 (4) do not match. .

  In the case (T11), the signal is correctly transmitted up to the sampling circuit 6 (2), but the signal is not correctly transmitted to the sampling circuit 6 (3) and the sampling circuit 6 (4). It can be determined that a failure has occurred in the backplane 31.

  Case (T12) is a case where the sampling circuit 6 (2) and the sampling circuit 6 (3) match the data of the sampling circuit 6 (1) and the data of the sampling circuit 6 (4) does not match the data of the sampling circuit 6 (1). .

  In the case (T12), the signal is correctly transmitted to the sampling circuit 6 (1), the sampling circuit 6 (2), and the sampling circuit 6 (3), but the signal is correctly transmitted to the sampling circuit 6 (4). Therefore, it can be determined that a failure has occurred in the interface unit of the input / output device 5.

  In the case (T13), there is no sampling completion report from the sampling circuit 6 (1), and the data of the sampling circuit 6 (3) and the sampling circuit 6 (4) match the data of the sampling circuit 6 (2). This is the case.

  In this case, since the sampling circuit 6 (1) is not responding, the reference for comparison of the sampling data is based on the data of the sampling circuit 6 (2).

  In the case (T13), the trigger condition is established when the input / output device 4 or the input / output device 5 acquires the right to use the common bus, and the sampling circuit 6 (2), the sampling circuit 6 (3), and the sampling circuit are satisfied. Sampling is performed at 6 (4), but the trigger condition is not satisfied in the sampling circuit 6 (1).

  Since the signal is not correctly transmitted between the sampling circuit 6 (2) and the sampling circuit 6 (3), it can be determined that a failure has occurred in the cable 2.

  Case (T14) is a case where there is no sampling completion report from the sampling circuit 6 (2), the sampling circuit 6 (3), and the sampling circuit 6 (4), and only the sampling circuit 6 (1) is sampled.

  In this case, since only the data of the sampling circuit 6 (1) is present, the sampling data is not compared.

  In the case (T14), since the signal is not correctly transmitted after the sampling circuit 6 (2), the trigger condition is not satisfied, so that it can be determined that a failure has occurred in the cable 2.

  As described above, the state of the common bus is simultaneously recorded by the sampling circuit, and by comparing the respective sampling data, it is possible to detect a failure in the transmission path of the common bus and specify the failure occurrence site. Further, it becomes possible to point out the failure point in detail, and it is possible to shorten the time for system restoration by replacing parts.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a bus failure detection system for detecting a failure in a data transmission path and specifying a part in an information processing system that performs data transfer using a common bus, and in particular, a system for detecting a failure in a common bus. It is applicable to.

It is a block diagram which shows the structure of the information processing system containing the bus failure detection system which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the sampling circuit of the bus failure detection system which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the bus failure detection circuit of the bus failure detection system which concerns on one embodiment of this invention. It is a figure which shows operation | movement of the bus failure detection system which concerns on one embodiment of this invention. It is explanatory drawing for demonstrating the loopback mode of the trigger signal of the sampling circuit of the bus failure detection system which concerns on one embodiment of this invention. It is the figure which showed an example of the result by the bus failure detection circuit of the bus failure detection system which concerns on one embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Host, 2 ... Cable, 3 ... Expansion device, 4, 5 ... Input / output device, 6 ... Sampling circuit, 7 ... Bus failure detection circuit, 61 ... Controller, 62 ... Latch group, 63 ... Trigger generation circuit, 64 ... Dedicated interface, 65... Trigger enable signal, 71... Controller, 72.

Claims (3)

A plurality of sampling circuits for sampling a state of the common bus added to a connection point of components constituting the common bus of the information processing system;
An instruction to start sampling to the plurality of sampling circuits, and a bus failure detection circuit for collecting and comparing data sampled by the plurality of sampling circuits,
The bus fault detection circuit detects a bus fault based on the comparison result of the data, and specifies a faulty part from the position of the sampling circuit where the fault is detected. The bus failure detection system according to claim 1,
A signal is output from the bus failure detection circuit to the plurality of sampling circuits, the plurality of sampling circuits are operated in a loopback mode, a transmission time of the signal is measured, and a delay time corresponding to the measured transmission time is set as the delay time. Set for each of multiple sampling circuits,
A bus failure detection system, wherein sampling operations of the plurality of sampling circuits are started simultaneously in response to a common sampling start instruction from the bus failure detection circuit. The bus failure detection system according to claim 1,
In the operation of sampling the state of the common bus by the bus failure detection circuit, the sampling circuit is instructed to start sampling, but if the sampling trigger condition is not satisfied, it is also determined as a failure of the common bus. Bus failure detection system characterized by that.

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