JPH08248099A - Lsi internal state recognition circuit - Google Patents

Abstract

PURPOSE: To provide an LSI internal state recognition circuit having a mode switching terminal and small number of LSI terminals. CONSTITUTION: A periodic pulse generator 20, a shift register 10 are provided in an LSI, LSI internal states 101, 102, 103, 104 are aligned in time series to output. A mode switching terminal 30 for H-fixed inputting to a shift register 10 is separately provided. Both are switched to recognizing the LSI internal state without providing a test special purpose output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device using an LSI inside a device, and to a circuit for monitoring the internal state of the LSI.

[0002]

2. Description of the Related Art In recent LSIs, the number of pins for external output is generally small while the function is improved and the size is reduced. A method of reducing the number of output pins to the outside of the LSI by degenerating inside has been taken. Also, in the LSI internal state monitoring, as shown in Japanese Patent Laid-Open No. 63-16275, a specialized L
A method has been proposed in which an SI external output pin is newly prepared, and the LSI internal state is arranged in a time series and output to check the LSI internal state.

Further, as shown in JP-A-61-73075,
An address is assigned to the internal state of the LSI, a terminal for designating the address is provided, and each LS is designated by designating the address.
A method of outputting the I internal state to the outside has also been proposed.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the circuit system described in No. 16275, it is necessary to prepare a dedicated external output terminal, and it is necessary to prepare at least one LSI external output terminal.

Further, the circuit system described in Japanese Patent Laid-Open No. 61-73075 requires a scan address terminal for designating an address, which is assigned to the internal state of the LSI together with an external output terminal. Even when the addresses are arranged side by side in a time series, one scan address terminal and an input terminal for a signal designating the head of address data are required.

[0006]

According to the present invention, an LSI
A buffer for inputting an internal state and outputting it to the outside of the LSI, a shift register for outputting an input from the pulse generator as an enable signal for the buffer, and a pulse generator for inputting a clock signal and outputting a pulse signal to the shift register. , And a mode switching means for switching the input of the shift register.

Further, according to the present invention, the pulse generating section is configured by combining a counter and a logic circuit for periodically inputting an output control signal to the shift register. An internal state confirmation circuit can be obtained.

Further, according to the present invention, there is obtained an LSI internal state confirmation circuit characterized in that the mode switching means is a mode switching terminal for giving an instruction to switch the input mode of the shift register.

That is, in the circuit configuration of the present invention, attention is paid to the fact that the LSI internal state observation point is generally used for detecting an internal abnormality of the LSI.
The output terminal to the outside is a commonly used terminal indicating an LSI abnormality, and is provided with a mode switching function, which is characterized in that the normal operation state and the test state are switched and used.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An LSI internal state confirmation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an LSI internal state display circuit of the present invention, and FIG. 2 is a time chart when (A) is a normal mode and (B) is a test mode. Is.

The LSI internal state confirmation circuit according to this embodiment is provided with the output buffers 1, 2, 3, 4 for inputting the internal state of the LSI and outputting it to the outside of the LSI, the shift register 10, and the shift register to which the clock signal 301 is input. A pulse generator 20 for outputting a pulse signal to 10 and a mode switching terminal 30 for giving an instruction to switch the input mode of the shift register 10 are provided. The pulse generator 20 is configured by combining a counter 20A and a logic circuit 20B in order to periodically input an output control signal to the shift register 10.

In the LSI internal state confirmation circuit of this embodiment,
As a normal mode selection instruction, when the mode switching terminal 30 is set to H, the input to the shift register 10 is always H, so that the output buffers 1, 2, 3, 4 are all in the enable state, and the change in the LSI internal state is changed. It will be output as is. In the configuration example of FIG. 1, since all the internal states of the LSI are output in a wired-OR state,
It becomes like the time chart of (A). That is, since the LSI internal states 101 to 104 are states that are wired-ORed and output to the LSI external output terminal 201, they are terminals generally used as LSI failure detection terminals and the like.

As a test mode selection instruction, when the mode switching terminal 30 is set to L, the pulse generator 20 uses the clock signal 301 to generate H pulses of an arbitrary cycle (the number of stages of the shift register 10). , The shift register 10 which receives it sequentially outputs the output buffers 1, 2,
Enable 3 and 4. Therefore, the LSI internal states 101 to 104 are sequentially output in time series to the LSI external output terminal 201, as shown in the time chart of FIG. Here, the output of the pulse generator 20 is synchronized with the synchronous output 40.
By referring to item 1 in FIG. 1, it is possible to monitor and confirm the internal state of the LSI.

When data is transmitted and received to and from the LSI by a synchronization method using frame pulses, the LSI transmits data without using a dedicated pulse generator or a dedicated synchronization output terminal. It is possible to use the frame pulse terminal for transmitting and receiving.

[0016]

As described above, according to the present invention, the internal state of the LSI is sequentially output, and the LSI terminals which are normally used in practice are switched between the normal mode and the test mode to be used. It is possible to confirm the functions of many LSI internal states at the output terminal. Depending on the application of the LSI, other terminals constituting the present invention can be easily replaced with terminals for practical use, and there is also an effect that the dedicated test terminals can be easily reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an LSI internal state confirmation circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation of the LSI internal state confirmation circuit shown in FIG. 1, (A) is a waveform diagram showing an operation in each part in a normal mode, and (B) is a test mode. FIG. 6 is a waveform chart showing the operation in each part of FIG.

[Explanation of symbols]

 1 Output Buffer 2 Output Buffer 3 Output Buffer 4 Output Buffer 10 Shift Register 20 Pulse Generator 20A Counter 20B Logic Circuit 30 Mode Switching Terminal 101 LSI Internal State 102 LSI Internal State 103 LSI Internal State 104 LSI Internal State 201 LSI External Output Terminal 301 Clock signal 401 Synchronous output

Claims (3)

[Claims] 1. A buffer for inputting an internal state of an LSI and outputting it to the outside of the LSI, a shift register for outputting an input from a pulse generator as an enable signal for the buffer, and a clock signal for inputting a pulse signal to the shift register. An LSI internal state confirmation circuit comprising: a pulse generator for outputting and a mode switching means for switching the input of the shift register. 2. The LSI internal state confirmation circuit according to claim 1, wherein the pulse generation unit is configured by combining a counter and a logic circuit so as to periodically input an output control signal to the shift register. LSI characterized by
Internal status check circuit. 3. The LSI internal state confirmation circuit according to claim 1, wherein the mode switching means is a mode switching terminal for giving an instruction to switch the input mode of the shift register. circuit.