JPH08242413A - Multi-screen television receiver - Google Patents

Abstract

PURPOSE: To improve the quality of an image on plural slave screens and to make a memory for slave screen processing to be inexpensive and advantageous in a manufacturing. CONSTITUTION: A master screen video signal is decoded by a master screen decoder 7, compressed in horizontal and vertical directions by a compression circuit 10 and the compressed signal is fed to a switch 17, where plural channels are selected, then the plural slave screens obtained by the selection are decoded by a slave screen decoder 11 and compressed by a compression circuit 12 and the compressed signal is stored in a FIFO 13. A slave screen video signal read out of the FIFO 13 is fed to the switch 17. The switch 17 sets a master screen output period and a slave screen output period and a selected signal is fed to a display device 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen television receiver for displaying broadcasts of a plurality of channels on a single television receiver so that they can be simultaneously viewed.

[0002]

2. Description of the Related Art In recent years, television receivers have become capable of simultaneously displaying a plurality of channels of video on a single television receiver due to advances in digital technology. In a conventional television receiver, as shown in the example of the display screen in FIG. 14A, the parent screen is halved horizontally.
And a random access memory (RAM) is used as a child screen memory in the remaining portion of the plurality of received television signals or external video signals, for example, 9 bytes.
It has been proposed to display individual child screens (A to I) and use the same as a channel search screen or the like.

FIG. 13 is a diagram showing a block configuration of a television receiver having such a multi-screen display function.
Here, it is assumed that a video signal having a reference synchronization signal when displaying an image on the display device is a parent screen image, and the parent screen is on the left side of the display screen. Further, the channel search screen is output in synchronization with the sync signal of the parent screen, and is therefore a child screen.

For example, a satellite broadcast signal is induced in the antenna 1. Further, a high-frequency video signal of, for example, UHF or VHF broadcasting is induced in the antenna 2. The aspect ratio of the signal induced in the antennas 1 and 2 is 4: 3. The high-frequency video signal induced in the antenna 1 is supplied to the tuner 3, and the tuner 3 demodulates the video after selecting a predetermined channel of satellite broadcasting, and becomes a baseband video signal. 5 is supplied. The high-frequency video signal induced in the antenna 2 is tuned by the tuner 6, and the signal of a predetermined channel becomes the second
After being converted to an intermediate frequency, the image is demodulated and becomes a baseband image signal, which is supplied to the parent screen switch 4 and the child screen switch 5. Also, a baseband external video signal can be supplied to the master screen switch 4 and the slave screen switch 5 via the external video input terminal 7.

The parent screen switch 4 selects a source to be displayed as a parent screen, and the child screen switch 5 selects a source to be displayed as a child screen. Main screen switch 4
The video signal selected by is supplied to the parent screen decoder 7 as a parent signal. Hereinafter, the main screen switch 4 selects the output of the tuner 3, and the sub screen switch 5 selects the tuner 6
It is assumed that the output of is selected.

The main screen video decoder 7 separates the horizontal sync signal fh1 and the vertical sync signal fv1 from the input video signal, and at the same time, the pixel clock CK synchronized with the video signal.
1 is generated and supplied to the input terminals 9 and 20 via the output terminal 8. Further, the parent screen video decoder 7 decodes the video signal to reproduce the component signals such as the color signals R, G, B, the luminance signal Y, and the color difference signals RY, BY. These component signals are supplied to the compression circuit 10 where they are horizontally compressed to 1/2. As a result, the parent screen image can be displayed on the horizontal half (right side) of the display area. The output of the compression circuit 10 is given to the switch 17.

On the other hand, the video signal selected by the sub-screen switch 5 is the sub-screen video decoder 1 as a sub-screen signal.
1 is supplied. The sub-picture video decoder 11 decodes the sub-picture signals and reproduces component signals such as color signals R, G, B, luminance signal Y, color difference signals RY, BY. The small screen video decoder 11 also generates a horizontal synchronizing signal fh2 and a vertical synchronizing signal fv2 indicating the display area of the small screen and a pixel clock CK2 synchronized with the small screen signal and supplies the pixel clock CK2 to the write control circuit 1301. The component signal from the small screen decoder 11 is given to the compression circuit 12.

In the compression circuit 12, in order to display a plurality of sub-screens (three in the horizontal direction) in the area of 1/2 (left side) of the screen, the sub-screen images of the respective channels are horizontally ⅙. Compress to. Also, since three images are displayed in the vertical direction, the sub-picture video signal is compressed to 1/3 in the vertical direction. The output of the compression circuit 12 is given to the child screen memory (RAM) 1306 through the address control circuit 1305.
The address control circuit 1305 performs address control of writing and reading of video on the RAM 1306.

The write control circuit 1301 controls the address control circuit 1305 to synchronize with the synchronization signal of the small screen, and the compressed small screen image from the compression circuit 12 is transferred to the RAM1.
It is controlled so as to be written in 306. At this time R
The area of AM1306 is divided as shown in FIG. 14B, and the first channel is area A, the second channel is area B ... The ninth channel is area I, and so on. The video of the channel is stored.

These controls are performed by the write control circuit 130.
1 and the channel control means 1302 are interlocked. The channel control means 1302 changes the tuning channel of the tuner (tuner 6 in this example) at regular time intervals, and in conjunction with this, the write control circuit 130.
1 sequentially changes the writing area of the RAM 1306 into areas A to I. When the data is written up to the area I, the channel is returned to the first channel and the following steps are repeated.

On the other hand, the read control circuit 1303 receives the clock CK1 and the horizontal and vertical synchronization signals f via the input terminal 9.
h1 and fv1 are given to the address control circuit 13
Read control of the RAM 1306 is performed via 05.

This read operation is performed in synchronization with the sync signal of the main screen, and the information displayed in the horizontal direction is read continuously, so that the information of channels 1 to 3 is simultaneously read or the information of channels 4 to 6 is read. At the same time, or the information of channels 7 to 9 is read at the same time. On the other hand, the switching signal generator 1304 is supplied with the clock CK1 and the horizontal and vertical synchronization signals fh1 and fv1 via the input terminal 9, and supplies the switching signal to the switch 17 in synchronization with the parent screen. The switch 17 switches the signals of the parent screen and the child screen based on the signal from the switching signal generator 1304 and supplies the signals to the display unit 18. Display 1
In 8, the images of the parent screen and the child screen are combined and displayed based on the synchronization signal from the input terminal 20. With the configuration as described above, a plurality of child screen images are displayed while displaying the parent screen.
As shown in (a), it can be displayed as nine pieces of video information.

[0013]

However, since the RAM 1306 is used as the sub-screen memory in the above-mentioned configuration, an address line is required and the circuit becomes complicated. Furthermore, if the speed of channel feed is increased in order to bring all nine screens closer to a moving image, the screen becomes difficult to see. This is because the video storage means being read and the video storage means being written are the same, so the image of the portion displayed while being rewritten is moving. Therefore, since any of the nine screens has changed, if the moving time of the moving image position is shortened, the screen flickers and becomes difficult to see.

In view of the above problems, the present invention uses a first-in first-out memory (FIFO), which does not require an address line and is cheaper than a RAM, as a sub-screen memory, and does not flicker even if the channel is switched quickly, thus providing a multi-screen. It is intended to provide a television receiver in which everything can be displayed like a moving image.

[0015]

In order to solve the above-mentioned problems, the number of address lines is reduced by using a FIFO for a sub-screen memory. Further, since the FIFO is generally cheaper than the RAM, it is advantageous in manufacturing. Moreover, FI
The capacity of the FO is divided into two screens, the divided areas are written into these two areas, and the non-written areas are read out so that all the multi-screens displayed in the sub-screens are displayed so as to be changed at the same timing. . At this time, if the display area of the small screen is smaller than 1/2 of the horizontal direction of the display device, the display area is changed by writing the two areas by line interleaving and changing the read start position. If the display area of the sub-screen is smaller than 1/2 of the vertical direction of the display device, the two areas are divided into upper and lower areas of the memory for writing, and the display area is changed by changing the reset signal or the read period. To do.

A: Specifically, a display device for displaying a video signal, tuning means for sequentially tuning N-channel television broadcasting, and video of the selected N-channel television broadcasting. A compression means for compressing a signal, a first-in first-out type memory having a capacity for writing the video information compressed by the compression means into two areas by N channels, and a line interleave by M channels of the video signal. In the memory, writing control means for writing in the memory, reading control means for controlling the reading of the memory in accordance with the synchronizing signal of the display device, and a period of 1/2 or less of one cycle of the horizontal synchronizing signal of the display device, Switching means for selectively providing the output of the first-in first-out memory side to the display device; Until just before selecting the force, and means for advancing to the beginning address of the not write the read address of the first-in first-out type memory side.

B: Further, a display device for displaying a video signal, a channel selecting means for sequentially selecting N-channel television broadcasts, and a video signal for the selected N-channel television broadcasts are compressed. And a first-in first-out type memory having a capacity for writing the video information compressed by the compression means into N-channels for each of the low-order side and the high-order side of the address, and the N-channel video signal for the first-in first-out Type memory for writing to either the low side or the high side of the address, read control means for controlling the reading of the first-in first-out memory memory according to the synchronizing signal of the display device, and the vertical direction of the display device. The output of the first-in first-out memory side is output to the display device during a period equal to or less than 1/2 of one cycle of the synchronization signal. Comprising a switching means for providing in-option, the time immediately before selecting the output of said first-in first-out type memory side, and means for advancing to the address head of the not write the read address of the first-in first-out type memory side.

[0018]

According to the present invention, the number of wirings can be reduced by using the first-in first-out memory as the child screen memory.
When the sub screen is displayed smaller than 1/2 of the horizontal size of the display device by the means A, the sub screen displayed on the N screen does not flicker even if the speed of channel change is increased. The entire N screen is displayed in a state close to a moving image. Further, when the sub-screen is displayed smaller than 1/2 of the vertical size of the display device by the means B, the sub-screen displayed on the N-screen flickers even if the channel change speed is increased. Instead, the entire N screen is displayed in a state close to a moving image.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a multi-screen television receiver according to the present invention. In FIG. 1, the same parts as those in FIG. 13 are designated by the same reference numerals. In addition, as shown in FIG. 2, for example, the multi-screen display method is that the main screen is horizontally compressed to 1/2 and displayed on the left side toward the screen, and the multi-screens that are sub-screens are displayed on the right side. The case will be described.

A satellite broadcast signal is induced in the antenna 1. Further, the antenna 2 may be, for example, UHF or VHF.
The high frequency video signal of broadcasting is induced. The aspect ratio of the signal induced in the antennas 1 and 2 is, for example, 4: 3. The high-frequency video signal induced in the antenna 1 is supplied to the tuner 3, and the tuner 3 demodulates the video after selecting a predetermined channel of the satellite broadcast signal, and the demodulated baseband video signal is the parent screen switch 4 and the child screen. It is supplied to the screen switch 5. The high-frequency video signal induced in the antenna 2 is tuned by the tuner 6, the signal of a predetermined channel is converted to the second intermediate frequency and then demodulated, and the demodulated baseband video signal is displayed on the master screen switch 4 and the slave screen. It is supplied to the switch 5. Also the parent screen switch 4
Also, a baseband external video signal can be supplied to the sub-screen switch 5 via the external video input terminal 7.

The parent screen switch 4 is for selecting the source to be displayed as the parent screen, and the child screen switch 5 is for selecting the source to be displayed as the child screen. Switch 4 on the main screen
The video signal selected by is supplied to the parent screen decoder 7 as a parent signal. In the following description, it is assumed that the parent screen switch 4 selects the output of the tuner 3 and the child screen switch 5 selects the output of the tuner 6.

The main screen video decoder 7 receives a horizontal synchronizing signal fh1 from the video signal selected and demodulated by the tuner 3.
The vertical synchronizing signal fv1 is separated, and the pixel clock CK1 synchronized with the video signal is generated and supplied to the input ends 9 and 20 via the output end 8. Further, the parent image video decoder 7 decodes the video signal to obtain the color signals R, G,
B, component signals such as luminance signal Y, color difference signals R-Y, and B-Y are reproduced. These component signals are supplied to the compression circuit 10.

In the compression circuit 10, the parent signal is 1 / horizontally in the horizontal direction.
Compress to 2. The output of the compression circuit 10 is given to the switch 17. On the other hand, the video signal selected and demodulated by the tuner 6 selected by the small screen switch 5 is supplied to the small screen video decoder 11 as a small screen signal.
The sub-picture video decoder 11 decodes the sub-picture signals to obtain color signals R, G, B, a luminance signal Y, and a color difference signal R-.
Reproduces component signals such as Y and BY. The small screen video decoder 11 also generates a horizontal synchronizing signal fh2 and a vertical synchronizing signal fv2 indicating the display area of the small screen and a pixel clock CK2 synchronized with the small screen signal, and supplies the pixel clock CK2 to the write control circuit 14. The component signal output from the small screen decoder is supplied to the compression circuit 12.

In the compression circuit 12, since a plurality of sub-screens are displayed in a half area of the entire screen, in order to display three sub-screens in the horizontal direction, the sub-screen images of the respective channels are displayed in the horizontal direction. Compress to 1/6. Further, since three images are displayed in the vertical direction, the sub-screen video signal is ⅓ in the vertical direction.
Compress to. The output of the compression circuit 12 is the FIFO 13
Is supplied to.

The FIFO 13 can perform writing and reading asynchronously, and can advance only the address pointer without changing data at the time of writing, and can move the writing address to a predetermined address. Also, the FIFO
Are generally cheaper than RAMs and do not require address lines, which is advantageous in manufacturing because wiring can be reduced.

The write control circuit 14 gives a control signal such as a write clock signal, a write enable signal, an input enable signal, and a chip select signal to the FIFO 13 to control the writing of the video signal for the child screen from the compression circuit 12. . Further, the display area change signal CH is given to the read control circuit 15.

The read control circuit 15 receives the clock CK1, horizontal and vertical sync signals fh1 and fv via the input terminal 9.
1 is given, and the read enable signal RE, the read clock CKR, and the read reset signal RESR are given to the FIFO 13 to control the video reading from the FIFO 13.

The data read from the FIFO 13 is
It is supplied to 17 with a switch. The switch 17 selects either the parent screen signal or the child screen signal input based on the signal from the switching signal generator 16 and supplies it to the display unit 18. The display 18 displays the combined video signal based on the synchronization signal input from the input terminal 20. The switching signal generator 16 receives the clock CK input from the input terminal 9.
1. Based on the horizontal and vertical synchronization signals fh1 and fv1, the switching signal is given to the switch 17 so that the parent screen is displayed on the left side of the display 18 and the child screen is displayed on the right side.

The channel control circuit 19 controls the tuner 3 and the tuner 6 to switch channels.
Further, the write control circuit 14 is instructed of the write area corresponding to each channel.

The write operation of the FIFO 13 will be described below. FIG. 3 shows how the area of the FIFO 13 is divided. The first channel is the area A or A ',
The image of each channel is stored in a separate area for each channel, such as area B or B '... for the second channel and I or I'for the ninth channel.

The write control of the FIFO 13 is performed by the write control circuit 14 and the channel control circuit 19 working together. The channel control circuit 19 changes the channel selected by the tuner 6 to 1, 2, 3, ... At constant time intervals, and in conjunction with this, the write control circuit 14 causes the FI
The write address of the FO 13 is sequentially changed like A, B, C .... After writing to the area I, the channels are changed to channels 1, 2, 3, ... And in conjunction with this, the write control circuit 13 sets the write addresses of the sub-screen memory to A ', B', C '... Change in order. Region I '
After writing to, go back to channel 1 again, write to A, and so on. In this example, the tuner 6 sequentially selects and demodulates the video signal of each channel given to the child screen memory.

Next, with reference to FIG. 4, the state of the memory in units of lines will be described. As shown in FIG. 4, after writing the data A1 for one line of the channel 1 and advancing the address pointer without performing address writing until the data amount for five lines is reached, the next one line of the channel 1 is written. The data A2 of is written. In this way, writing is performed for each line of data that is twice the number of screens of the child screen displayed in the horizontal direction. That is, here, as shown in FIG. 2, three individual screens are displayed in the horizontal direction, so that writing is performed for each data of 6 lines. In order to write the channel 2 in the area B, the address pointer is advanced to the address corresponding to the data for one line before writing the data of the first line, the data writing is started from B1, and the area A is written in the following. As with writing, writing is performed for every 6 lines of data. By repeating this, the data is written in the FIFO 13 as shown in FIG. Here, the memory areas A to I are area a, the memory areas A ′ to I ′ are area b, and data a1, a2, ...
And the data b1, b2, ...
The data is written in the FIFO 13 alternately. That is, area a
The data of b and b are written by line interleaving. By writing in this way, it is possible to divide into writing areas as shown in FIG.

The write control circuit 14 is a FIFO.
The display position change signal CH is set to a low level while the areas A to I of 13 are written, and the display position change signal CH is set to a high level while A'to I'is written.

On the other hand, the read control circuit 15 is connected to the display 1
The data of the FIFO 13 is read out in synchronization with the synchronization signal given to the signal 8. At this time, the information displayed in the horizontal direction is
Since they are read out successively, the information of the channels 1 to 3 and 1'to 3'are simultaneously obtained, or the information of the channels 4 to 6 and 4'to 6'at the same time, or 7 to 9 and 7 '.
The information of the 9'channel will be read at the same time.

FIG. 5 shows a more detailed block diagram of the read control circuit 15. Clock CK1, vertical synchronizing signal fv1, horizontal synchronizing signal fH from the input terminal 513
1 is input. The clock CK1 is given to the H counter 507 through the signal line 513a. Also clock C
K1 is the read clock CKR through the signal line 513e.
Is given to the output terminal 515. Vertical sync signal fv
1 is supplied to the V counter 501 through the signal line 513d. Further, the vertical synchronization signal fv1 is output as a read reset signal RESR through the signal line 513d to the output terminal 51.
Given to 5. The horizontal synchronizing signal fH1 is supplied to the signal line 513.
It is given to the H counter 507 and the V counter 501 through b and 513c, respectively. On the other hand, the input terminal 514
From, the read area change signal CH is input and given to the AND circuit 519.

The V counter 501 has a horizontal synchronizing signal f.
H1 that is, the number of lines is counted, and the vertical synchronization signal fv1
Is initialized by. The output of the V counter 501 is given to the comparator 502 and the comparator 503. Comparator 502
Then, the read start line value 504 and the V counter 50
The output value of 1 is compared, and if they match, the output signal is set to the low level for the 1H period. Further, the comparator 503 compares the value 505 of the read end line with the output value of the V counter 501, and when they match, the output signal is set to 1
Set to low level for H period. Therefore, the output of the RS flip-flop 506 is output with the high level in the vertical direction designated for reading.

On the other hand, the H counter 507 has a clock CK.
1 is counted and initialized by the horizontal synchronizing signal fH1. The output of the H counter 507 is given to the comparator 508 and the comparator 509. In the comparator 508, the value of the read start position A or B is compared with the output value of the H counter 507, and if they match, the output signal is set to low level. Further, the comparator 509 compares the value 510 at the read end position with the output value of the H counter 507,
When they match, the output signal is set to low level. Therefore, the output of the RS flip-flop 511 is output with the high level in the horizontal direction designated for reading.

The logical product circuit 512 calculates the logical product of the output of the RS flip-flop 506 and the output of the RS flip-flop 511 and outputs it as a read enable signal RE from the output terminal 515. Only during the period when the read enable RE is output, the read address advances and the data is read in synchronization with the read clock CKR.

The value given to the comparator 508 is switched by the switch 518. The logical product of the inverted value of the output of the comparator 502 and the display area change signal CH is obtained by the logical product circuit 519, and switching is performed according to the output level of the logical product circuit 519. That is, the V counter 501
Display area change signal C that matches the read start line
The read start position B is set to the comparator 5 only when H is at the high level.
It is given to 08. Here, the read start position B is set to be the midpoint between the read start position A and the read end position, and the number of data read when the read start position B is selected is the same as when the read start position A is selected. It is set to be 1/2 of the read data.

The read operation of the FIFO 13 will be described with reference to FIG. Here, a1, b1 ... Match with FIG. When the display area change signal CH is at low level,
The read start position of the read start line becomes A, and as shown in FIG. 6A, the data a of the first line of the area a
1 is read from the left end, and then the data b1 of the first line of the area b is read. The following lines are also read in the same manner. Eventually, the data of the area a is read on the left side of the screen and the data of the area b is read on the right side.

On the other hand, when writing to A'-I ', the read display area change signal CH becomes high level, and the read start position is changed only for the read start line to become the read start position B. At this time,
As in (b), a1 is read at the position where b1 was read in FIG. 6 (a). Then, the read data is shifted so that the data in the area b is read on the left side and the data in the area a is read on the right side.
Therefore, when the read area change signal is written from A'to I ', the read start position is B on the read start line.

Since the read data is selected by the switch and given to the display device, the parent screen is selected on the left side of the screen and the child screen is selected on the right side of the screen, and the display 18
Will display either the memory area a or b.

As described above, according to this embodiment, when reading an image of 9 channels, the area not written is displayed, so that the flicker of the screen caused by the rewriting operation is eliminated, and the 9 screens change simultaneously. It can be displayed as a quasi-video.

Further, the display position of the sub-screen may be other than the above as long as it can be displayed within 1/2 of one cycle of the horizontal period of the display device as shown in FIG. 7, and the size in the vertical direction is also the above. It may be other than. Further, the aspect ratio of the display device 18 and the compression rate of the parent screen may be other than those described above, and other video may be displayed without displaying the parent screen. Further, the child screen may be displayed so as to overlap a part of the parent screen. Further, when the control of the read position is controlled by using a processor or the like, it can be realized by changing the setting value of the software.

FIG. 8 shows another embodiment of the present invention. Elements that operate in the same manner as in FIG. 1 are assigned the same reference numerals and explanations thereof are omitted. In this embodiment, the operations of the write control circuit, the channel control circuit, the read control circuit, and the switching signal generator are slightly different from those in the above-described embodiment, so that the respective circuits are given different reference numerals such as 801, 802, 103, 804. are doing.

The operation of the above apparatus will be described. Figure 9
An operation of displaying the parent screen on the upper side of the display 18 and displaying eight sub-screens on the lower side as in (a) and (c) will be described. The parent screen image from the parent screen image decoder 7 is given to the compression circuit 10 to compress the parent screen vertically to 1/2,
The output is given to the switch 17.

On the other hand, the sub-picture video signal from the sub-picture decoder 11 is compressed by the compression circuit 10 to 1/4 in the horizontal direction and 1/4 in the vertical direction. The output of the compression circuit 10 is given to the child screen memory 13.

The write control circuit 801 includes a FIFO 13
A control signal such as a write clock signal, a write enable signal, an input enable signal, and a chip select signal is given to control the writing of the video signal for the small screen from the compression circuit 12 in the small screen memory (FIFO) 13. .

The read control circuit 803 receives the clock CK1 and the horizontal and vertical sync signals fh1 and f through the input terminal 9.
v1 is given, and the control signal of the read clock CKR, the read enable signal RE, and the read reset signal RESR is given to the FIFO 13 to control the reading of data.

The data read from the FIFO 13 is
It is given to the switch 17. The switch 17 selects either the parent screen signal or the child screen signal that has been input based on the signal from the switching signal generator 804, and supplies it to the display unit 18. The display 18 displays the composite video signal based on the sync signal input to the input terminal 20. The switching signal generator 804 is based on the clock CK1 input from the input terminal 9 and the horizontal and vertical synchronization signals fh1 and fv1.
A switching signal is given to the switch 17 so that the parent screen is displayed on the upper side of 8 and the child screen is displayed on the lower side. The channel control circuit 802 controls the tuner 3 and the tuner 6 to switch channels. Further, the write control circuit 801 is instructed of the write area.

The write operation of the FIFO 13 will be described below. FIG. 10 shows how the area of the FIFO 13 is divided. The first channel is the area A or A ', the second channel is the area B or B' ..., The eighth channel H or H '. The video of each channel is stored in a separate area for each channel.

These controls are performed by the write control circuit 801.
And the channel control circuit 802 is interlocked. The channel control circuit 802 changes the channels of the tuner 6 to 1, 2, 3, ... At constant time intervals, and in conjunction with this, the write control circuit 801 causes the write control circuit 801 to change to the FIFO 13
The writing areas are sequentially changed to A, B, C, and so on, and when writing is performed up to the area H, the channels are changed to 1, 2, 3 ,. The control circuit 801 sequentially changes the write area of the FIFO 13 to A ', B', C '... When the data has been written up to the area H ', the channel 1 is returned to again, the data is written in A, and so on. Here, as shown in FIG. 11, the data of A to H are written in the upper part of the memory address, and the data of A ′ to H ′ are written in the lower part of the memory address.

In FIG. 11, A1 shows the data for one line of the first line of the child screen of one channel written in the area A, and a1 shows the data output on the first line read from the FIFO 13. By controlling the writing in this way, it is possible to write data in a divided region as shown in FIG.

The display area change signal CH is given to the read control circuit 803. Read area change signal CH
Becomes high level while writing in the lower area A'to H ', and becomes low level in other cases.

On the other hand, the read control circuit 803 uses the FIF
The data is read from O13 in synchronization with the synchronization signal given to the display 18, and the information displayed in the horizontal direction is continuously read. Information at the same time, or 1'-4 'information at the same time, or 5'
The ~ 8 'channels are read simultaneously.

The operation of the read control circuit 803 will be described below. By outputting the read reset signal RESR, the read address is returned to the lowest. In the read enable RE, the read address advances and data is output in synchronization with the read clock CKR only during the period when this signal is output.

FIG. 12 shows a more detailed block diagram of the read control circuit 803. Input terminal 101
A clock CK1, a vertical synchronizing signal fv1, and a horizontal synchronizing signal fH1 are input from 7. The clock CK1 is the signal line 1
It is supplied to the H counter 1006 through 017a. The clock CK1 is also output to the output terminal 1019 as the read clock CKR. The vertical synchronization signal fv1 is
It is supplied to the V counter 1001 through the signal line 1017d. Further, the vertical synchronization signal fv1 is supplied to the logical sum circuit 1016.
Also given to. The horizontal synchronizing signal fH1 is supplied to the signal line 101.
H counter 100 through 7b and 1017c respectively
6 and V counter 1001. On the other hand, the display area change signal CH is input from the input terminal 1018 and is given to the OR circuit 1015.

The V counter 1001 has a horizontal synchronizing signal fH.
1, that is, the number of lines is counted and initialized by the vertical synchronizing signal fv1. The output of the V counter 1101 is given to the comparator 1002, the comparator 1003, and the comparator 1004. In the comparator 1002, the value of the read start line is 1
020 and the value of the V counter 1001 are compared, and if they match, the output signal is set to low level. Comparator 1
In 003, the value 1021 on the read end line and the value of the V counter 1001 are compared, and if they match, the output signal is set to the low level. Therefore, the output of the RS flip-flop 1005 is at the high level during the read-specified vertical period. The comparator 1004 compares the value 1022 of the reset line with the value of the V counter 1001 to set the vertical position for outputting the reset signal.

On the other hand, the H counter 1006 counts the clock CK1 of the parent screen and is initialized by the horizontal synchronizing signal fH1. The output of the H counter 1006 is the comparator 10
07 and the comparator 1008, the comparator 1009 and the comparator 1
010 is supplied. The comparator 1007 compares the read start position A with the value of the H counter 1006, and if they match, sets the output signal to the low level. Comparator 1
At 008, the read end position 1024 and the H counter 1
The value of 006 is compared, and if they match, the output signal is set to low level. Therefore, the RS flip-flop 10
The output of 11 becomes high level during the horizontal direction designated for reading. Reset start position 1 in the comparator 1009
025 and the value of the H counter 1006 are compared, and the comparator 1
At 010, the reset end position 1026 and the H counter 1
The values of 006 are compared. As a result, the output of the RS flip-flop 1012 is output as a high level while the value of the H counter 1006 is between the reset start position and the reset end position.

Output of RS flip-flop 1005 and R
The read enable signal RE is obtained by obtaining the logical product of the outputs of the S flip-flops 1011 by the logical product circuit 1013. The output of the AND circuit 1013 is output to the output terminal 1019 as the read enable signal RE.

The output of the AND circuit 1014 is a reset output line, and the value of the horizontal H counter 1006 becomes high level during the period of reset start and reset end. The output of the logical product circuit 1015 is the logical product circuit 10
It is output when the output of 14 is at a high level and the display area change signal CH is at a high level. The output of the logical product circuit 1015 is given to the logical sum circuit 1016, and is logically summed with the inverted signal of the vertical synchronizing signal fv1 and output from the output terminal 1019 as the memory read reset signal RESR. Therefore, the memory read reset signal RESR
Is output every time the vertical synchronizing signal fv1 is input, and whether the output of the AND circuit 1014 in the high level reset output period is output to the memory as the reset signal RESR depending on the level of the display area change signal CH. Whether or not is selected.

The read operation will be described with reference to FIG. A to H in the upper area of the memory, A'to H'in the lower area
It is assumed that the data of is written. When displaying A'to H'on the lower side of the display device, the reading of data is started from the position shown in FIG. 9B and the reading is performed so that only the lower region is displayed. At this time, the read reset is output at the position of the arrow in FIG. 9A so that the address becomes the lowest just before starting the reading. By this, it is possible to advance to the address to be displayed by the time immediately before reading the address.

On the other hand, in order to display the upper areas A to H, the read range is set as in the case of FIG.
At the timing of the arrow of (c), reset is output again during the period from the end of reading H to the start of next reading. The state of the data read at this time is shown in FIG.
It is shown in (d). At this time, the upper area is read twice.

In this way, in order to change the range read and displayed from the FIFO 13 between the lower and upper memory addresses, it is sufficient to change the timing of the reset signal without changing the read range.

Further, the display range is not limited to the above case, and the display area can be changed as shown in FIGS. 9 (e) and 9 (f). This is the beginning of reading
The display area can be changed by changing as shown in (b) and FIG. 9 (f). In addition, the display range may be any display range in which the upper region can be read during the period other than the display range and the address can be advanced to the lower region before the display starts.
FIG. 10 shows an example thereof. 10 (a) and 10 (c)
Shows the display position and the output position of the reset lead.
0 (b) and FIG. 10 (d) show the state of the memory area in each of the above cases. In this way, the vertical read range is set at two places, the read set is output immediately after the display range is read, and the read reset is output immediately before the display range.

Then, the above-mentioned change of the read area is controlled so that the area which is not written is read. In addition, the aspect ratio of the display device, the number of screens, the compression ratio of the parent screen and the child screen, and the display position may be other than the above. If the read position control or reset lead is controlled using a processor, etc., the software It can also be realized by changing the setting value of. As described above, according to this embodiment, since the 8-channel image is read out by displaying the unwritten area, the flicker of the screen caused by the rewriting operation is eliminated, and the multi-screen is displayed as a quasi-moving image that changes simultaneously. be able to. The display does not need to be integrated, and may be a separate display device.

[0067]

As described above, according to the present invention, when a plurality of N child screens are simultaneously displayed on the display, the N child screens are all updated at the same timing. For this reason, since a part of the screen, which has been a problem in the past, is always moving and moving, the screen does not flicker when the channel change speed is increased, and the screen is easy to see. Further, since the child screen memory FIFO is used, it is cheaper than the case of using a RAM, and an address line is not required, which is advantageous in manufacturing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a multi-screen television receiver according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a display screen of the multi-screen television receiver.

FIG. 3 is an explanatory diagram for explaining an operation of a video memory of the multi-screen television receiver.

FIG. 4 is an explanatory diagram for explaining addresses of the video memory.

FIG. 5 is a block diagram showing a read control circuit for the video memory.

FIG. 6 is a conceptual diagram for explaining a read operation of the video memory.

FIG. 7 is a diagram showing another example of the display screen of the multi-screen television receiver.

FIG. 8 is a block diagram showing a multi-screen television receiver according to a second embodiment of the present invention.

FIG. 9 is an explanatory diagram for explaining the operation of the video memory according to the second embodiment.

FIG. 10 is a conceptual diagram for explaining a data read operation for the video memory of the second embodiment.

FIG. 11 is an explanatory diagram for explaining addresses of the video memory according to the second embodiment.

FIG. 12 is a block diagram showing a read control circuit for the video memory according to the second embodiment.

FIG. 13 is a block diagram showing a conventional multi-screen television receiver.

FIG. 14 is an explanatory diagram for explaining the operation of the memory of the conventional multi-screen television receiver.

[Explanation of symbols]

1, 2 ... Antenna, 3 ... Tuner, 4 ... Main screen switch, 5 ... Sub screen switch, 6 ... Tuner, 7 ... External video input terminal, 10 ... Compression circuit, 11 ... Sub screen video decoder, 12 ... Compression circuit, 13 ... Child screen memory, 14 ... Write control circuit, 15 ... Read control circuit, 16 ... Switching signal generator, 17 ... Switch, 18 ... Display device, 19 ...
Channel control circuit.

Claims (2)

[Claims] 1. A display device for displaying a video signal, a tuning means for sequentially tuning N-channel television broadcasts, and a compression for compressing the selected N-channel television broadcast video signals. Means, a first-in first-out type memory having a capacity for dividing the video information compressed by the compression means into two regions by N channels, and writing the video signal by M channels in the line interleave. Writing control means; reading control means for controlling the reading of the memory in accordance with a synchronization signal of the display device; and a period of ½ or less of one cycle of a horizontal synchronization signal of the display device with respect to the display device. Switching means for selecting and providing the output on the first-in first-out memory side, and selecting the output on the first-in first-out memory side. A means for advancing the read address of the first-in first-out memory to the beginning of the address on the non-writing side until just before the start of the multi-screen television receiver. 2. A display device for displaying a video signal, a tuning means for sequentially tuning N-channel television broadcasts, and a compression for compressing the selected N-channel television broadcast video signals. Means, a first-in first-out type memory having a capacity for writing the video information compressed by the compression means into N-channels on the low-order side and the high-order side of the address respectively, and an N-channel video signal on the first-in first-out type memory Write control means for writing to either the low-order side or the high-order side of the address, read control means for controlling the read-out of the first-in first-out type memory in accordance with the synchronization signal of the display device, and the vertical synchronization signal of the display device. The output from the first-in first-out memory side is selected and given to the display device during a period of 1/2 or less of one cycle. A multi-screen television comprising a switching means and means for advancing the read address of the first-in first-out memory to the beginning of the address on the non-writing side until just before selecting the output on the first-in first-out memory side. John receiver.