JPH08236825A - Superconducting element and its forming method - Google Patents

Superconducting element and its forming method

Info

Publication number
JPH08236825A
JPH08236825A JP7034914A JP3491495A JPH08236825A JP H08236825 A JPH08236825 A JP H08236825A JP 7034914 A JP7034914 A JP 7034914A JP 3491495 A JP3491495 A JP 3491495A JP H08236825 A JPH08236825 A JP H08236825A
Authority
JP
Japan
Prior art keywords
superconducting
electrode
junction
normal conductor
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7034914A
Other languages
Japanese (ja)
Inventor
Kazuo Saito
和夫 齊藤
Mutsuko Hatano
睦子 波多野
Mitsuo Suga
三雄 須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7034914A priority Critical patent/JPH08236825A/en
Publication of JPH08236825A publication Critical patent/JPH08236825A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To form an effective superconducting quantum thin wire in normal conductor forming a superconducting junction, by designing the width of a superconducting electrode to be narrower than an ordinary superconducting junction. CONSTITUTION: The width of superconducting electrodes 301, 302 is 1.0μm, and the electrode width of their tip parts is 0.5μm. The interval 200 between the superconducting electrodes 301 and 302 of superconducting junction parts where the superconducting electrodes face with each other via normal conductor is 0.5μm. In the state that a gate voltage is not applied, superconductivity couples in the normal conductor constituting the superconducting junction in a region which becomes shorter than the coherence length. The region becomes equivalent to a superconducting quantum wire. The width of the region where superconductivity couples in the normal conductor becomes much thinner than the width of an actual superconducting electrode, as the result of the influence of the boundary in the electrode width direction. When the width of the superconducting coupling region becomes narrower than the normal coherence length, an effective superconducting quantum wire can be formed in the normal conductor forming the superconducting junction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は超電導素子およびその作
製方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、平面型の超電導接合にゲート電極
を設けたいわゆる三端子型の超電導素子は、ザ・ニュー
・スーパーコンダクティング・エレクトロニクス(ナト
ー・アドバンスト・スタディー・インスィティチュート
・シリーズ,クルーワーアカデミックパブリッシャー
ズ,1993)第249頁〜第275頁に開示されてい
る。これらの従来技術では、常伝導体が金属もしくは半
導体である超電導電界効果型の三端子素子についてその
動作特性が示されている。
2. Description of the Related Art Conventionally, a so-called three-terminal type superconducting element in which a gate electrode is provided on a planar type superconducting junction is known as The New Superconducting Electronics (NATO Advanced Study Institute Series, Crew). War Academic Publishers, 1993) pp. 249-275. These prior arts show the operating characteristics of a superconducting field effect type three-terminal element in which the normal conductor is a metal or a semiconductor.

【0003】[0003]

【発明が解決しようとする課題】この従来技術のうち、
超電導素子で果たしうる機能は、ゲート電極への電圧印
加による超電導電流の制御による単純なスイッチング動
作のみである。
Among the conventional techniques,
The function that the superconducting element can fulfill is only a simple switching operation by controlling the superconducting current by applying a voltage to the gate electrode.

【0004】本発明の目的は新規の動作原理による、超
高速,低消費電力でかつ単体素子で論理機能を実現し、
さらにこれらの素子の組み合わせによって並列処理を容
易にする機能性超電導素子を提供することにある。
The object of the present invention is to realize a logical function with a single element at a very high speed and low power consumption according to a new operating principle.
Another object is to provide a functional superconducting device that facilitates parallel processing by combining these devices.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、本発明の超電導素子は、複数の超電導電極が常伝導
体を介して結合する平面型の超電導接合の構造を有し、
前記常伝導体中で超電導性が結合する超電導接合部の領
域は、前記超電導電極の形状によって超電導電極が近接
した第一の常伝導体の領域と、それよりも前記超電導電
極の間の距離が大きい第二の常伝導体の領域とを少なく
とも一つずつ形成するような形状の超電導電極で構成さ
れ、さらに前記第二の常伝導体の領域で前記超電導接合
部の面積を制御することが可能であるようにゲート電極
を構成する。
In order to achieve the above object, the superconducting element of the present invention has a structure of a planar type superconducting junction in which a plurality of superconducting conductive electrodes are coupled via a normal conductor.
The region of the superconducting junction where superconductivity is combined in the normal conductor is the region of the first normal conductor where the superconducting electrode is close to the superconducting electrode due to the shape of the superconducting electrode, and the distance between the superconducting electrodes is greater than that. It is composed of superconducting electrodes having a shape such that at least one large second normal conductor region is formed, and it is possible to control the area of the superconducting junction in the second normal conductor region. The gate electrode is configured as follows.

【0006】[0006]

【作用】本発明の超電導素子で前記超電導電極の幅は通
常の超電導接合よりも狭く設計される(典型的には1μ
m以下)。このように設計された超電導接合では、常伝
導体中で超電導性が結合する領域の幅が、電極幅方向の
境界の影響により実際の超電導電極の幅よりも非常に細
くなる。超電導結合領域の幅がノーマルコヒーレンス長
よりも狭くなると超電導接合を形成する常伝導体中で、
実効的な超電導量子細線が形成される。
In the superconducting device of the present invention, the width of the superconducting electrode is designed to be narrower than that of an ordinary superconducting junction (typically 1 μm).
m or less). In the superconducting junction designed in this way, the width of the region where the superconductivity is coupled in the normal conductor becomes much smaller than the actual width of the superconducting electrode due to the influence of the boundary in the electrode width direction. When the width of the superconducting coupling region becomes narrower than the normal coherence length, in the normal conductor forming the superconducting junction,
An effective superconducting quantum wire is formed.

【0007】超電導量子細線が形成されると、超電導接
合で定められる超電導波動関数の位相差の量子力学的な
遷移過程によって、超電導接合は超電導状態から電圧状
態へと遷移する。この効果を巨視的量子位相すべりとい
う。巨視的量子位相すべりは、超電導接合の臨界電流以
下のバイアス電流値で生じる。
When the superconducting quantum wire is formed, the superconducting junction transits from the superconducting state to the voltage state by the quantum mechanical transition process of the phase difference of the superconducting waveguide function defined by the superconducting junction. This effect is called macroscopic quantum phase slip. Macroscopic quantum phase slip occurs at a bias current value below the critical current of a superconducting junction.

【0008】本発明による超電導素子では、超電導電極
の形状によって超電導電極が近接した第一の常伝導体の
領域と、それよりも前記超電導電極の間の距離が大きい
第二の常伝導体の領域とを少なくとも一つずつ形成す
る。この素子構成により巨視的量子位相すべりによる電
圧状態への遷移が支配的かつ安定となる。臨界電流以下
での電圧状態が支配的かつ安定となるために本発明の超
電導素子の電流−電圧特性には巨視的量子位相すべりを
反映した負性抵抗が生じる。
In the superconducting element according to the present invention, the region of the first normal conductor in which the superconducting electrodes are close to each other due to the shape of the superconducting electrodes and the region of the second normal conductor in which the distance between the superconducting electrodes is larger than that. And at least one each. With this device configuration, the transition to the voltage state due to macroscopic quantum phase slip becomes dominant and stable. Since the voltage state below the critical current is dominant and stable, the current-voltage characteristics of the superconducting device of the present invention have a negative resistance reflecting macroscopic quantum phase slip.

【0009】上述した巨視的量子位相すべりによる負性
抵抗を用いると、本発明による超電導素子を用いてAN
D,OR,XOR,NAND等の論理機能が実行でき
る。さらに、前記ゲート電極に電圧を印加すると、電流
−電圧特性の負性抵抗の生じ方が変化する。この制御性
を利用すると単体で論理機能が実行できかつゲート電極
への電圧の印加により論理機能を切り替えることが可能
である超電導素子が実現できる。
When the negative resistance due to the above-mentioned macroscopic quantum phase slip is used, the superconducting element according to the present invention is used for AN.
Logical functions such as D, OR, XOR and NAND can be executed. Further, when a voltage is applied to the gate electrode, the way in which the negative resistance of the current-voltage characteristic is generated changes. By utilizing this controllability, it is possible to realize a superconducting device that can execute a logic function by itself and can switch the logic function by applying a voltage to the gate electrode.

【0010】[0010]

【実施例】【Example】

(実施例1)図1は本発明の第一の実施例による超電導
素子の上面図である。図2は本発明の第一の実施例の図
1におけるC−C′矢視の断面図である。まず図2によ
って本発明による超電導素子の基本的な作製プロセスを
説明する。シリコン単結晶よりなる基板100の表面に
熱酸化法によって厚さ約550nmのフィールド酸化膜
101を形成する。続いてボロンイオンを打ち込むこと
により半導体中の低不純物濃度領域102を形成する。
さらに、多結晶シリコン103,窒化シリコン104か
らなるゲート電極用の多層膜を形成する。このようにし
て形成したゲート電極用多層膜を電子線直接描画法とエ
ッチングを繰り返して加工し、ゲート電極を形成した。
次に砒素イオンを打ち込むことにより高不純物濃度領域
105を形成する。以上の作製プロセスにより常伝導体
領域として用いられる不純物濃度領域の直上にゲート電
極を備えた基板が形成できる。
(Embodiment 1) FIG. 1 is a top view of a superconducting element according to a first embodiment of the present invention. FIG. 2 is a sectional view of the first embodiment of the present invention taken along the line CC 'in FIG. First, a basic manufacturing process of the superconducting element according to the present invention will be described with reference to FIG. A field oxide film 101 having a thickness of about 550 nm is formed on the surface of a substrate 100 made of silicon single crystal by a thermal oxidation method. Then, by implanting boron ions, a low impurity concentration region 102 in the semiconductor is formed.
Further, a multi-layer film for the gate electrode, which is made of polycrystalline silicon 103 and silicon nitride 104, is formed. The gate electrode multilayer film thus formed was processed by repeating the electron beam direct writing method and etching to form a gate electrode.
Then, arsenic ions are implanted to form the high impurity concentration region 105. By the above manufacturing process, a substrate having a gate electrode can be formed immediately above the impurity concentration region used as the normal conductor region.

【0011】この基板表面を清浄化し、次に高真空中で
モレキュラビーム法によって超電導体Nbよりなる厚さ
100nmの超電導体層を形成する。上記、超電導体層
を電子線直接描画法によって形成したレジストパターン
をマスクとして、反応性イオンエッチング法によって加
工することにより、図1に示すような対向した超電導電
極301,302とゲート電極400とを含んだ超電導
素子が得られる。
The surface of this substrate is cleaned, and then a superconductor layer made of superconductor Nb and having a thickness of 100 nm is formed by a molecular beam method in a high vacuum. The superconducting layers 301 and 302 facing each other and the gate electrode 400 as shown in FIG. 1 are processed by the reactive ion etching method using the resist pattern formed by the electron beam direct writing method as a mask. A superconducting element containing the same can be obtained.

【0012】図3および図4に本発明の第一の実施例に
よる超電導素子の電流−電圧特性図を示す。図3がゲー
ト電圧を印加しない場合、図4がゲート電圧を印加した
場合である。ゲート電圧を印加しない状態では、超電導
接合を構成する常伝導体中にコヒーレンス長よりも短く
なる領域で超電導性が結合する。この領域は超電導量子
細線と等価となる。その結果、量子力学的な過程により
超電導状態から電圧状態に遷移する巨視的量子位相すべ
りが生じる。本発明による超電導素子ではこの現象によ
る電圧状態への遷移が支配的、かつ安定となる。巨視的
量子位相すべりによる電圧状態への遷移が安定になると
電流−電圧特性に負性抵抗が生じる。また、ゲート電圧
を印加した場合には超電導結合領域の幅が広くなる。こ
のとき巨視的量子位相すべりによる電圧状態への遷移は
抑制され、負性抵抗の生じ方も弱められる。
FIGS. 3 and 4 show current-voltage characteristics of the superconducting device according to the first embodiment of the present invention. 3 shows the case where the gate voltage is not applied, and FIG. 4 shows the case where the gate voltage is applied. When no gate voltage is applied, superconductivity is coupled in the normal conductor forming the superconducting junction in a region where the superconducting junction is shorter than the coherence length. This region is equivalent to a superconducting quantum wire. As a result, a macroscopic quantum phase slip that transitions from the superconducting state to the voltage state occurs due to the quantum mechanical process. In the superconducting device according to the present invention, the transition to the voltage state due to this phenomenon becomes dominant and stable. When the transition to the voltage state due to the macroscopic quantum phase slip becomes stable, a negative resistance occurs in the current-voltage characteristic. Further, when the gate voltage is applied, the width of the superconducting coupling region becomes wider. At this time, the transition to the voltage state due to the macroscopic quantum phase slip is suppressed and the negative resistance is weakened.

【0013】次に、図3,図4に示した特性曲線に基づ
く論理機能動作について説明する。本発明では独立な二
つの入力A,Bを超電導電極301に入力する場合を考
える。このとき表1に示した入力信号の各組み合わせと
これに対応する電流値は図3,図4に(0,0),
(0,1)などの記号で示すようになる。
Next, the logical function operation based on the characteristic curves shown in FIGS. 3 and 4 will be described. In the present invention, consider the case where two independent inputs A and B are input to the superconducting electrode 301. At this time, each combination of the input signals shown in Table 1 and the corresponding current value are (0, 0) in FIGS.
It is indicated by symbols such as (0, 1).

【0014】ゲート電圧を印加しない場合には、巨視的
量子位相すべりによる負性抵抗があるために入力(0,
0)に対する応答電圧が最も大きくなる。したがって、
図3に示したようなしきい電圧Vthを設定すると、入
力(0,0)のときだけ出力は、“1”であとはすべ
て、“0”となる。これにより、表1の真理表に示すN
OR論理を実行できる。また、ゲート電圧を印加する
と、負性抵抗の生じ方が弱められるため、先に定義した
入力信号を入れると本発明の超電導素子の電圧応答は、
表1に示すOR論理を実行できる。
When the gate voltage is not applied, there is a negative resistance due to the macroscopic quantum phase slip, so the input (0,
The response voltage for 0) is the largest. Therefore,
When the threshold voltage Vth as shown in FIG. 3 is set, the output is "1" only when the input is (0,0) and is "0". As a result, N shown in the truth table of Table 1
Can perform OR logic. Further, when a gate voltage is applied, the way in which negative resistance is generated is weakened. Therefore, when the input signal defined above is input, the voltage response of the superconducting element of the present invention is
The OR logic shown in Table 1 can be implemented.

【0015】[0015]

【表1】 [Table 1]

【0016】次に超電導素子の加工寸法の一例を示す。
図1に示した、超電導電極301,302の幅は1.0
μmであり、その先端部分の電極幅は0.5μmであ
る。また超電導電極が常伝導体を介して対向する超電導
接合部の超電導電極301と302の間隔は0.5μmであ
る。この寸法は一例であってこれに限るものではない。
推奨される寸法は各超電導電極の幅の寸法が50〜0.
2μm であり、超電導電極が常伝導体を介して対向す
る第一の超電導接合部の間隔の寸法は50〜0.05μmで
あり、第二の超電導接合部の間隔は50〜0.2μm で
ある。より望ましい寸法は各超電導電極の幅の寸法が2
〜0.5μm であり、超電導電極が常伝導体を介して対
向する第一および第二の超電導接合部の間隔の寸法は
0.5〜0.1μmである。
Next, an example of processing dimensions of the superconducting element will be shown.
The width of the superconducting electrodes 301 and 302 shown in FIG. 1 is 1.0.
μm, and the electrode width at the tip portion thereof is 0.5 μm. The distance between the superconducting electrodes 301 and 302 in the superconducting junction where the superconducting electrodes are opposed to each other with the normal conductor interposed therebetween is 0.5 μm. This size is an example, and the size is not limited to this.
The recommended dimensions are 50 to 0 for the width of each superconducting electrode.
The distance between the first superconducting junctions where the superconducting electrodes face each other via the normal conductor is 50 to 0.05 μm, and the distance between the second superconducting junctions is 50 to 0.2 μm. A more desirable size is that the width of each superconducting electrode is 2
.About.0.5 .mu.m, and the size of the interval between the first and second superconducting junctions where the superconducting conductive electrodes face each other via the normal conductor is 0.5 to 0.1 .mu.m.

【0017】(実施例2)図5は本発明の第二の実施例
による超電導素子の上面図である。本実施例の超電導素
子の作製工程および使用材料は本発明の第一の実施例と
同様であってよい。但し、本実施例では、超電導電極の
形状が凸型の針状電極である点と、超電導接合部には電
界効果の影響が生じないようにゲート電極が各超電導電
極の先端の側面に沿って形成されている点が異なってい
る。本実施例の場合も第一の実施例と同様に超電導接合
部には超電導量子細線と等価な領域が形成され、巨視的
量子位相すべりが生じる。超電導電極が凸型の針状電極
であるために、量子細線に等しい領域の幅はさらに狭く
なり、量子位相すべりによる電圧状態への遷移がより支
配的になり、負性抵抗の生じ方が先の実施例1で示した
結果よりも顕著になる。
(Embodiment 2) FIG. 5 is a top view of a superconducting device according to a second embodiment of the present invention. The manufacturing process and materials used for the superconducting element of this embodiment may be the same as those of the first embodiment of the present invention. However, in this embodiment, the shape of the superconducting electrode is a convex needle electrode, and the gate electrode along the side surface of the tip of each superconducting electrode so that the superconducting junction is not affected by the electric field effect. The difference is that they are formed. Also in the case of this embodiment, as in the first embodiment, a region equivalent to the superconducting quantum wire is formed in the superconducting junction, and macroscopic quantum phase slip occurs. Since the superconducting pole is a convex needle electrode, the width of the region equivalent to the quantum wire becomes narrower, the transition to the voltage state due to the quantum phase slip becomes more dominant, and the negative resistance is generated first. It becomes more remarkable than the result shown in the first embodiment.

【0018】ゲート電圧を印加すると、図5に示した超
電導接合部201の近傍ではゲート電極の形状により電
極幅方向にのみ超電導性が染みだす領域が拡がる。した
がって実効的な超電導量子細線の幅が広くなり、巨視的
量子位相すべりによる負性抵抗の生じ方が抑制される
が、その程度は実施例1の場合に比べると弱い。これは
ゲート電極の形状により超電導接合部には電界効果が顕
著に生じないため、巨視的量子効果も極端に抑制されな
いためである。
When a gate voltage is applied, the region where the superconductivity exudes only in the electrode width direction expands near the superconducting junction 201 shown in FIG. 5 due to the shape of the gate electrode. Therefore, the width of the effective superconducting quantum wire becomes wider, and the generation of negative resistance due to macroscopic quantum phase slip is suppressed, but the degree thereof is weaker than that of the first embodiment. This is because the electric field effect is not significantly generated in the superconducting junction due to the shape of the gate electrode, and the macroscopic quantum effect is not extremely suppressed.

【0019】図6および図7に本実施例による超電導素
子の電流−電圧特性図を示す。図中に用いた記号の意味
は実施例1の場合(図3,図4)と同様である。また、
図6がゲート電圧を印加しない場合、図7がゲート電圧
を印加した場合である。これらの電流−電圧特性に基づ
き、本発明の第一の実施例で説明したと同様に、ゲート
電圧を印加しない場合にはXOR、印加した場合にはN
AND論理を実行することができる。表2にそれぞれの
真理表を示す。
FIGS. 6 and 7 show current-voltage characteristic diagrams of the superconducting device according to this embodiment. The meanings of the symbols used in the drawings are the same as in the case of the first embodiment (FIGS. 3 and 4). Also,
6 shows the case where the gate voltage is not applied, and FIG. 7 shows the case where the gate voltage is applied. Based on these current-voltage characteristics, as in the first embodiment of the present invention, XOR is applied when the gate voltage is not applied, and N is applied when the gate voltage is applied.
AND logic can be implemented. Table 2 shows each truth table.

【0020】[0020]

【表2】 [Table 2]

【0021】(実施例3)図8は本発明の第三の実施例
による超電導素子の上面図である。本実施例の超電導素
子の作製工程及び使用材料は本発明の第一の実施例と同
様であってよい。但し本実施例では、一方の超電導電極
に段差構造がなく、かつゲート電極も超電導接合部を完
全に覆う形状で形成されている点が異なっている。本発
明の第一および第二の実施例で示したように、超電導お
よびゲート電極の形状によって、巨視的量子位相すべり
による負性抵抗の生じ方を制御できる。本実施例におけ
る超電導電極,ゲート電極の形状は負性抵抗のピークが
ブロードになるように超電導電極301のみ矩形形状と
した。
(Embodiment 3) FIG. 8 is a top view of a superconducting device according to a third embodiment of the present invention. The manufacturing process and materials used for the superconducting device of this embodiment may be the same as those of the first embodiment of the present invention. However, this example is different in that one of the superconducting electrodes does not have a step structure and the gate electrode is also formed in a shape that completely covers the superconducting junction. As shown in the first and second embodiments of the present invention, it is possible to control how negative resistance is caused by macroscopic quantum phase slip depending on the shapes of superconducting and gate electrodes. As for the shapes of the superconducting electrode and the gate electrode in this embodiment, only the superconducting electrode 301 has a rectangular shape so that the peak of the negative resistance becomes broad.

【0022】図9および図10に本実施例による超電導
素子の電流−電圧特性を示す。また、図9がゲート電圧
を印加しない場合、図10がゲート電圧を印加した場合
の電流−電圧特性である。これらの電流−電圧特性に基
づき、第一の実施例で説明したと同様に、ゲート電圧を
印加しない場合にはOR、印加した場合にはAND論理
を実行することができる。表3にそれぞれの真理表を示
す。
9 and 10 show current-voltage characteristics of the superconducting device according to this embodiment. Further, FIG. 9 shows current-voltage characteristics when the gate voltage is not applied and FIG. 10 shows current-voltage characteristics when the gate voltage is applied. Based on these current-voltage characteristics, it is possible to execute OR when the gate voltage is not applied and AND logic when the gate voltage is applied, as described in the first embodiment. Table 3 shows each truth table.

【0023】[0023]

【表3】 [Table 3]

【0024】(実施例4)図11は本発明第四の実施例
による超電導素子の上面図である。本実施例の超電導素
子の作製工程および使用材料は第一の実施例と同様であ
ってよい。但し本実施例では、入力として用いる一方の
超電導電極は独立な二つの超電導電極から構成され、各
超電導接合部の構成はそれぞれ実施例2および3で示し
たNAND(XOR)および、OR(AND)論理機能
を果たす素子構成をとっている。したがってゲート電極
410および420に電圧を印加するか否かで、4通り
の論理機能の並列処理が実行できる。ゲート電圧の印加
の有無によって実行される並列処理を表4にまとめる。
本実施例の如き、論理機能を切り替えることができる機
能素子を組み合わせることによって、並列処理を行うこ
とが可能となる。
(Embodiment 4) FIG. 11 is a top view of a superconducting device according to a fourth embodiment of the present invention. The manufacturing process and materials used for the superconducting element of this embodiment may be the same as those of the first embodiment. However, in this embodiment, one superconducting electrode used as an input is composed of two independent superconducting electrodes, and the structure of each superconducting junction is NAND (XOR) and OR (AND) shown in Examples 2 and 3, respectively. It has an element configuration that fulfills the logical function. Therefore, parallel processing of four logic functions can be executed depending on whether or not a voltage is applied to the gate electrodes 410 and 420. Table 4 summarizes the parallel processing executed depending on whether or not the gate voltage is applied.
Parallel processing can be performed by combining functional elements capable of switching logical functions as in the present embodiment.

【0025】[0025]

【表4】 [Table 4]

【0026】以上の本発明による第一〜第四の実施例で
示した超電導素子による論理動作は、本発明による超電
導素子を例えば液体ヘリウム中で冷却することによって
得られる。また、以上の実施例で超電導体としてNbを
用いたが、これに換えてPb、あるいはPbの合金,N
bの金属間化合物、例えばNbN,Nb Sn,NbG
e,Nb Al,Nb Siなどを用いても良い。また常
伝導体としてSiを用いたが、これに換え半導体化合
物、例えばGaAs,InAsなどを用いても本発明の
目的を達成することができる。
The logical operation of the superconducting element shown in the first to fourth embodiments of the present invention can be obtained by cooling the superconducting element of the present invention in, for example, liquid helium. Further, although Nb is used as the superconductor in the above embodiments, Pb or an alloy of Pb, Nb may be used instead.
b intermetallic compound such as NbN, Nb Sn, NbG
You may use e, NbAl, NbSi etc. Although Si is used as the normal conductor, the object of the present invention can be achieved by using a semiconductor compound such as GaAs or InAs instead of Si.

【0027】上記の本発明による第四の実施例では、並
列処理を行なう超電導接合部に接続する超電導電極、お
よびゲート電極が二個の場合のみを示したが、三個以上
の場合にはさらに多数の論理演算の並列処理を実行する
論理機能超電導素子が実現可能である。
In the above-mentioned fourth embodiment of the present invention, only the case where there are two superconducting conductive electrodes and gate electrodes connected to the superconducting junction portion to be processed in parallel is shown. A logic function superconducting device that executes parallel processing of many logic operations can be realized.

【0028】[0028]

【発明の効果】本発明では平面型の超電導接合を用い
て、超電導性の染みだしにより常伝導体中に実効的に超
電導量子細線と等価な領域を形成し、平面型の超電導接
合で巨視的量子位相すべりが顕著に生じることを可能に
した。さらに、ゲート電極に電圧を印加して超電導性が
染みだす領域を拡大し、従来の三端子超電導素子では実
現できなかった巨視的量子位相すべりを制御する超電導
素子を実現可能とした。
According to the present invention, a plane type superconducting junction is used, and a region equivalent to a superconducting quantum wire is effectively formed in a normal conductor by superconducting bleeding. It enabled quantum phase slip to occur remarkably. Furthermore, by applying a voltage to the gate electrode, the region where the superconductivity exudes was expanded, and it became possible to realize a superconducting device that controls macroscopic quantum phase slip, which was not possible with conventional three-terminal superconducting devices.

【0029】この超電導素子を用いると、複数のスイッ
チング素子を用いた回路を構成することによって実現し
ていた論理演算機能(AND,OR,NAND,NO
R,XOR)を単体の素子で実現できる。さらに、これ
らの素子を組み合わせた構成にすると論理機能の切り替
えが可能で、かつ並列処理が実行できる超電導素子を実
現できる。本発明による超電導素子の特徴を活かすと集
積性に優れた超高速,低消費電力の超電導素子および情
報処理ユニットを実現できる。
When this superconducting element is used, logical operation functions (AND, OR, NAND, NO, which are realized by constructing a circuit using a plurality of switching elements).
(R, XOR) can be realized by a single element. Furthermore, by combining these elements, it is possible to realize a superconducting element capable of switching logical functions and executing parallel processing. By utilizing the features of the superconducting element according to the present invention, it is possible to realize a superconducting element and an information processing unit which are excellent in integration and have high speed and low power consumption.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例による超電導素子の上面
図。
FIG. 1 is a top view of a superconducting device according to a first embodiment of the present invention.

【図2】本発明の第一の実施例による図1におけるC−
C′断面を示す断面図。
FIG. 2 shows C- in FIG. 1 according to the first embodiment of the present invention.
Sectional drawing which shows C'section.

【図3】本発明の第一の実施例における超電導素子の動
作特性を表す電流−電圧特性図。
FIG. 3 is a current-voltage characteristic diagram showing operating characteristics of the superconducting element in the first embodiment of the present invention.

【図4】本発明の第一の実施例における超電導素子の動
作特性を表す電流−電圧特性図。
FIG. 4 is a current-voltage characteristic diagram showing operating characteristics of the superconducting element in the first embodiment of the present invention.

【図5】本発明の第二の実施例による超電導素子の上面
図。
FIG. 5 is a top view of a superconducting device according to a second embodiment of the present invention.

【図6】本発明の第二の実施例における超電導素子の動
作特性を表す電流−電圧特性図。
FIG. 6 is a current-voltage characteristic diagram showing the operating characteristics of the superconducting element according to the second embodiment of the present invention.

【図7】本発明の第二の実施例における超電導素子の動
作特性を表す電流−電圧特性図。
FIG. 7 is a current-voltage characteristic diagram showing operating characteristics of the superconducting element according to the second embodiment of the present invention.

【図8】本発明の第三の実施例による超電導素子の上面
図。
FIG. 8 is a top view of a superconducting device according to a third embodiment of the present invention.

【図9】本発明の第三の実施例における超電導素子の動
作特性を表す電流−電圧特性図。
FIG. 9 is a current-voltage characteristic diagram showing the operating characteristics of the superconducting element according to the third embodiment of the present invention.

【図10】本発明の第四の実施例における超電導素子の
動作特性を表す電流−電圧特性図。
FIG. 10 is a current-voltage characteristic diagram showing operating characteristics of the superconducting element in the fourth example of the present invention.

【図11】本発明の第四の実施例による超電導素子の上
面図。
FIG. 11 is a top view of a superconducting device according to a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

301,302…超電導電極(Nb)、400…ゲート
電極、200…超電導接合部。
301, 302 ... Superconducting electrode (Nb), 400 ... Gate electrode, 200 ... Superconducting junction.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】複数の超電導電極が常伝導体を介して結合
する平面型の超電導接合の構造を有し、前記常伝導体中
において超電導性が結合する超電導接合部の領域は、前
記超電導電極の形状によって超電導電極が近接した第一
の常伝導体の領域と、それよりも前記超電導電極の間の
距離が大きい第二の常伝導体の領域とを少なくとも一つ
ずつ形成するような形状の超電導電極で構成され、前記
第二の常伝導体の領域において前記超電導接合部の面積
を制御することが可能であるようにゲート電極が構成さ
れることを特徴とする超電導素子。
1. A superconducting junction having a planar structure in which a plurality of superconducting electrodes are coupled via a normal conductor, and a region of the superconducting junction in which superconductivity is coupled in the normal conductor is the superconducting electrode. Of a first normal conductor having a superconducting electrode close to each other by a shape of and a region of a second normal conductor having a larger distance between the superconducting electrodes than that, at least one by one. A superconducting element comprising a superconducting electrode, wherein a gate electrode is constituted so that the area of the superconducting junction can be controlled in the region of the second normal conductor.
【請求項2】請求項1において、前記ゲート電極に電圧
を印加することにより、前記超電導電極の幅方向、もし
くは電極間距離方向、もしくは両方向において定められ
る前記超電導接合部の面積が制御できるように、前記超
電導電極,前記ゲート電極が構成される超電導素子。
2. The area of the superconducting junction defined in the width direction of the superconducting conductive electrode, the distance between electrodes, or both directions can be controlled by applying a voltage to the gate electrode. A superconducting element comprising the superconducting conductive electrode and the gate electrode.
【請求項3】請求項1または2において、前記超電導接
合部を定める前記超電導電極は矩形形状であり、前記ゲ
ート電極は前記超電導電極の矩形形状に整合し、その一
部を覆う形状である超電導素子。
3. The superconducting electrode according to claim 1, wherein the superconducting electrode defining the superconducting junction has a rectangular shape, and the gate electrode has a shape matching the rectangular shape of the superconducting electrode and covering a part thereof. element.
【請求項4】請求項1,2または3において、前記超電
導接合部の面積を制御するために前記超電導電極は矩形
形状であり、前記超電導接合部を覆うように複数のゲー
ト電極が構成される超電導素子。
4. The superconducting electrode according to claim 1, 2 or 3, wherein the superconducting conductive electrode has a rectangular shape for controlling the area of the superconducting junction, and a plurality of gate electrodes are formed so as to cover the superconducting junction. Superconducting element.
【請求項5】請求項1,2または3において、前記超電
導接合部を構成する超電導電極の一方は、複数の独立な
超電導電極から構成され、前記超電導電極によって形成
されるそれぞれの超電導接合部にゲート電極が設けられ
ている超電導素子。
5. The superconducting conductive electrode according to claim 1, wherein one of the superconducting conductive electrodes forming the superconducting bonding part is composed of a plurality of independent superconducting conductive electrodes, and each of the superconducting bonding parts formed by the superconducting conductive electrodes is A superconducting device provided with a gate electrode.
【請求項6】請求項1,2,3,4または5において前
記超電導接合部に高周波数のマイクロ波を照射するため
の導波管あるいは導体を備えている超電導素子。
6. A superconducting element according to claim 1, 2, 3, 4 or 5, comprising a waveguide or a conductor for irradiating said superconducting junction with microwaves of high frequency.
【請求項7】請求項1,2,3,4または5において、
前記超電導接合部にレーザ光を導く導波管あるいは光フ
ァイバを備えている超電導素子。
7. The method according to claim 1, 2, 3, 4 or 5,
A superconducting element comprising a waveguide or an optical fiber for guiding laser light to the superconducting junction.
【請求項8】請求項1,2,3,4または5において、
超電導体は鉛,鉛の合金,ニオブ,ニオブ金属間化合物
より選ばれた材料であり、常伝導体は金,銀,銅、また
はアルミニウム及びその合金あるいは半導体や半導体化
合物あるいはその化合物より選ばれた少なくとも一つの
材料によって構成される超電導素子。
8. The method according to claim 1, 2, 3, 4 or 5.
The superconductor is a material selected from lead, a lead alloy, niobium, and a niobium intermetallic compound, and the normal conductor is selected from gold, silver, copper, or aluminum and its alloys, semiconductors, semiconductor compounds, or their compounds. A superconducting element composed of at least one material.
【請求項9】複数の超電導電極が常伝導体を介して結合
する平面型の超電導接合の構造を有し、前記常伝導体中
において超電導性が結合する超電導接合部の領域は、前
記超電導電極の形状によって超電導電極が近接した第一
の常伝導体の領域と、それよりも前記超電導電極の間の
距離が大きい第二の常伝導体の領域とを少なくとも一つ
ずつ形成するような形状の超電導電極で構成され、前記
第二の常伝導体の領域で前記超電導接合部の面積を制御
することが可能であるようにゲート電極が構成される超
電導素子において、少なくとも電子線直接描画法を用い
た超電導接合部の超電導接合部の超電導薄膜の加工を行
う工程を含むことを特徴とする超電導素子の作製方法。
9. A superconducting junction structure in which a plurality of superconducting electrodes are coupled via a normal conductor, and a region of the superconducting junction where superconductivity is coupled in the normal conductor is the superconducting electrode. Of a first normal conductor having a superconducting electrode close to each other by a shape of and a region of a second normal conductor having a larger distance between the superconducting electrodes than that, at least one by one. In a superconducting element composed of a superconducting electrode and having a gate electrode so that the area of the superconducting junction can be controlled in the region of the second normal conductor, at least the electron beam direct drawing method is used. A method of manufacturing a superconducting element, comprising the step of processing a superconducting thin film of a superconducting junction of the above-mentioned superconducting junction.
JP7034914A 1995-02-23 1995-02-23 Superconducting element and its forming method Pending JPH08236825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7034914A JPH08236825A (en) 1995-02-23 1995-02-23 Superconducting element and its forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7034914A JPH08236825A (en) 1995-02-23 1995-02-23 Superconducting element and its forming method

Publications (1)

Publication Number Publication Date
JPH08236825A true JPH08236825A (en) 1996-09-13

Family

ID=12427491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7034914A Pending JPH08236825A (en) 1995-02-23 1995-02-23 Superconducting element and its forming method

Country Status (1)

Country Link
JP (1) JPH08236825A (en)

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