JP3026482B2 - Superconducting element, method of manufacturing and operating method - Google Patents
Superconducting element, method of manufacturing and operating methodInfo
- Publication number
- JP3026482B2 JP3026482B2 JP7134886A JP13488695A JP3026482B2 JP 3026482 B2 JP3026482 B2 JP 3026482B2 JP 7134886 A JP7134886 A JP 7134886A JP 13488695 A JP13488695 A JP 13488695A JP 3026482 B2 JP3026482 B2 JP 3026482B2
- Authority
- JP
- Japan
- Prior art keywords
- superconducting
- voltage
- superconducting element
- voltage state
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000011017 operating method Methods 0.000 title 1
- 239000013078 crystal Substances 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 57
- 239000010409 thin film Substances 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 32
- 239000010408 film Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 19
- 239000002887 superconductor Substances 0.000 claims description 14
- 229910052788 barium Inorganic materials 0.000 claims description 8
- 230000005684 electric field Effects 0.000 claims description 8
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052797 bismuth Inorganic materials 0.000 claims description 7
- 229910052701 rubidium Inorganic materials 0.000 claims description 7
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052700 potassium Inorganic materials 0.000 claims description 6
- 239000011591 potassium Substances 0.000 claims description 6
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 5
- 210000000352 storage cell Anatomy 0.000 claims description 5
- 238000005304 joining Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 15
- 230000007423 decrease Effects 0.000 description 13
- 230000008859 change Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000010884 ion-beam technique Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- -1 niobium (Nb) Chemical class 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高速デジタル回路、ア
ナログデ−タ処理回路、センサ回路装置、微小磁場信号
検出装置等、超電導性を用いることによって特有の性能
を発揮する超電導エレクトロニクスの分野に係り、特
に、スイッチング速度が大きく、消費電力が低いという
優れた特性を有する３端子型超電導素子の素子構造とそ
の製造方法および動作方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of superconducting electronics, such as a high-speed digital circuit, an analog data processing circuit, a sensor circuit device, and a small magnetic field signal detecting device, which exhibit specific performance by using superconductivity. In particular, the present invention relates to an element structure of a three-terminal superconducting element having excellent characteristics such as high switching speed and low power consumption, and a method of manufacturing and operating the element.
【０００２】[0002]
【従来の技術】従来のスイッチング動作に使用される超
電導素子は、常伝導層を介して超電導電極が接続された
構造を有し、常伝導層に電界を印加するためのゲ−ト絶
縁膜およびゲ−ト電極が配設されている。この構造の素
子では、以下に述べる動作原理によってスイッチング動
作が実行される。すなわち、超電導近接効果によって、
常伝導層の超電導電極に接する部分に超電導キャリアが
滲み出し超電導性を帯びることになる。常伝導層が狭け
れば、両側の電極からの近接効果によって超電導性を帯
びた部分が繋がる。その結果、常伝導層を介して超電導
電流が流れる。超電導キャリアが滲み出して電極間に流
れる超電導電流の大きさは、常伝導層のキャリア濃度に
依存し、キャリア濃度が高くなるほど超電導電流は増大
する。したがって、ゲ−ト絶縁膜を介してゲ−ト電極に
電圧を印加し、電界効果によってキャリア濃度を変調す
ることにより超電導電流を制御することができる。な
お、超電導電流と同時に素子の抵抗値も増減する。この
ような超電導素子の超電導電極材料としては、ニオブ
（Ｎｂ）等の金属や、イットリウム（Ｙ）、バリウム
（Ｂａ）および銅（Ｃｕ）の酸化物等が用いられ、チャ
ネル層材料としては、シリコン（Ｓｉ）等の半導体やプ
ラセオジム（Ｐｒ）、ＢａおよびＣｕの酸化物等の非超
電導酸化物が用いられている。2. Description of the Related Art A conventional superconducting element used for a switching operation has a structure in which superconducting electrodes are connected via a normal conductive layer, and a gate insulating film for applying an electric field to the normal conductive layer and a gate insulating film. A gate electrode is provided. In the device having this structure, the switching operation is performed according to the operation principle described below. That is, by the superconducting proximity effect,
The superconducting carrier oozes into a portion of the normal conductive layer which is in contact with the superconducting electrode, and takes on superconductivity. If the normal conductive layer is narrow, a portion having superconductivity is connected by the proximity effect from the electrodes on both sides. As a result, the superconductive current flows through the normal conductive layer. The magnitude of the superconducting current that oozes out and flows between the electrodes depends on the carrier concentration in the normal conductive layer, and the higher the carrier concentration, the greater the superconducting current. Therefore, a superconducting current can be controlled by applying a voltage to the gate electrode via the gate insulating film and modulating the carrier concentration by the electric field effect. The resistance value of the element increases and decreases simultaneously with the superconducting current. Metals such as niobium (Nb), oxides of yttrium (Y), barium (Ba), and copper (Cu) are used as a superconducting electrode material of such a superconducting element, and silicon is used as a channel layer material. Semiconductors such as (Si) and non-superconducting oxides such as praseodymium (Pr), oxides of Ba and Cu are used.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の超電導
素子の素子構造において、超電導素子としての性能を発
揮し、十分な制御機能と、利得を有する素子を作製する
上で、以下に示す問題ないしは障害があった。すなわ
ち、従来の超電導素子構造では、利得を得るのが困難で
ある。ここで、従来型の超電導素子のオン状態での電圧
−電流特性を図２（ａ）に、従来型の超電導素子のオフ
状態での電圧−電流特性を図２（ｂ）に示す。デプレッ
ション型の素子の場合には、ゲ−ト電圧信号を加えない
状態で超電導臨界電流２０が流れ、低抵抗状態（従来型
素子のゲ−ト電圧信号零での抵抗曲線）２１にある〔図
２（ａ）〕。そして、ゲ−ト電圧信号を印加することに
より、超電導電流が減少すると共に、電圧状態での抵抗
値（従来型素子のゲ−ト電圧信号有限での抵抗曲線）２
２が増大する〔図２（ｂ）〕。ゲ−ト電圧信号の正負
は、常伝導層のキャリアの種類に依存する。オン状態と
オフ状態は、素子に超電導電流が流れる状態と、素子が
高抵抗になって負荷抵抗等に電流が転送された状態に対
応する。オフ状態で十分に電流を転送するためには、素
子抵抗をオン状態での値の１０倍、もしくはこれ以上に
する必要がある。しかるに抵抗値のゲ−ト電圧による変
化割合は、超電導電流の変化割合より小さい。エンハン
スメント型の素子の場合には、ゲ−ト電圧信号を加えな
い状態では超電導電流は流れず、高抵抗の電圧状態にあ
る。そして、ゲ−ト電圧信号を印加することにより、電
圧状態での抵抗値は減少して、超電導臨界電流が増大
し、超電導状態にスイッチする。この型の素子において
も、オフ状態で十分に電流を転送するためには素子抵抗
をオン状態での値の１０倍、もしくはこれ以上の値にす
る必要があることは、上記デプレッション型の素子の場
合と同様である。このように、素子のスイッチング動作
を実行するためには、素子抵抗値が１０倍以上変化する
だけのゲ−ト電圧を印加する必要がある。このことは、
近接効果を発揮させるに足る高いキャリア濃度を有し、
デバイ距離の短い超電導素子においては利得低下の原因
となる。In the element structure of the conventional superconducting element described above, the following problems or problems arise in producing an element exhibiting the performance as a superconducting element and having a sufficient control function and gain. There was a disability. That is, it is difficult to obtain a gain with the conventional superconducting element structure. Here, FIG. 2A shows the voltage-current characteristics of the conventional superconducting element in the on state, and FIG. 2B shows the voltage-current characteristics of the conventional superconducting element in the off state. In the case of a depletion type device, a superconducting critical current 20 flows without a gate voltage signal being applied, and the device is in a low resistance state (resistance curve at zero gate voltage signal of a conventional device) 21 [FIG. 2 (a)]. By applying the gate voltage signal, the superconducting current is reduced, and the resistance in the voltage state (resistance curve of the conventional device with a finite gate voltage signal) 2
2 increases [FIG. 2 (b)]. The sign of the gate voltage signal depends on the type of carriers in the normal conductive layer. The ON state and the OFF state correspond to a state in which a superconducting current flows through the element and a state in which the element has a high resistance and the current is transferred to a load resistance or the like. In order to sufficiently transfer the current in the off state, the element resistance needs to be 10 times or more the value in the on state. However, the rate of change of the resistance value due to the gate voltage is smaller than the rate of change of the superconducting current. In the case of the enhancement type element, the superconducting current does not flow when no gate voltage signal is applied, and the element is in a high resistance voltage state. By applying the gate voltage signal, the resistance value in the voltage state decreases, the superconducting critical current increases, and the superconducting state is switched. Also in this type of element, it is necessary to set the element resistance to ten times or more the value in the on state in order to sufficiently transfer the current in the off state. Same as in the case. As described above, in order to execute the switching operation of the element, it is necessary to apply a gate voltage that changes the element resistance value ten times or more. This means
Has a high carrier concentration enough to exhibit the proximity effect,
In a superconducting element having a short Debye distance, it causes a decrease in gain.
【０００４】本発明の課題は、上記した従来の超電導素
子よりも高い利得を有し、スイッチング回路に適合し、
回路構成および動作方式をより簡単化することが可能
で、より高速化された素子構造を有する超電導素子と、
その製造方法および動作方法を提供することにある。An object of the present invention is to have a higher gain than the above-described conventional superconducting element, to be suitable for a switching circuit,
A superconducting element having a faster element structure, which can further simplify the circuit configuration and operation method,
An object of the present invention is to provide a manufacturing method and an operation method.
【０００５】[0005]
【課題を解決するための手段】上記本発明の課題を解決
するために、本発明は特許請求の範囲に記載のような構
成とするものである。すなわち、本発明は請求項１に記
載のように、所定の基板上に、第１の絶縁層を２枚の超
電導電極を接続する超電導薄膜の結晶粒界によって構成
し、上記超電導薄膜は、バリウム（Ｂａ）、カリウム
（Ｋ）、ビスマス（Ｂｉ）からなる酸化物、もしくは該
酸化物を構成するＫの１部または全部が鉛（Ｐｂ）もし
くはルビジウム（Ｒｂ）によって置換された酸化物超電
導体からなり、上記第１の絶縁層を介して上記２枚の超
電導電極を接続して、超電導状態である零電圧状態と、
超電導ギャップ電圧以下の高抵抗電圧状態である電圧状
態の二つの安定な状態を持つヒステリシス特性を有する
トンネル接合を形成して、上記２枚の超電導電極間にト
ンネル電流および超電導電流が流れる構造となし、か
つ、上記２枚の超電導電極と上記第１の絶縁層を上記基
板上に平面状に配設し、ゲート絶縁膜である第２の絶縁
層を介して、上記第１の絶縁層に電界を印加するゲ−ト
電極を少なくとも配設した構造の超電導素子であって、
上記ゲ−ト電極に、ゲ−ト電圧を入力信号として印加す
ることにより、超電導電流の値と、電圧状態でのトンネ
ル抵抗値を制御して、上記零電圧状態と電圧状態間をス
イッチングする機能を備えた構造の超電導素子とするも
のである。また、本発明は請求項２に記載のように、請
求項１に記載の超電導素子において、下地基板材とし
て、結晶方位の異なる２枚の単結晶を貼り合わせたバイ
クリスタルを用い、第１の絶縁層を構成する超電導薄膜
の結晶粒界を、上記下地基板材の結晶粒界に沿って形成
するものである。また、本発明は請求項３に記載のよう
に、請求項１に記載の超電導素子において、下地基板材
として段差構造を有する単結晶を用い、第１の絶縁層を
構成する超電導薄膜の結晶粒界を、上記基板材の段差部
に沿って形成するものである。また、本発明は請求項４
に記載のように、請求項１または請求項３に記載の超電
導素子において、段差を複数個、並列に配列した構造の
下地基板材を用い、上記段差に沿った結晶粒界によって
構成される第１の絶縁層を複数個、直列に配列した構造
の超電導素子とするものである。また、本発明は請求項
５に記載のように、請求項１ないし請求項４のいずれか
１項に記載の超電導素子において、該超電導素子が零電
圧状態と電圧状態の二つの安定な状態を有し、入力ゲ−
ト電圧信号により超電導電流の値と電圧状態でのトンネ
ル抵抗値を制御することによって、上記零電圧状態と電
圧状態の二つの状態間をスイッチし、論理回路のゲ−ト
または記憶回路の記憶セル、もしくはデコ−ダ回路のゲ
−ト、さらにはアナログ、ディジタル変換器用論理要素
に適用し得る構造とするものである。また、本発明は請
求項６に記載のように、請求項１ないし請求項４のいず
れか１項に記載の超電導素子において、正負の両極性を
有する電圧パルスを入力信号としてトンネル抵抗および
超電導電流の値を制御する手段を備えた構造とするもの
である。また、本発明は請求項７に記載のように、請求
項１ないし請求項６のいずれか１項に記載の超電導素子
を製造する方法であって、結晶方位の異なる２枚の単結
晶を接合して形成した結晶粒界を有するバイクリスタル
の基板上、もしくは、少なくとも一つ以上の段差を並列
に配列した構造の単結晶基板上に、所定組成の酸化物超
電導体からなる超電導薄膜を成長させて、該基板の結晶
粒界に沿った２枚の超電導薄膜の結晶粒界からなる第１
の絶縁層、もしくは上記基板の段差部に沿って少なくと
も一つ以上の超電導薄膜の結晶粒界からなる第１の絶縁
層を形成する工程と、上記基板の裏面に、ゲート絶縁膜
である第２の絶縁層を形成し、上記第１の絶縁層に電界
を印加するためのゲ−ト電極を作製する工程を、少なく
とも含む超電導素子の製造方法とするものである。ま
た、本発明は請求項８に記載のように、請求項７に記載
の超電導素子の製造方法において、所定組成の酸化物超
電導体は、バリウム（Ｂａ）、カリウム（Ｋ）、ビスマ
ス（Ｂｉ）元素からなる酸化物、もしくは該酸化物を構
成するＫの一部または全部が鉛（Ｐｂ）もしくはルビジ
ウム（Ｒｂ）によって置換された酸化物超電導体とする
ものである。また、本発明は請求項９に記載のように、
請求項１ないし請求項６のいずれか１項に記載の超電導
素子の動作方法であって、上記超電導素子は、零電圧状
態と電圧状態での二つの安定な状態を有し、入力ゲ−ト
電圧信号を印加することにより、超電導電流の値と、電
圧状態でのトンネル抵抗の値を制御することによって、
上記零電圧状態と電圧状態の二つの状態間をスイッチせ
るようにしたものである。また、本発明は請求項１０に
記載のように、請求項９において、入力ゲ−ト電圧信号
は、正負の両極性を有する電圧パルスを入力信号として
用いるものである。Means for Solving the Problems In order to solve the above problems of the present invention, the present invention is configured as described in the claims. That is, according to the present invention, a first insulating layer is formed on a predetermined substrate by two or more sheets.
Constructed by grain boundaries of superconducting thin film connecting conductive poles
The superconducting thin film is made of barium (Ba), potassium
(K), an oxide composed of bismuth (Bi), or
If part or all of K constituting the oxide is lead (Pb),
Oxide superconductor substituted by rubidium (Rb)
A conductor, and the two superconductors are interposed via the first insulating layer.
By connecting the conductive poles, a zero voltage state which is a superconducting state,
A voltage state that is in a high resistance voltage state below the superconducting gap voltage
With hysteresis characteristics with two stable states
Forming a tunnel junction, the two superconducting electrodes between the tunnel current and a superconducting current flows structure and without, or
First , the two superconducting electrodes and the first insulating layer are disposed in a plane on the substrate, and an electric field is applied to the first insulating layer via a second insulating layer that is a gate insulating film. A superconducting element having a structure in which at least a gate electrode to be applied is provided,
A gate electrode, gate - - the gate to apply the G Voltage as an input signal
The value of the superconducting current and the tunneling
The resistance between the zero voltage state and the voltage state is controlled by controlling the
This is a superconducting element having a structure having an etching function . Further, the present invention is as claimed in claim 2, in the superconducting device of claim 1, as a base substrate material, using a bi-crystal by bonding two single crystal having a different crystal orientation, a first The crystal grain boundary of the superconducting thin film constituting the insulating layer is formed along the crystal grain boundary of the base substrate material. Further, the present invention is as claimed in claim 3, in the superconducting device of claim 1, a single crystal having a stepped structure as a base substrate material, the crystal grains of the superconducting thin film constituting the first insulating layer The field is formed along the step of the substrate material. In addition, the present invention relates to claim 4
In the superconducting element according to claim 1 or 3 , a plurality of steps are used, and an undersubstrate material having a structure arranged in parallel is used, and the superconducting element is constituted by crystal grain boundaries along the steps. A superconducting element having a structure in which a plurality of one insulating layers are arranged in series. Further, the present invention is defined by the claims.
According to a fifth aspect , in the superconducting element according to any one of the first to fourth aspects, the superconducting element has two stable states of a zero voltage state and a voltage state, and has an input gate.
By controlling the value of the superconducting current and the tunnel resistance value in the voltage state by the gate voltage signal, the two states of the zero voltage state and the voltage state are switched, and the gate of the logic circuit or the storage cell of the storage circuit is switched. Alternatively, the structure can be applied to the gate of a decoder circuit, and further to a logic element for an analog or digital converter. In addition, the present invention is 請
As described in claim 6 , in the superconducting element according to any one of claims 1 to 4 , the values of the tunnel resistance and the superconducting current are controlled by using a voltage pulse having both positive and negative polarities as an input signal. It is a structure provided with the means. According to a seventh aspect of the present invention, there is provided a method of manufacturing a superconducting element according to any one of the first to sixth aspects, wherein two single crystals having different crystal orientations are joined. A superconducting thin film made of an oxide superconductor having a predetermined composition is grown on a bicrystal substrate having crystal grain boundaries formed as described above, or on a single crystal substrate having a structure in which at least one or more steps are arranged in parallel. A first superconducting thin film having a grain boundary formed by two superconducting thin films along the grain boundary of the substrate.
Forming a first insulating layer composed of crystal grain boundaries of at least one superconducting thin film along the step of the substrate or the step of the substrate; and forming a second insulating layer serving as a gate insulating film on the back surface of the substrate. Forming a gate electrode for applying an electric field to the first insulating layer is a method for manufacturing a superconducting element. Further, the present invention is as claimed in claim 8, in the method for manufacturing a superconducting device according to claim 7, the oxide superconductor having a predetermined composition is barium (Ba), potassium (K), bismuth (Bi) An oxide composed of an element or an oxide superconductor in which part or all of K constituting the oxide is replaced with lead (Pb) or rubidium (Rb). Further, the present invention is as claimed in claim 9,
7. The method of operating a superconducting element according to claim 1 , wherein said superconducting element has two stable states, a zero voltage state and a voltage state, and has an input gate. By controlling the value of the superconducting current and the value of the tunnel resistance in the voltage state by applying a voltage signal,
It is designed to switch between the two states of the zero voltage state and the voltage state. Further, the present invention is as claimed in claim 10, in claim 9, an input gate - G Voltage signals is to use a voltage pulse having a positive and negative polarities as an input signal.
【０００６】[0006]
【作用】本発明の超電導素子の素子構造は、以下に示す
理由により、回路用スイッチング素子として用いるに十
分な利得を有し、かつ素子を動作させるために煩雑な回
路を用いる必要がなく、スイッチング素子として用いる
場合に特別な回路構成を必要としない効果がある。ここ
で、本発明の超電導素子の動作原理について、図３
（ａ）、（ｂ）を用いて説明する。超電導素子の電流通
電部は、２枚の超電導電極の間に絶縁層が挾まれた構造
である。この素子構造に対応して、流れる電流はトンネ
ル電流である。図に示すように、トンネル型のジョセフ
ソン接合と名付けられている素子と同様に、零（０）電
圧で超電導臨界電流３１が流れ、通電電流がバイアス電
流を越えると電圧状態（本発明の素子のゲート電圧信号
零での抵抗曲線）３２に遷移する。発生電圧は超電導電
極のギャップ電圧３３に相当する。通電電流を下げる
と、電圧値はギャップ電圧３３を維持し、電流のみが減
少する。さらに、通電電流を下げると、零電圧に復帰す
る限界電圧値（ゲート電圧信号零での零電圧復帰電圧）
３４に達し、ほぼ電圧値のみが減少して零電圧状態に戻
る〔図３（ａ）〕。このように、素子の電圧−電流特性
はヒステリシスを示す。すなわち、入力信号を印加しな
い場合の電圧−電流特性は、従来のジョセフソン接合と
ほとんど変わらない。ジョセフソン接合では磁場信号等
によって超電導電流の臨界値を変化させ、これによって
超電導状態から電圧状態にスイッチング動作を行わせる
が、磁場信号が印加されても電圧状態での常伝導電流の
電圧−電流特性は変化を受けない。本発明の超電導素子
をスイッチング素子として用いる場合、ゲ−ト電圧を入
力信号に用いる。ゲ−ト電圧信号が印加された場合は、
図３（ｂ）に示すように、超電導臨界電流３５が減少す
るとともに、電圧状態での抵抗値（本発明の素子のゲー
ト電圧信号有限での抵抗曲線）３６も全体的に増大す
る。本発明の超電導素子のスイッチング動作を、図４
（ａ）、（ｂ）、（ｃ）に示す。すなわち、図４（ａ）
に示すごとく、バイアス電流値４２を、超電導素子の超
電導臨界電流３１より低い値に設定する。図４（ｂ）に
示されるように、ゲ−ト電圧信号によって超電導臨界電
流３５が減少し、バイアス電流４２より低くなれば超電
導素子は電圧状態に遷移する。そして、超電導素子に並
列に負荷抵抗が接続された回路構成において、負荷抵抗
の値が超電導素子の抵抗より十分に低い場合、大部分の
電流は負荷抵抗に流れる。ゲ−ト電圧信号によって超電
導素子の電圧状態での抵抗値が増加することは、上記負
荷抵抗への電流の転送割合の増大に寄与している。した
がって、本発明の超電導素子において、超電導臨界電流
３１が、バイアス電流４２を越えて変化するだけのゲ−
ト電圧信号を印加するのみで、スイッチング動作を行
い、しかもバイアス電流の大部分が負荷抵抗に転送され
る。この理由は、本発明の超電導素子の電圧−電流特性
が非線形であり、ギャップ電圧以下で十分に高い抵抗値
を示し、かつヒステリシスを有するからである。この結
果、本発明の超電導素子は、スイッチング素子として用
いる場合の入力信号電圧に対する出力電圧の割合、すな
わち利得を得るのに有利な特性を有するものである。一
方、従来の超電導素子の場合、ゲ−ト電圧信号を印加し
て超電導臨界電流がバイアス電流を越えることにより超
電導素子は電圧状態に遷移するが、ヒステリシス特性を
有していないので、電圧値は零電圧近傍にあり、負荷抵
抗への電流の転送割合は僅少である。したがって、超電
導素子の電圧状態における抵抗値を、ゲ−ト電圧信号に
よって１０倍以上に増加させないかぎり、負荷抵抗にバ
イアス電流の大部分を転送することができない。従来の
超電導素子の超電導結合層には、常伝導材料が用いられ
ているのに対して、本発明にかかる超電導素子の超電導
結合層には絶縁材料が用いられる。キャリア濃度は、当
然のことながら本発明の超電導素子の超電導結合層の方
が低くなり、素子構造の観点からも本発明の超電導素子
は、従来の超電導素子より高い利得が得られる。このよ
うに、本発明の超電導素子は、相対的にわずかの信号電
圧でスイッチング動作を行うことができるので、キャリ
ア濃度の変化も、これに対応して相対的にわずかであ
る。したがって、従来の超電導素子と比較して高速のス
イッチング特性が得られる。このようなヒステリシス特
性を持った超電導素子は、トンネル接合構造を有するこ
とが望ましい。トンネル接合の絶縁層に電界を印加する
のであるから、素子は平面型の構造であることが必要と
なる。本発明の超電導素子のように、超電導薄膜の結晶
粒界によって絶縁層を形成する場合、絶縁層と２枚の超
電導電極が１枚の超電導薄膜から得られるので、平面型
の構造を容易に実現することができる。 また、２枚の
超電導電極を構成する超電導薄膜を、Ｂａ、Ｋ、Ｂｉの
酸化物、もしくはＫの１部または全部を、ＰｂまたはＲ
ｂ等によって置換した酸化物超電導体とすれば、上記２
枚の超電導薄膜の結晶粒界は絶縁性を有することにな
る。また、下地基板材に単結晶を用いた場合、上記酸化
物系の超電導薄膜はエピタキシャルに成長するので、超
電導薄膜の結晶粒界は、下地基板材の結晶粒界や段差部
で形成される。したがって、結晶方位の異なる２枚の単
結晶を貼り合わせたバイクリスタルや、あらかじめ段差
部を形成した単結晶を下地基板材として用いることによ
り超電導薄膜に結晶粒界、すなわち絶縁層を形成するこ
とができる。なお、段差構造の場合は、複数個の段差を
配列することにより、自動的に直列に接続された超電導
素子を得ることができ、電圧利得をいっそう向上させる
ことが可能となる。本発明の超電導素子は、ヒステリシ
スを有する電圧−電流特性を示すが、ジョセフソン接合
とは異なり、入力信号によって電圧状態になった場合
に、その入力信号を解除することにより零電圧状態に復
帰させることができる。この理由は、図４（ｃ）に示す
ごとく、入力信号を加えることにより、超電導素子の電
圧状態での抵抗値が増大するので、零電圧に復帰する限
界電圧値（ゲ−ト電圧信号有限での零電圧復帰電圧）４
４が減少して電圧状態が安定に存在する。入力信号を解
除すれば、限界電圧値（ゲ−ト電圧信号零での零電圧復
帰電圧）３４が増大して電圧状態での電圧値（負荷を接
続した場合の電圧状態）４３を上回り、超電導素子は自
動的に零電圧状態に復帰する。入力信号として超電導臨
界電流を低減するスイッチング電圧信号を解除するとき
に、同時に符号を反転した電圧信号、すなわち超電導臨
界電流を増大させる信号を入力することにより、超電導
素子の零電圧状態への復帰をより確実にし、かつ限界電
圧値を高める作用がある。本発明の超電導素子において
は、零電圧状態と電圧状態の二つの安定な状態を有する
ので、入力ゲ−ト電圧信号によって超電導電流の値と、
電圧状態での抵抗値を制御することによって、これら二
つの安定な状態間をスイッチさせることができ、論理回
路のゲ−ト、または記憶回路の記憶セル、もしくはデコ
−ダ回路のゲ−ト等、さらにはアナログ、ディジタル変
換器用論理要素等に有効に適用することができる。The element structure of the superconducting element according to the present invention has a gain sufficient for use as a circuit switching element for the following reason, and does not require the use of a complicated circuit for operating the element. When used as an element, there is an effect that a special circuit configuration is not required. Here, the operation principle of the superconducting element of the present invention will be described with reference to FIG.
This will be described with reference to (a) and (b). The current conducting portion of the superconducting element has a structure in which an insulating layer is sandwiched between two superconducting electrodes. The flowing current is a tunnel current corresponding to this element structure. As shown in the figure, similarly to a device named as a tunnel type Josephson junction, a superconducting critical current 31 flows at zero (0) voltage, and a voltage state (a device of the present invention) (Resistance curve at zero gate voltage signal). The generated voltage corresponds to the gap voltage 33 of the superconducting electrode. When the energizing current is reduced, the voltage value maintains the gap voltage 33, and only the current decreases. Furthermore, a limit voltage value (zero voltage return voltage at zero gate voltage signal) at which the current returns to zero voltage when the current is reduced
34, only the voltage value decreases and returns to the zero voltage state (FIG. 3A). Thus, the voltage-current characteristics of the device show hysteresis. That is, the voltage-current characteristics when no input signal is applied are almost the same as those of the conventional Josephson junction. In the Josephson junction, the critical value of the superconducting current is changed by a magnetic field signal or the like, and thereby the switching operation is performed from the superconducting state to the voltage state, but the voltage-current of the normal conduction current in the voltage state even when the magnetic field signal is applied. The characteristics do not change. When the superconducting element of the present invention is used as a switching element, a gate voltage is used for an input signal. When the gate voltage signal is applied,
As shown in FIG. 3B, as the superconducting critical current 35 decreases, the resistance value in a voltage state (the resistance curve of the device of the present invention with a finite gate voltage signal) 36 increases as a whole. FIG. 4 shows the switching operation of the superconducting element of the present invention.
(A), (b) and (c) are shown. That is, FIG.
, The bias current value 42 is set to a value lower than the superconducting critical current 31 of the superconducting element. As shown in FIG. 4 (b), the superconducting critical current 35 is reduced by the gate voltage signal, and if the critical current 35 becomes lower than the bias current 42, the superconducting element transitions to the voltage state. In a circuit configuration in which a load resistance is connected in parallel to the superconducting element, when the value of the load resistance is sufficiently lower than the resistance of the superconducting element, most of the current flows through the load resistance. The increase in the resistance value of the superconducting element in the voltage state due to the gate voltage signal contributes to an increase in the rate of current transfer to the load resistance. Therefore, in the superconducting device of the present invention, the superconducting critical current 31 is a gate which only changes beyond the bias current 42.
The switching operation is performed only by applying the reset voltage signal, and most of the bias current is transferred to the load resistance. The reason for this is that the voltage-current characteristics of the superconducting element of the present invention are nonlinear, exhibit a sufficiently high resistance value below the gap voltage, and have a hysteresis. As a result, the superconducting element of the present invention has a characteristic advantageous for obtaining a ratio of an output voltage to an input signal voltage when used as a switching element, that is, a gain. On the other hand, in the case of a conventional superconducting element, when the gate voltage signal is applied and the superconducting critical current exceeds the bias current, the superconducting element transits to a voltage state. However, since the superconducting element does not have hysteresis characteristics, the voltage value is It is near zero voltage and the transfer rate of current to the load resistor is negligible. Therefore, most of the bias current cannot be transferred to the load resistance unless the resistance value of the superconducting element in the voltage state is increased more than ten times by the gate voltage signal. While a normal conductive material is used for the superconducting coupling layer of the conventional superconducting element, an insulating material is used for the superconducting coupling layer of the superconducting element according to the present invention. Of course, the carrier concentration of the superconducting coupling layer of the superconducting element of the present invention is lower than that of the superconducting element of the present invention, and the superconducting element of the present invention can obtain a higher gain than the conventional superconducting element from the viewpoint of the element structure. As described above, since the superconducting element of the present invention can perform the switching operation with a relatively small signal voltage, the change in the carrier concentration is relatively small correspondingly. Therefore, high-speed switching characteristics can be obtained as compared with the conventional superconducting element. It is desirable that the superconducting element having such hysteresis characteristics has a tunnel junction structure. Since an electric field is applied to the insulating layer of the tunnel junction, the element needs to have a planar structure. When the insulating layer is formed by the crystal grain boundaries of the superconducting thin film as in the superconducting element of the present invention, the insulating layer and two superconducting electrodes can be obtained from one superconducting thin film, so that a planar structure can be easily realized. can do. Further, the superconducting thin film constituting the two superconducting electrodes is formed of Ba, K, Bi oxide, or part or all of K by Pb or Rb.
If the oxide superconductor is replaced by b or the like,
The grain boundaries of the superconducting thin films have insulating properties. When a single crystal is used for the base substrate material, the oxide-based superconducting thin film grows epitaxially, so that the crystal grain boundaries of the superconducting thin film are formed at the crystal grain boundaries of the base substrate material and at the steps. Therefore, a crystal grain boundary, that is, an insulating layer can be formed in a superconducting thin film by using a bicrystal in which two single crystals having different crystal orientations are bonded to each other or a single crystal in which a step is formed in advance as a base substrate material. it can. In the case of a step structure, by arranging a plurality of steps, a superconducting element automatically connected in series can be obtained, and the voltage gain can be further improved. The superconducting element of the present invention exhibits a voltage-current characteristic having hysteresis. However, unlike a Josephson junction, when a voltage state is caused by an input signal, the superconducting element returns to a zero voltage state by canceling the input signal. be able to. The reason for this is that, as shown in FIG. 4 (c), when the input signal is applied, the resistance value of the superconducting element in the voltage state increases, so that the limit voltage value which returns to zero voltage (the gate voltage signal is finite) Zero return voltage)
4 decreases and the voltage state exists stably. When the input signal is released, the limit voltage value (zero voltage return voltage at zero gate voltage signal) 34 increases and exceeds the voltage value in the voltage state (voltage state when a load is connected) 43, and the superconductivity is increased. The device automatically returns to the zero voltage state. When the switching voltage signal for reducing the superconducting critical current is released as an input signal, the voltage signal with the inverted sign at the same time, that is, the signal for increasing the superconducting critical current is input, thereby returning the superconducting element to the zero voltage state. This has the effect of making it more reliable and increasing the limit voltage value. Since the superconducting element of the present invention has two stable states, a zero voltage state and a voltage state, the value of the superconducting current is determined by the input gate voltage signal.
By controlling the resistance value in the voltage state, it is possible to switch between these two stable states, such as the gate of a logic circuit, the storage cell of a storage circuit, or the gate of a decoder circuit. The present invention can be effectively applied to logic elements for analog and digital converters.
【０００７】次に、本発明の超電導素子について請求項
別の効果について説明する。本発明は請求項１に記載の
ように、所定の基板上に、第１の絶縁層を介して２枚の
超電導電極を接続してトンネル接合を構成し、上記２枚
の超電導電極間にトンネル電流および超電導電流が流れ
る構造となし、上記２枚の超電導電極と第１の絶縁層を
上記基板上に平面状に配設し、ゲート絶縁膜である第２
の絶縁層を介して、上記第１の絶縁層に電界を印加する
ゲ−ト電極を少なくとも配設した構造の超電導素子であ
って、上記ゲ−ト電極に印加するゲ−ト電圧を入力信号
として、トンネル抵抗および超電導電流の値を制御する
手段を備えた超電導素子である。このような素子構造と
することにより、超電導臨界電流がバイアス電流を越え
て変化するだけのゲート電圧信号を印加するのみでスイ
ッチング動作を行うことができ、しかもバイアス電流の
大部分が負荷抵抗に転送される。これは、本発明の超電
導素子の電圧−電流特性が非線形であり、ギャップ電圧
以下で十分に高い抵抗値を示し、かつヒステリシスを有
するからであり、その結果、スイッチング素子として用
いる場合の入力信号電圧に対する出力電圧の割合、すな
わち利得を得るのに有利な特性を持っている。また、超
電導結合層には絶縁層を用いているので、従来の常伝導
材料を超電導結合層に用いた場合に比べキャリア濃度も
著しく低く、したがって素子構造の観点からも高い利得
が得られる。すなわち、相対的にわずかの信号電圧でス
イッチング動作を行うことができ、キャリア濃度の変化
も相対的にわずかであり、高速のスイッチング性能が得
られる効果がある。また、本発明は請求項１に記載のよ
うに、第１の絶縁層は、２枚の超電導電極を接続する超
電導薄膜の結晶粒界によって構成することにより、結晶
粒界を有する下地基板上に、１枚の超電導薄膜をエピタ
キシャル成長させるだけで、絶縁層と２枚の超電導電極
を同時に形成できる効果がある。また、本発明は請求項
１に記載のように、２枚の超電導電極を構成する超電導
薄膜は、バリウム（Ｂａ）、カリウム（Ｋ）、ビスマス
（Ｂｉ）からなる酸化物、もしくは該酸化物を構成する
Ｋの一部または全部が鉛（Ｐｂ）もしくはルビジウム
（Ｒｂ）によって置換された酸化物超電導体とすること
により、容易に、その結晶粒界を絶縁層とすることがで
き、高速のスイッチング性能を有する超電導素子を容易
に実現することができる。また、本発明は請求項２に記
載のように、請求項１に記載の超電導素子において、下
地基板材として、結晶方位の異なる２枚の単結晶を貼り
合わせたバイクリスタルを用い、第１の絶縁層を構成す
る超電導薄膜の結晶粒界を、上記下地基板材の結晶粒界
に沿って形成することにより、結晶粒界、すなわち絶縁
層により接合された２枚の超電導電極を同時に形成でき
る効果がある。また、本発明は請求項３に記載のよう
に、請求項１に記載の超電導素子において、下地基板材
として段差構造を有する単結晶を用い、第１の絶縁層を
構成する超電導薄膜の結晶粒界を、上記基板材の段差部
に沿って形成した超電導素子であって、段差部を設けた
基板上に超電導薄膜を成長させると、段差部に超電導薄
膜の結晶粒界、すなわち絶縁層が形成されるので、絶縁
層により接合された２枚の超電導電極を同時に形成でき
る効果がある。また、本発明は請求項４に記載のよう
に、請求項１または請求項３に記載の超電導素子におい
て、段差を複数個、並列に配列した構造の下地基板材を
用い、上記段差に沿った結晶粒界によって構成される第
１の絶縁層を複数個、直列に配列した超電導素子であっ
て、このような素子構造とすることにより、自動的に直
列に接続された超電導素子を容易に作製することが可能
となり、電圧利得を向上させる効果がある。また、本発
明は請求項５に記載のように、請求項１ないし請求項４
のいずれか１項に記載の超電導素子において、該超電導
素子が零電圧状態と電圧状態の二つの安定な状態を有
し、入力ゲ−ト電圧信号により超電導電流の値と電圧状
態でのトンネル抵抗値を制御することによって、上記零
電圧状態と電圧状態の二つの状態間を安定して高速でス
イッチさせることができるので、論理回路のゲ−トまた
は記憶回路の記憶セル、もしくはデコ−ダ回路のゲ−
ト、さらにはアナログ、ディジタル変換器用論理要素に
有効に適用できる効果がある。また、本発明は請求項６
に記載のように、請求項１ないし請求項４のいずれか１
項に記載の超電導素子において、正負の両極性を有する
電圧パルスを入力信号としてトンネル抵抗および超電導
電流の値を制御する手段を備えた超電導素子であって、
入力信号として超電導臨界電流を低減するスイッチング
電圧信号を解除するときに、同時に符号を反転した電圧
信号、すなわち超電導臨界電流を増大させる信号を入力
することにより、超電導素子の零電圧状態への復帰をよ
り確実にし、かつ限界電圧値を高める効果がある。ま
た、本発明は請求項７に記載のように、請求項１ないし
請求項６のいずれか１項に記載の超電導素子を製造する
方法であって、結晶方位の異なる２枚の単結晶を接合し
て形成した結晶粒界を有するバイクリスタルの基板上、
もしくは、少なくとも一つ以上の段差を並列に配列した
構造の単結晶基板上に、所定組成の酸化物超電導体から
なる超電導薄膜を成長させて、該基板の結晶粒界に沿っ
た２枚の超電導薄膜の結晶からなる第１の絶縁層、もし
くは上記基板の段差部に沿って少なくとも一つ以上の第
１の絶縁層を形成する工程と、上記基板の裏面に、ゲー
ト絶縁膜である第２の絶縁層を形成し、上記第１の絶縁
層に電界を印加するためのゲ−ト電極を作製する工程
を、少なくとも含む超電導素子の製造方法である。この
ような工程で超電導素子を製造することにより、基板上
に成長させる超電導薄膜に結晶粒界を形成しやすく、容
易に絶縁層により接合された２枚の超電導電極を同時に
形成できる効果がある。また、本発明は請求項８に記載
のように、請求項７に記載の超電導素子の製造方法にお
いて、所定組成の酸化物超電導体は、バリウム（Ｂ
ａ）、カリウム（Ｋ）、ビスマス（Ｂｉ）元素からなる
酸化物、もしくは該酸化物を構成するＫの一部または全
部が鉛（Ｐｂ）もしくはルビジウム（Ｒｂ）によって置
換された酸化物超電導体とすることにより、その結晶粒
界を確実に、高品質の絶縁層とすることができ、高い利
得を有し、スイッチング回路に適合し、回路構成、動作
方式をより簡素化した超電導素子を容易に実現すること
ができる。また、本発明は請求項９に記載のように、請
求項１ないし請求項６のいずれか１項に記載の超電導素
子の動作方法であって、上記超電導素子は、零電圧状態
と電圧状態での二つの安定な状態を有し、入力ゲ−ト電
圧信号を印加することにより、超電導電流の値と、電圧
状態でのトンネル抵抗の値を制御することによって、上
記零電圧状態と電圧状態の二つの安定な状態間をスイッ
チさせるだけでよく、スイッチング動作を行わせるため
のゲ−ト電圧信号の振幅が低下でき利得を向上させるこ
とができ、また電圧状態から零電圧状態に復帰させるた
めに、供給電流を交流にする必要もなく、スイッチング
回路を作製した場合の回路構成が極めて簡単になる。さ
らに、スイッチング動作を行わせるためのゲ−ト電圧信
号の振幅を低下することができるので、これに対応する
キャリア濃度の変化の割合が低いため、従来の超電導素
子よりもスイッチング速度を高速にすることができる。
また、本発明は請求項１０に記載のように、請求項９に
おいて、入力ゲ−ト電圧信号は、正負の両極性を有する
電圧パルスを入力信号として用いるので、超電導臨界電
流を増大させる信号を入力することになり、超電導素子
の零電圧状態への復帰をより確実にし、かつ限界電圧値
を高める効果がある。Next, the effects of the claims of the superconducting element of the present invention will be described. According to the present invention, a tunnel junction is formed by connecting two superconducting electrodes on a predetermined substrate via a first insulating layer, and forming a tunnel junction between the two superconducting electrodes. A structure in which a current and a superconducting current flow is provided. The two superconducting electrodes and the first insulating layer are disposed in a plane on the substrate, and a second gate insulating film is formed.
A superconducting element having at least a gate electrode for applying an electric field to said first insulating layer via said insulating layer, wherein a gate voltage applied to said gate electrode is input to an input signal. As a superconducting element having means for controlling the values of tunnel resistance and superconducting current. With such an element structure, the switching operation can be performed only by applying a gate voltage signal that changes the superconducting critical current beyond the bias current, and most of the bias current is transferred to the load resistance. Is done. This is because the voltage-current characteristics of the superconducting element of the present invention are non-linear, exhibit a sufficiently high resistance value below the gap voltage, and have hysteresis. As a result, the input signal voltage when used as a switching element , That is, characteristics that are advantageous for obtaining a gain. In addition, since an insulating layer is used for the superconducting coupling layer, the carrier concentration is significantly lower than when a conventional normal conductive material is used for the superconducting coupling layer, so that a high gain can be obtained from the viewpoint of the element structure. That is, the switching operation can be performed with a relatively small signal voltage, the change in the carrier concentration is relatively small, and there is an effect that high-speed switching performance can be obtained. Further, the present invention is as claimed in claim 1, the first insulating layer, by forming the grain boundaries of the superconducting thin film which connects the two superconducting electrodes, the base substrate having a crystal grain boundary Further, there is an effect that an insulating layer and two superconducting electrodes can be simultaneously formed only by epitaxially growing one superconducting thin film. Further, the present invention is defined by the claims.
As described in 1 , the superconducting thin film constituting the two superconducting electrodes is made of an oxide composed of barium (Ba), potassium (K), bismuth (Bi), or a part of K constituting the oxide or By using an oxide superconductor entirely replaced by lead (Pb) or rubidium (Rb), a crystal grain boundary can be easily formed as an insulating layer, and a superconducting element having high-speed switching performance can be easily manufactured. Can be realized. Further, the present invention is as claimed in claim 2, in the superconducting device of claim 1, as a base substrate material, using a bi-crystal by bonding two single crystal having a different crystal orientation, a first By forming the crystal grain boundaries of the superconducting thin film constituting the insulating layer along the crystal grain boundaries of the base substrate material, it is possible to simultaneously form the crystal grain boundaries, that is, two superconducting electrodes joined by the insulating layer. There is. Further, the present invention is as claimed in claim 3, in the superconducting device of claim 1, a single crystal having a stepped structure as a base substrate material, the crystal grains of the superconducting thin film constituting the first insulating layer A superconducting element in which the boundary is formed along the step of the substrate material, and when the superconducting thin film is grown on the substrate provided with the step, a crystal grain boundary of the superconducting thin film, that is, an insulating layer is formed on the step. Therefore, there is an effect that two superconducting electrodes joined by the insulating layer can be simultaneously formed. According to a fourth aspect of the present invention, there is provided a superconducting element according to the first or third aspect , wherein a plurality of steps are used, and a base substrate material having a structure arranged in parallel is used. A superconducting element in which a plurality of first insulating layers constituted by crystal grain boundaries are arranged in series, and by adopting such an element structure, a superconducting element automatically connected in series can be easily manufactured. This has the effect of improving the voltage gain. In addition, the present invention provides, as described in claim 5 , claims 1 to 4
5. The superconducting element according to claim 1, wherein said superconducting element has two stable states of a zero voltage state and a voltage state, and the value of superconducting current and the tunnel resistance in the voltage state are determined by an input gate voltage signal. By controlling the value, the two states of the zero voltage state and the voltage state can be stably switched at a high speed. Therefore, the gate of the logic circuit or the storage cell of the storage circuit, or the decoder circuit The game of
This has the effect that it can be effectively applied to logic elements for analog and digital converters. In addition, the present invention provides claim 6
As described in any one of claims 1 to 4 ,
In the superconducting element according to the item, a superconducting element comprising means for controlling the value of the tunnel resistance and superconducting current as a voltage pulse having both positive and negative polarities as an input signal,
When the switching voltage signal for reducing the superconducting critical current is released as an input signal, the voltage signal with the inverted sign at the same time, that is, the signal for increasing the superconducting critical current is input, thereby returning the superconducting element to the zero voltage state. This has the effect of increasing reliability and increasing the limit voltage value. According to a seventh aspect of the present invention, there is provided a method of manufacturing a superconducting element according to any one of the first to sixth aspects, wherein two single crystals having different crystal orientations are joined. On a bicrystal substrate with crystal grain boundaries formed by
Alternatively, a superconducting thin film made of an oxide superconductor having a predetermined composition is grown on a single crystal substrate having a structure in which at least one or more steps are arranged in parallel, and two superconducting layers along the crystal grain boundaries of the substrate are grown. Forming a first insulating layer made of a thin film crystal or at least one first insulating layer along a step portion of the substrate; and forming a second insulating film as a gate insulating film on the back surface of the substrate. A method for manufacturing a superconducting element, comprising at least a step of forming an insulating layer and forming a gate electrode for applying an electric field to the first insulating layer. By manufacturing a superconducting element in such a process, it is easy to form crystal grain boundaries in a superconducting thin film grown on a substrate, and there is an effect that two superconducting electrodes joined by an insulating layer can be easily formed at the same time. Further, the present invention is as claimed in claim 8, in the method for manufacturing a superconducting device according to claim 7, the oxide superconductor having a predetermined composition are barium (B
a) an oxide comprising potassium (K) and bismuth (Bi) elements, or an oxide superconductor in which part or all of K constituting the oxide is replaced by lead (Pb) or rubidium (Rb). By doing so, the crystal grain boundaries can be reliably formed as a high-quality insulating layer, and a superconducting element that has a high gain, is suitable for a switching circuit, and has a simplified circuit configuration and operation method can be easily manufactured. Can be realized. According to a ninth aspect of the present invention, there is provided a method for operating a superconducting element according to any one of the first to sixth aspects, wherein the superconducting element is operated in a zero voltage state and a voltage state. By controlling the value of the superconducting current and the value of the tunnel resistance in the voltage state by applying the input gate voltage signal, the above-mentioned zero voltage state and the voltage state can be controlled. It is only necessary to switch between two stable states, the amplitude of the gate voltage signal for performing the switching operation can be reduced, the gain can be improved, and in order to return from the voltage state to the zero voltage state. In addition, there is no need to supply an alternating current, and the circuit configuration when a switching circuit is manufactured is extremely simplified. Further, since the amplitude of the gate voltage signal for performing the switching operation can be reduced, the rate of change of the carrier concentration corresponding thereto is low, so that the switching speed is higher than that of the conventional superconducting element. be able to.
Further, the present invention is as claimed in claim 10, in claim 9, an input gate - G Voltage signal, because using a voltage pulse having a positive and negative polarities as an input signal, a signal to increase the superconducting critical current That is, there is an effect that the superconducting element returns to the zero voltage state more reliably and the limit voltage value is increased.
【０００８】[0008]
【実施例】以下に本発明の実施例を挙げ、図面を用いて
さらに詳細に説明する。 〈実施例１〉本発明の超電導素子を、図１（ａ）〜
（ｄ）に示す手順で作製する。図１（ａ）に示すよう
に、（１００）面方位を一致させ、面内で方位を３６度
ずらせて、２枚のチタン酸ストロンチウム単結晶を接合
し、この結晶粒界２を有するバイクリスタル単結晶を、
（１００）面方位で切断して、超電導素子用の基板１を
作製する。次に、基板１の裏面中央部３を化学研磨し
て、厚み１００ｎｍに加工し、基板１の表面は鏡面研磨
を施す〔図１（ｂ）〕。このように作製したチタン酸ス
トロンチウムのバイクリスタル基板１上に、Ｂａ−Ｋ−
Ｂｉ酸化物の焼結体をタ−ゲットとして、高周波マグネ
トロンスパッタリング法によってＢａ−Ｋ−Ｂｉ酸化物
薄膜を成長させ、該酸化物薄膜の結晶粒界、すなわちト
ンネル絶縁層５を有するＢａ−Ｋ−Ｂｉ酸化物薄膜を形
成する。この時の、成膜温度は約５００℃とし、膜厚は
２０ｎｍ前後とした。次に、Ｂａ−Ｋ−Ｂｉ酸化物薄膜
に、有機レジストを塗布し、光学的な露光法によって、
超電導素子の電極および配線パタ−ンを形成する。すな
わち、Ａｒガスを用いたイオンビ−ムエッチング法によ
り、レジストパタ−ンをＢａ−Ｋ−Ｂｉ酸化物薄膜に転
写し、ソース電極もしくはドレイン電極４、６を形成す
る〔図１（ｃ）〕。次に、ＡｕとＰｄの合金薄膜を真空
蒸着法によって形成し、有機レジストの塗布、光学的な
露光法およびＡｒガスを用いたイオンビ−ムエッチング
法を用いて、超電導素子に並列につながる抵抗素子（図
示せず）を形成する。この抵抗素子は負荷抵抗として用
いるものである。さらに、チタン酸ストロンチウム基板
の裏面にＡｕ膜を形成し、ゲ−ト電極膜７を作製する
〔図１（ｄ）〕。以上の工程により、本発明の超電導素
子が得られる。上記基板１の結晶粒界上に形成した超電
導素子において、負荷抵抗を接続しない場合は、図３
（ａ）に示されるように、ヒステリシスを有する電圧−
電流特性が得られるので、Ｂａ−Ｋ−Ｂｉ酸化物薄膜の
結晶粒界は絶縁層となっていることが明らかであり、発
生電圧は超電導電極のギャップ電圧３３に相当する。な
お、符号の３１は超電導臨界電流、３２は本発明の素子
のゲ−ト電圧信号零での抵抗曲線、３４はゲ−ト電圧信
号零での零電圧復帰電圧を示す。負のゲ−ト電圧を印加
した場合は、図３（ｂ）に示されるように、超電導臨界
電流３５が減少すると共に、電圧状態での抵抗値（本発
明の素子のゲ−ト電圧信号有限での抵抗曲線）３６が増
大する。零（０）電圧に復帰する限界電圧（ゲ−ト電圧
信号有限での零電圧復帰電圧）４４は低下する。逆に、
正のゲ−ト電圧を印加した場合は、超電導臨界電流３５
が増大するとともに、電圧状態での抵抗値３６は減少
し、零電圧に復帰する限界電圧４４は上昇する。なお、
３７はギャップ電圧を示す。負荷抵抗を接続して負のゲ
−ト電圧を印加した場合は、図４（ｂ）に示されるよう
に、超電導素子は電圧状態に遷移し、大部分の電流は負
荷抵抗に転送される。この時、超電導臨界電流３５がバ
イアス電流４２より低下したことを示している。なお、
３４はゲ−ト電圧信号零での零電圧復帰電圧、３６は本
発明の素子のゲ−ト電圧信号有限での抵抗曲線、４１は
負荷曲線、４３は負荷を接続した場合の電圧状態、４４
はゲ−ト電圧信号有限での零電圧復帰電圧を示す。ゲ−
ト電圧を零に戻した場合は、図４（ｃ）に示されるよう
に、超電導素子は零電圧状態に復帰する。ゲ−ト電圧を
正に反転させた場合、超電導素子は零電圧状態に復帰す
るが、この場合には、負荷抵抗を増加させて、より高い
出力電圧が得られる。これらの振舞は、超電導素子がス
イッチング素子として機能していることを示している。
なお、３１は超電導臨界電流、３２は本発明の素子のゲ
−ト電圧信号零での抵抗曲線、３４はゲ−ト電圧信号零
での零電圧復帰電圧、４３は負荷を接続した場合の電圧
状態を示す。また、超電導薄膜として、Ｂａ−Ｋ−Ｂｉ
酸化物に代えて、Ｋの一部または全部をＰｂあるいはＲ
ｂ等によって置換した酸化物超電導薄膜を用いた場合に
おいても、本実施例と同様の素子特性ならびにスイッチ
ング特性を得ることができた。〈実施例２〉本発明の超
電導素子を、図５（ａ）〜（ｄ）に示す手順で作製す
る。まず、（１００）面方位のチタン酸ストロンチウム
単結晶を超電導素子用基板１として用いる。この基板の
裏面中央部１２を化学研磨して、厚み１００ｎｍに加工
する〔図５（ａ）〕。次に、基板１の表面に鏡面研磨を
施し、基板表面の１部を有機レジスト膜で覆い、Ａｒガ
スを用いたイオンビームエッチングにより、基板１の表
面に段差１１を形成する〔図５（ｂ）〕。上記段差１１
を形成したチタン酸ストロンチウム基板１上に、Ｂａ−
Ｋ−Ｂｉ酸化物の焼結体をタ−ゲットとして、高周波マ
グネトロンスパッタリング法によりＢａ−Ｋ−Ｂｉ酸化
物薄膜を形成する。なお、成膜温度は約５００℃で、膜
厚は２０ｎｍ前後とした。ついで、上記Ｂａ−Ｋ−Ｂｉ
酸化物薄膜に有機レジストを塗布し、光学的な露光法に
よって超電導素子のソ−ス電極もしくはドレイン電極お
よび配線のレジストパタ−ンを形成し、Ａｒガスを用い
たイオンビ−ムエッチング法によりレジストパタ−ンを
Ｂａ−Ｋ−Ｂｉ酸化物薄膜に転写して、ソ−ス電極もし
くはドレイン電極１３、１４を形成すると共に、段差１
１の部分に形成された上記酸化物薄膜の結晶粒界、すな
わちトンネル絶縁層１５を形成する〔図５（ｃ）〕。次
に、ＡｕとＰｄの合金薄膜を真空蒸着法によって形成
し、有機レジストの塗布、光学的な露光法およびＡｒガ
スを用いたイオンビ−ムエッチング法により、超電導素
子に並列につながる抵抗素子（図示せず）を形成する。
この抵抗素子は、負荷抵抗として用いる。次に、チタン
酸ストロンチウム基板１の裏面に、Ａｕ膜等を形成して
ゲ−ト電極膜１６を作製する。以上の工程を経ることに
よって本発明の超電導素子が得られる。上記の工程で作
製した超電導素子は、負荷抵抗を接続しない場合は、実
施例１で示した図３（ａ）と同様のヒステリシスを有す
る電圧−電流特性が得られ、基板の段差１１部で形成さ
れた結晶粒界がトンネル絶縁層１５となっていることが
明らかである。なお、発生電圧はギャップ電圧に相当す
る。また、負のゲ−ト電圧を印加した場合は、図３
（ｂ）に示されるように、超電導臨界電流が減少すると
共に、電圧状態での抵抗値が増大し、零電圧に復帰する
限界電圧は低下する。逆に、正のゲ−ト電圧を印加した
場合は、超電導臨界電流が増大すると共に、電圧状態で
の抵抗値は減少し、零電圧に復帰する限界電圧は上昇す
る。負荷抵抗を接続して負のゲ−ト電圧を印加した場合
も、実施例１で示した図４（ｂ）と同様に、超電導素子
は電圧状態に遷移し、大部分の電流は負荷抵抗に転送さ
れ、このとき超電導臨界電流はバイアス電流より低下し
たことを示している。また、ゲ−ト電圧を零に戻した場
合は超電導素子は零電圧状態に復帰する。これらの振舞
は、超電導素子がスイッチング素子として機能している
ことを示している。電子線描画法を用いて、幅１ミクロ
ンの範囲で平行なラインパタ−ンを有機レジスト膜に形
成することにより複数個の段差を基板上に作製する。こ
の基板上に作製された超電導素子の発生電圧は、段差の
数に比例して増大する。したがって、段差の数に比例し
て電圧利得が増加することになる。これらの超電導素子
を用いて、論理回路のＡＮＤゲ−ト、ＯＲゲ−ト等を構
成した場合においても有効に動作し適用し得ることを確
認した。また、これらの超電導素子を用いて、記憶回路
用の記憶セルあるいはデコ−ダ回路のゲ−ト等を構成し
た場合においても有効に動作し適用できることを確認し
た。さらに、これらの超電導素子を用いて、アナログ、
ディジタル変換器用論理素子等を作製した場合において
も有効に動作し、これらに適用し得ることを確認してい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in more detail with reference to the drawings. <Example 1> A superconducting element of the present invention is shown in FIGS.
It is manufactured by the procedure shown in (d). As shown in FIG. 1A, two strontium titanate single crystals are joined by aligning the (100) plane orientation and shifting the orientation by 36 degrees in the plane to form a bicrystal having the crystal grain boundary 2. A single crystal,
The substrate 1 for a superconducting element is manufactured by cutting in the (100) plane orientation. Next, the center 3 of the back surface of the substrate 1 is chemically polished to a thickness of 100 nm, and the surface of the substrate 1 is mirror-polished (FIG. 1B). Ba-K- is formed on the strontium titanate bicrystal substrate 1 thus manufactured.
Using a sintered body of Bi oxide as a target, a Ba-K-Bi oxide thin film is grown by a high-frequency magnetron sputtering method, and a crystal grain boundary of the oxide thin film, that is, a Ba-K-B thin film having a tunnel insulating layer 5 is formed. A Bi oxide thin film is formed. At this time, the film formation temperature was about 500 ° C., and the film thickness was about 20 nm. Next, an organic resist is applied to the Ba-K-Bi oxide thin film, and by an optical exposure method,
An electrode and a wiring pattern of the superconducting element are formed. That is, the resist pattern is transferred to the Ba-K-Bi oxide thin film by the ion beam etching method using Ar gas to form the source or drain electrodes 4 and 6 (FIG. 1C). Next, a resistive element connected in parallel to the superconducting element is formed by forming an alloy thin film of Au and Pd by a vacuum evaporation method, applying an organic resist, using an optical exposure method, and an ion beam etching method using Ar gas. (Not shown). This resistance element is used as a load resistance. Further, an Au film is formed on the back surface of the strontium titanate substrate to form a gate electrode film 7 (FIG. 1D). Through the above steps, the superconducting element of the present invention is obtained. In the case where the load resistance is not connected to the superconducting element formed on the crystal grain boundary of the substrate 1, FIG.
As shown in (a), a voltage having hysteresis-
Since current characteristics are obtained, it is clear that the crystal grain boundary of the Ba-K-Bi oxide thin film is an insulating layer, and the generated voltage corresponds to the gap voltage 33 of the superconducting electrode. Reference numeral 31 indicates a superconducting critical current, 32 indicates a resistance curve of the device of the present invention at a gate voltage signal of zero, and 34 indicates a zero voltage return voltage at a gate voltage signal of zero. When a negative gate voltage is applied, as shown in FIG. 3 (b), the superconducting critical current 35 decreases and the resistance in the voltage state (the gate voltage signal of the device of the present invention is finite). Resistance curve 36) increases. The limit voltage (zero voltage return voltage with a finite gate voltage signal) 44 that returns to zero (0) voltage decreases. vice versa,
When a positive gate voltage is applied, the superconducting critical current 35
Increases, the resistance 36 in the voltage state decreases, and the limit voltage 44 that returns to zero voltage increases. In addition,
37 indicates a gap voltage. When a negative gate voltage is applied by connecting a load resistor, the superconducting element transitions to a voltage state as shown in FIG. 4B, and most of the current is transferred to the load resistor. At this time, the superconducting critical current 35 is lower than the bias current 42. In addition,
Numeral 34 denotes a zero voltage return voltage at a gate voltage signal of zero, 36 denotes a resistance curve of the device of the present invention with a finite gate voltage signal, 41 denotes a load curve, 43 denotes a voltage state when a load is connected, 44
Indicates a zero voltage return voltage at a finite gate voltage signal. Gay
When the reset voltage is returned to zero, the superconducting element returns to the zero voltage state as shown in FIG. When the gate voltage is inverted positively, the superconducting element returns to the zero voltage state. In this case, the load resistance is increased and a higher output voltage can be obtained. These behaviors indicate that the superconducting element functions as a switching element.
31 is a superconducting critical current, 32 is a resistance curve of the device of the present invention at a gate voltage signal of zero, 34 is a zero voltage return voltage at a gate voltage signal of zero, and 43 is a voltage when a load is connected. Indicates the status. Further, as a superconducting thin film, Ba-K-Bi
Instead of the oxide, part or all of K may be Pb or R
Even when the oxide superconducting thin film substituted by b or the like was used, the same device characteristics and switching characteristics as those of this example could be obtained. <Example 2> A superconducting element of the present invention is manufactured according to the procedure shown in FIGS. First, a strontium titanate single crystal having a (100) plane orientation is used as the substrate 1 for a superconducting element. The central portion 12 on the back surface of this substrate is chemically polished to a thickness of 100 nm (FIG. 5A). Next, the surface of the substrate 1 is mirror-polished, a portion of the substrate surface is covered with an organic resist film, and a step 11 is formed on the surface of the substrate 1 by ion beam etching using Ar gas [FIG. )]. The step 11
Is formed on the strontium titanate substrate 1 on which
Using a sintered body of K-Bi oxide as a target, a Ba-K-Bi oxide thin film is formed by a high-frequency magnetron sputtering method. The film formation temperature was about 500 ° C. and the film thickness was about 20 nm. Then, the above Ba-K-Bi
An organic resist is applied to the oxide thin film, a resist pattern for a source electrode or a drain electrode of the superconducting element and a wiring are formed by an optical exposure method, and the resist pattern is formed by an ion beam etching method using Ar gas. Is transferred to a Ba-K-Bi oxide thin film to form a source electrode or a drain electrode 13 and 14, and a step 1 is formed.
A crystal grain boundary of the oxide thin film formed in the portion 1 is formed, that is, a tunnel insulating layer 15 is formed (FIG. 5C). Next, an alloy thin film of Au and Pd is formed by a vacuum evaporation method, and a resistive element connected in parallel to the superconducting element by applying an organic resist, optically exposing, and ion beam etching using Ar gas (see FIG. (Not shown).
This resistance element is used as a load resistance. Next, an Au film or the like is formed on the back surface of the strontium titanate substrate 1 to form a gate electrode film 16. Through the above steps, the superconducting element of the present invention is obtained. When a load resistance is not connected, the superconducting element manufactured in the above-described process can obtain a voltage-current characteristic having the same hysteresis as that shown in FIG. It is clear that the crystal grain boundary thus formed is the tunnel insulating layer 15. Note that the generated voltage corresponds to the gap voltage. In addition, when a negative gate voltage is applied, FIG.
As shown in (b), as the superconducting critical current decreases, the resistance value in the voltage state increases, and the limit voltage at which the voltage returns to zero voltage decreases. Conversely, when a positive gate voltage is applied, the superconducting critical current increases, the resistance in the voltage state decreases, and the limit voltage at which the voltage returns to zero increases. When a negative gate voltage is applied by connecting a load resistor, the superconducting element transitions to the voltage state as in FIG. 4B shown in the first embodiment, and most of the current flows to the load resistor. Transferred, indicating that the superconducting critical current has dropped below the bias current. When the gate voltage is returned to zero, the superconducting element returns to the zero voltage state. These behaviors indicate that the superconducting element functions as a switching element. A plurality of steps are formed on a substrate by forming parallel line patterns within a width of 1 micron on an organic resist film using an electron beam lithography method. The generated voltage of the superconducting element manufactured on this substrate increases in proportion to the number of steps. Therefore, the voltage gain increases in proportion to the number of steps. It has been confirmed that these superconducting elements can be effectively operated and applied even when an AND gate or an OR gate of a logic circuit is formed. It was also confirmed that these superconducting elements can be effectively operated and applied to the case where a storage cell for a storage circuit or a gate of a decoder circuit is constructed. Furthermore, using these superconducting elements, analog,
It operates effectively even when a logic element for a digital converter or the like is manufactured, and has been confirmed to be applicable to these.
【０００９】[0009]
【発明の効果】以上詳細に説明したごとく、本発明の超
電導素子は、以下に示す効果がある。 （１）スイッチング動作を行わせるためのゲ−ト電圧信
号の振幅が低下でき、利得を向上させることができる。 （２）また、スイッチング動作を行わせるためのゲ−ト
電圧信号の振幅が低下でき、これに対応するキャリア濃
度の変化の割合が低いため、従来の超電導素子よりスイ
ッチング速度が高速となる。 （３）さらに、電圧状態から零電圧状態に復帰させるた
めに、供給電流を交流にする必要がなく、スイッチング
回路を作製した場合の回路構成を簡略化することが可能
で、低消費電力性能を有する３端子型超電導素子を容易
に実現することができる。As described in detail above, the superconducting element of the present invention has the following effects. (1) The amplitude of the gate voltage signal for performing the switching operation can be reduced, and the gain can be improved. (2) Further, the amplitude of the gate voltage signal for performing the switching operation can be reduced, and the rate of change of the carrier concentration corresponding thereto is low, so that the switching speed is higher than that of the conventional superconducting element. (3) Further, in order to return from the voltage state to the zero voltage state, there is no need to change the supply current to AC, so that the circuit configuration when a switching circuit is manufactured can be simplified, and low power consumption performance can be achieved. It is possible to easily realize a three-terminal type superconducting element having the same.
【図１】本発明の実施例１で例示した超電導素子の作製
過程を示す工程図。FIG. 1 is a process chart showing a manufacturing process of a superconducting element exemplified in Example 1 of the present invention.
【図２】従来の超電導素子の電圧−電流特性を示すグラ
フ。FIG. 2 is a graph showing voltage-current characteristics of a conventional superconducting element.
【図３】本発明の実施例１および２で例示した超電導素
子の電圧−電流特性を示すグラフ。FIG. 3 is a graph showing voltage-current characteristics of the superconducting elements exemplified in Examples 1 and 2 of the present invention.
【図４】本発明の実施例１および２で例示した超電導素
子の負荷抵抗を接続した場合の電圧−電流特性を示すグ
ラフ。FIG. 4 is a graph showing voltage-current characteristics when a load resistance of the superconducting element exemplified in the first and second embodiments of the present invention is connected.
【図５】本発明の実施例２で例示した超電導素子の作製
過程を示す工程図。FIG. 5 is a process chart showing a manufacturing process of the superconducting element exemplified in Embodiment 2 of the present invention.
１…基板 ２…結晶粒界 ３…ゲ−ト絶縁層 ４…ソ−ス電極もしくはドレイン電極 ５…トンネル絶縁層 ６…ソ−ス電極もしくはドレイン電極 ７…ゲ−ト電極膜 １１…段差 １２…ゲ−ト絶縁層 １３…ソ−ス電極もしくはドレイン電極 １４…ソ−ス電極もしくはドレイン電極 １５…トンネル絶縁層 １６…ゲ−ト電極膜 ２０…超電導臨界電流 ２１…従来型素子のゲ−ト電圧信号零での抵抗曲線 ２２…従来型素子のゲ−ト電圧信号有限での抵抗曲線 ３１…超電導臨界電流 ３２…本発明の素子のゲ−ト電圧信号零での抵抗曲線 ３３…ギャップ電圧 ３４…ゲ−ト電圧信号零での零電圧復帰電圧 ３５…超電導臨界電流 ３６…本発明の素子のゲ−ト電圧信号有限での抵抗曲線 ３７…ギャップ電圧 ４１…負荷曲線 ４２…バイアス電流 ４３…負荷を接続した場合の電圧状態 ４４…ゲ−ト電圧信号有限での零電圧復帰電圧 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Crystal grain boundary 3 ... Gate insulating layer 4 ... Source electrode or drain electrode 5 ... Tunnel insulating layer 6 ... Source electrode or drain electrode 7 ... Gate electrode film 11 ... Step 12 Gate insulating layer 13 ... Source electrode or drain electrode 14 ... Source electrode or drain electrode 15 ... Tunnel insulating layer 16 ... Gate electrode film 20 ... Superconducting critical current 21 ... Gate voltage of conventional element Resistance curve at zero signal 22 ... Resistance curve at finite gate voltage signal of conventional device 31 ... Superconducting critical current 32 ... Resistance curve at zero gate voltage signal of device of the present invention 33 ... Gap voltage 34 ... Zero voltage return voltage at zero gate voltage signal 35 Superconducting critical current 36 Resistance resistance of device of the present invention at finite gate voltage signal 37 Gap voltage 41 Load curve 42 Bias current 43 Load Contact Voltage state in case of continuing 44 ... Reset voltage to zero voltage with finite gate voltage signal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 樺沢 宇紀 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所 中央研究所内 (72)発明者 長谷川 晴弘 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所 中央研究所内 (72)発明者 ▲高▼木 一正 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所 中央研究所内 (56)参考文献 特開 平３−178173（ＪＰ，Ａ) 特開 平６−132577（ＪＰ，Ａ) 特開 平２−230778（ＪＰ，Ａ) 特開 平８−153908（ＪＰ，Ａ) 特開 平４−84469（ＪＰ，Ａ) 特開 昭62−273782（ＪＰ，Ａ) 信学技報，ＳＣＥ94−10，ＭＷ94−10 （1994−04），ｐｐ．59−63 ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ ＡＰＰＬＩＥＤ ＳＵＰＥＲＣ ＯＮＤＵＣＴＩＶＩＴＹ，Ｖｏｌ．３, Ｎｏ．１，ＭＡＲＣＨ 19 93，ＰＰ, 2925−2928 Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．63 （５），２ Ａｕｇｕｓｔ 1993，ｐ ｐ．684−686 ＮＡＴＵＲＥ，Ｖｏｌ．332 ２Ｒ ＡＰＲＩＬ 1988，ｐｐ．814−816 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 39/22 H01L 39/24 H01L 39/00 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Uki Kabazawa 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory (72) Inventor Takamasa Kazuma Ki 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (56) References JP-A-3-178173 (JP, A) JP-A-6 JP-A-132577 (JP, A) JP-A-2-230778 (JP, A) JP-A-8-153908 (JP, A) JP-A-4-84469 (JP, A) JP-A-62-273782 (JP, A) ) IEICE Technical Report, SCE94-10, MW94-10 (1994-04), pp. 59-63 IEEE TRANSACTIONS ON APPLIED SUPERC ONDUCTIVITY, Vol. 3, No. 1, MARCH 1993, PP, 2925-2928 Appl. Phys. Lett. 63 (5), 2 August 1993, p. 684-686 NATURE, Vol. 332 2R APRIL 1988, pp. 814-816 (58) Fields investigated (Int.Cl. 7 , DB name) H01L 39/22 H01L 39/24 H01L 39/00
Claims (10)
電導電極を接続する超電導薄膜の結晶粒界によって構成
し、上記超電導薄膜は、バリウム（Ｂａ）、カリウム
（Ｋ）、ビスマス（Ｂｉ）からなる酸化物、もしくは該
酸化物を構成するＫの１部または全部が鉛（Ｐｂ）もし
くはルビジウム（Ｒｂ）によって置換された酸化物超電
導体からなり、上記第１の絶縁層を介して上記２枚の超
電導電極を接続して、超電導状態において零電圧状態と
所定の臨界電流とを有するとともに、超電導ギャップ電
圧以下の高抵抗電圧状態である電圧状態の二つの安定な
状態を持つヒステリシス特性を有するトンネル接合を形
成して、上記２枚の超電導電極間にトンネル電流および
超電導電流が流れる構造となし、かつ、上記２枚の超電
導電極と上記第１の絶縁層を上記基板上に平面状に配設
し、ゲート絶縁膜である第２の絶縁層を介して、上記第
１の絶縁層に電界を印加するゲ−ト電極を少なくとも配
設した構造の超電導素子であって、上記ゲ−ト電極に、
前記臨界電流より小さい超電流電流が流れるゲ−ト電圧
を入力信号として印加することにより、超電導電流の値
と、電圧状態でのトンネル抵抗値を制御して、上記零電
圧状態と電圧状態間をスイッチングする機能を備えたこ
とを特徴とする超電導素子。A first insulating layer formed on a predetermined substrate by a crystal grain boundary of a superconducting thin film connecting two superconducting electrodes, wherein the superconducting thin film is made of barium (Ba), potassium (K), The first insulating layer is made of an oxide made of bismuth (Bi) or an oxide superconductor in which part or all of K constituting the oxide is substituted with lead (Pb) or rubidium (Rb). The above two superconducting electrodes are connected through a zero voltage state in the superconducting state .
A tunnel junction having a predetermined critical current and a hysteresis characteristic having two stable states of a voltage state that is a high resistance voltage state equal to or lower than the superconducting gap voltage is formed, and a tunnel junction is formed between the two superconducting electrodes. A structure in which a current and a superconducting current flow are provided, and the two superconducting electrodes and the first insulating layer are disposed in a plane on the substrate, and are disposed via a second insulating layer serving as a gate insulating film. A superconducting element having at least a gate electrode for applying an electric field to the first insulating layer, wherein the gate electrode comprises:
By applying a gate voltage at which a supercurrent smaller than the critical current flows as an input signal, the value of the superconducting current and the tunnel resistance value in the voltage state are controlled to switch between the zero voltage state and the voltage state. A superconducting element having a switching function.
地基板材として、結晶方位の異なる２枚の単結晶を貼り
合わせたバイクリスタルを用い、第１の絶縁層を構成す
る超電導薄膜の結晶粒界を、上記下地基板材の結晶粒界
に沿って形成してなることを特徴とする超電導素子。2. The superconducting element according to claim 1, wherein a bicrystal in which two single crystals having different crystal orientations are bonded is used as a base substrate material, and a crystal of a superconducting thin film constituting a first insulating layer is provided. A superconducting element, wherein a grain boundary is formed along a crystal grain boundary of the base substrate material.
地基板材として段差構造を有する単結晶を用い、第１の
絶縁層を構成する超電導薄膜の結晶粒界を、上記基板材
の段差部に沿って形成してなることを特徴とする超電導
素子。3. A superconducting device according to claim 1, wherein a single crystal having a step structure is used as a base substrate material, and a crystal grain boundary of a superconducting thin film constituting a first insulating layer is formed on a step portion of said substrate material. A superconducting element characterized by being formed along.
子において、段差を複数個、並列に配列した構造の下地
基板材を用い、上記段差に沿った結晶粒界によって構成
される第１の絶縁層を複数個、直列に配列してなること
を特徴とする超電導素子。4. A superconducting element according to claim 1, wherein the base substrate material has a structure in which a plurality of steps are arranged in parallel, and the first is constituted by crystal grain boundaries along the steps. A superconducting element characterized in that a plurality of insulating layers are arranged in series.
記載の超電導素子において、該超電導素子が零電圧状態
と電圧状態の二つの安定な状態を有し、入力ゲ−ト電圧
信号により超電導電流の値と電圧状態でのトンネル抵抗
値を制御することによって、上記零電圧状態と電圧状態
の二つの状態間をスイッチし、論理回路のゲ−トまたは
記憶回路の記憶セル、もしくはデコ−ダ回路のゲ−ト、
さらにはアナログ、ディジタル変換器用論理要素に適用
してなることを特徴とする超電導素子。5. A superconducting element according to claim 1, wherein said superconducting element has two stable states, a zero voltage state and a voltage state, and an input gate voltage signal. By controlling the value of the superconducting current and the tunnel resistance value in the voltage state, the two states of the zero voltage state and the voltage state are switched, and the gate of the logic circuit or the storage cell of the storage circuit or the decoupling state is controlled. The gate of the damper circuit,
Furthermore, a superconducting element characterized by being applied to a logic element for an analog / digital converter.
記載の超電導素子において、正負の両極性を有する電圧
パルスを入力信号としてトンネル抵抗および超電導電流
の値を制御する手段を備えたことを特徴とする超電導素
子。6. A superconducting element according to claim 1, further comprising means for controlling a value of a tunnel resistance and a superconducting current by using a voltage pulse having both positive and negative polarities as an input signal. A superconducting element characterized by the above-mentioned.
記載の超電導素子を製造する方法であって、 結晶方位の異なる２枚の単結晶を接合して形成した結晶
粒界を有するバイクリスタルの基板上、もしくは、少な
くとも一つ以上の段差を並列に配列した構造の単結晶基
板上に、所定組成の酸化物超電導体からなる超電導薄膜
を成長させて、該基板の結晶粒界に沿った２枚の超電導
薄膜の結晶粒界からなる第１の絶縁層、もしくは上記基
板の段差部に沿って少なくとも一つ以上の第１の絶縁層
を形成する工程と、 上記基板の裏面に、ゲート絶縁膜である第２の絶縁層を
形成し、上記第１の絶縁層に電界を印加するためのゲ−
ト電極を作製する工程を、少なくとも含むことを特徴と
する超電導素子の製造方法。7. A method for manufacturing a superconducting element according to claim 1, wherein said method has a crystal grain boundary formed by joining two single crystals having different crystal orientations. A superconducting thin film made of an oxide superconductor having a predetermined composition is grown on a bicrystal substrate or on a single crystal substrate having a structure in which at least one or more steps are arranged in parallel, and a crystal grain boundary of the substrate is formed. Forming at least one first insulating layer along a first insulating layer formed of crystal grain boundaries of two superconducting thin films along the step or the step portion of the substrate; Forming a second insulating layer, which is a gate insulating film, and a gate for applying an electric field to the first insulating layer;
A method for manufacturing a superconducting element, comprising at least a step of manufacturing a contact electrode.
おいて、所定組成の酸化物超電導体は、バリウム（Ｂ
ａ）、カリウム（Ｋ）、ビスマス（Ｂｉ）元素からなる
酸化物、もしくは該酸化物を構成するＫの一部または全
部が鉛（Ｐｂ）もしくはルビジウム（Ｒｂ）によって置
換された酸化物超電導体であることを特徴とする超電導
素子の製造方法。8. The method for manufacturing a superconducting element according to claim 7, wherein the oxide superconductor having a predetermined composition is made of barium (B
a) an oxide composed of potassium (K) or bismuth (Bi), or an oxide superconductor in which part or all of K constituting the oxide is replaced by lead (Pb) or rubidium (Rb). A method for manufacturing a superconducting element, comprising:
記載の超電導素子の動作方法であって、上記超電導素子
は、零電圧状態と電圧状態での二つの安定な状態を有
し、入力ゲ−ト電圧信号を印加することにより、超電導
電流の値と、電圧状態でのトンネル抵抗の値を制御する
ことによって、上記零電圧状態と電圧状態の二つの状態
間をスイッチさせることを特徴とする超電導素子の動作
方法。9. A method for operating a superconducting element according to claim 1, wherein said superconducting element has two stable states in a zero voltage state and a voltage state. Controlling the value of the superconducting current and the value of the tunnel resistance in the voltage state by applying an input gate voltage signal to switch between the two states of the zero voltage state and the voltage state. Characteristic method of operating a superconducting element.
は、正負の両極性を有する電圧パルスを入力信号として
用いることを特徴とする超電導素子の動作方法。10. A method of operating a superconducting element according to claim 9, wherein the input gate voltage signal uses a voltage pulse having both positive and negative polarities as an input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7134886A JP3026482B2 (en) | 1995-06-01 | 1995-06-01 | Superconducting element, method of manufacturing and operating method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7134886A JP3026482B2 (en) | 1995-06-01 | 1995-06-01 | Superconducting element, method of manufacturing and operating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08330641A JPH08330641A (en) | 1996-12-13 |
| JP3026482B2 true JP3026482B2 (en) | 2000-03-27 |
Family
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669107B2 (en) * | 1986-02-15 | 1994-08-31 | 日本電信電話株式会社 | JO Josephson junction element and its manufacturing method |
| JPH0763100B2 (en) * | 1986-05-21 | 1995-07-05 | 日本電信電話株式会社 | JO Josephson junction element and its manufacturing method |
| JPH0284469A (en) * | 1988-06-10 | 1990-03-26 | Kansai Paint Co Ltd | Cationic electrodeposition coating |
| JPH02114681A (en) * | 1988-10-25 | 1990-04-26 | Seiko Epson Corp | Field effect josephson transistor |
| JPH0484469A (en) * | 1990-07-27 | 1992-03-17 | Riken Corp | Three-terminal device |
-
1995
- 1995-06-01 JP JP7134886A patent/JP3026482B2/en not_active Expired - Fee Related
Non-Patent Citations (4)
| Title |
|---|
| Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．６３（５），２ Ａｕｇｕｓｔ １９９３，ｐｐ．６８４−６８６ |
| ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ ＡＰＰＬＩＥＤ ＳＵＰＥＲＣＯＮＤＵＣＴＩＶＩＴＹ，Ｖｏｌ．３，Ｎｏ．１，ＭＡＲＣＨ １９ ９３，ＰＰ，２９２５−２９２８ |
| ＮＡＴＵＲＥ，Ｖｏｌ．３３２ ２Ｒ ＡＰＲＩＬ １９８８，ｐｐ．８１４−８１６ |
| 信学技報，ＳＣＥ９４−１０，ＭＷ９４−１０（１９９４−０４），ｐｐ．５９−６３ |
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| Publication number | Publication date |
|---|---|
| JPH08330641A (en) | 1996-12-13 |
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