JPH08236651A - Package of semiconductor element - Google Patents

Package of semiconductor element

Info

Publication number
JPH08236651A
JPH08236651A JP7035004A JP3500495A JPH08236651A JP H08236651 A JPH08236651 A JP H08236651A JP 7035004 A JP7035004 A JP 7035004A JP 3500495 A JP3500495 A JP 3500495A JP H08236651 A JPH08236651 A JP H08236651A
Authority
JP
Japan
Prior art keywords
semiconductor element
package
lid
electrode
housing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7035004A
Other languages
Japanese (ja)
Inventor
Sadakatsu Yoshida
定功 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7035004A priority Critical patent/JPH08236651A/en
Publication of JPH08236651A publication Critical patent/JPH08236651A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE: To obtain a package of semiconductor element in which the semicon ductor element can be operated normally and stably for long term. CONSTITUTION: In a package where a semiconductor element 3 is received airtightly in the inner space of a container 4 comprising an insulating basic body 1 and a cover body 2, a capacitive element A is fixed to a region opposing the space for containing the semiconductor element 3 while being coated with a protective film B made of a material scarcely emitting α-rays.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関し、より詳細には
内部に収容する半導体素子への電源ノイズの悪影響を有
効に防止するようになした半導体素子収納用パッケージ
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element accommodating package for accommodating semiconductor elements, and more particularly to a semiconductor for effectively preventing adverse effects of power source noise on semiconductor elements accommodated inside. The present invention relates to an element storage package.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは一般に酸化アルミニウム質焼
結体等の電気絶縁材料から成り、上面に半導体素子を収
容するための凹部及び該凹部周辺から外周部にかけて導
出するタングステン、モリブデン、マンガン等の高融点
金属粉末から成るメタライズ配線層を有する絶縁基体
と、半導体素子の各電極を外部電気回路に接続するため
に前記メタライズ配線層に銀ロウ等のロウ材を介し取着
された外部リード端子と、蓋体とから構成されており、
絶縁基体の凹部底面に半導体素子をガラス、樹脂、ロウ
材等の接着剤を介して接着固定するとともに半導体素子
の各電極をメタライズ配線層にボンディングワイヤを介
して電気的に接続し、しかる後、絶縁基体の上面に蓋体
をガラス、樹脂、ロウ材等の封止材を介して接合させ、
絶縁基体と蓋体とから成る容器内部に半導体素子を気密
に収容することによって製品としての半導体装置とな
る。
2. Description of the Related Art Conventionally, a semiconductor element accommodating package for accommodating a semiconductor element is generally made of an electrically insulating material such as an aluminum oxide sintered body, and has a concave portion for accommodating the semiconductor element on the upper surface and a periphery thereof. An insulating substrate having a metallized wiring layer made of a high melting point metal powder such as tungsten, molybdenum, or manganese that is led out to the outer peripheral portion, and a silver solder or the like for the metallized wiring layer for connecting each electrode of the semiconductor element to an external electric circuit. It is composed of an external lead terminal attached via a brazing material and a lid,
The semiconductor element is adhered and fixed to the bottom surface of the recess of the insulating substrate via an adhesive such as glass, resin, or a brazing material, and each electrode of the semiconductor element is electrically connected to the metallized wiring layer via a bonding wire. The lid is joined to the upper surface of the insulating base through a sealing material such as glass, resin, or brazing material,
A semiconductor device as a product is obtained by hermetically housing a semiconductor element in a container formed of an insulating base and a lid.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、近時、
半導体素子は高密度化、高集積化が急激に進み、電極数
が大幅に増大してきており、該半導体素子の各電極に接
続さる外部リード端子の数も急激に増大し、各外部リー
ド端子はその線幅が極めて細く、インダクタンスが20
nH程度の高いものとなってきている。そのためこの外
部リード端子を介して半導体素子に駆動のための電力及
び電気信号を供給した場合、外部リード端子のインダク
タンスが高いことに起因して半導体素子への供給電源電
圧に変動が生じると大きなノイズが発生し、これが電気
信号とともに半導体素子に供給されて半導体素子に誤動
作を起こさせるという重大な欠点を有していた。
However, in recent years,
The density and integration of semiconductor elements have rapidly increased, and the number of electrodes has increased significantly. The number of external lead terminals connected to each electrode of the semiconductor element has also increased rapidly, and each external lead terminal is The line width is extremely thin and the inductance is 20
It has become as high as nH. Therefore, when power and electric signals for driving are supplied to the semiconductor element through the external lead terminal, if the power supply voltage to the semiconductor element fluctuates due to the high inductance of the external lead terminal, a large noise is generated. Has occurred, and this is supplied to the semiconductor device together with the electric signal, causing the semiconductor device to malfunction.

【0004】そこで上記欠点を解消するために半導体素
子を収容する容器の蓋体内面で、半導体素子を収容する
空所と対向する領域にチタン酸バリウム磁器等から成る
容量素子を取着しておき、該容量素子の一対の電極を半
導体素子の電源電極及び接地電極に接続させ、半導体素
子の電源電極及び接地電極の間に一定の静電容量をもた
せておくことによって、半導体素子への供給電源電圧の
変動によって生じるノイズを前記静電容量に吸収させ、
半導体素子の誤動作を防止することが考えられる。
Therefore, in order to solve the above-mentioned drawbacks, a capacitive element made of barium titanate porcelain or the like is attached to the inner surface of the lid of the container for housing the semiconductor element in a region facing the void for housing the semiconductor element. , A pair of electrodes of the capacitive element is connected to a power electrode and a ground electrode of the semiconductor element, and a constant capacitance is provided between the power electrode and the ground electrode of the semiconductor element to supply power to the semiconductor element. The capacitance caused to absorb noise caused by voltage fluctuations,
It is possible to prevent malfunction of the semiconductor element.

【0005】しかしながら、この半導体素子収納用パッ
ケージにおいては、容量素子を構成するチタン酸バリウ
ム磁器等が多量のアルファ線を放出し、これが半導体素
子に作用して半導体素子を誤動作させるという欠点を誘
発してしまう。
However, in this semiconductor element housing package, the barium titanate porcelain or the like which constitutes the capacitive element emits a large amount of alpha rays, which acts on the semiconductor element and causes a malfunction of the semiconductor element. Will end up.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に収容する半導体素子を長期間にわ
たり正常、且つ安定に作動させることができる半導体素
子収納用パッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to provide a semiconductor element housing package capable of normally and stably operating a semiconductor element housed therein for a long period of time. Especially.

【0007】[0007]

【課題を解決するための手段】本発明は絶縁基体と蓋体
とから成る容器の内部空所に半導体素子を気密に収容す
る半導体素子収納用パッケージであって、前記蓋体の内
面で、半導体素子を収容する空所と対向する領域に容量
素子を取着するとともに該容量素子をアルファ線の放出
が少ない材料から成る保護膜で被覆したことを特徴とす
るものである。
SUMMARY OF THE INVENTION The present invention is a semiconductor element housing package for hermetically housing a semiconductor element in an inner space of a container composed of an insulating base and a lid, wherein the semiconductor is provided on the inner surface of the lid. It is characterized in that a capacitive element is attached to a region facing an empty space for accommodating the element, and the capacitive element is covered with a protective film made of a material that emits less alpha rays.

【0008】また本発明は前記保護膜がSiO 2 ーCaO ー
ZnO ガラス、SiO 2 ーBaO ーZnO ガラス、SiO 2 、エポ
キシ樹脂、ポリイミド樹脂もしくはこれらの混合物で形
成されていることを特徴とするものである。
In the present invention, the protective film is SiO 2 --CaO--
It is characterized by being formed of ZnO glass, SiO 2 —BaO—ZnO glass, SiO 2 , epoxy resin, polyimide resin or a mixture thereof.

【0009】[0009]

【作用】本発明の半導体素子収納用パッケージによれ
ば、半導体素子を収容する容器の蓋体内面で、半導体素
子を収容する空所と対向する領域に容量素子が取着され
ていることから、該容量素子の一対の電極を半導体素子
の電源電極及び接地電極に接続させ、半導体素子の電源
電極及び接地電極の間に一定の静電容量をもたせば、半
導体素子への供給電源電圧の変動によって生じるノイズ
は前記静電容量に有効に吸収されることとなり、その結
果、半導体素子へのノイズの入り込みによる誤動作がな
くなり、半導体素子を常に正常、且つ安定に作動させる
ことが可能となる。
According to the semiconductor element accommodating package of the present invention, the capacitative element is attached to the inner surface of the lid of the container accommodating the semiconductor element in a region facing the void for accommodating the semiconductor element. By connecting a pair of electrodes of the capacitive element to the power supply electrode and the ground electrode of the semiconductor element and providing a constant capacitance between the power supply electrode and the ground electrode of the semiconductor element, the power supply voltage to the semiconductor element fluctuates. The generated noise is effectively absorbed by the electrostatic capacitance, and as a result, malfunction due to noise entering the semiconductor element is eliminated, and the semiconductor element can always be operated normally and stably.

【0010】また本発明の半導体素子収納用パッケージ
によれば、容量素子をアルファ線の放出が少ない材料か
ら成る保護膜で被覆したことから半導体素子にアルファ
線が照射され、作用することは一切なく、その結果、半
導体素子がアルファ線によって誤動作することはなく、
常に正常、且つ安定に作動させることが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, since the capacitive element is covered with the protective film made of a material that emits less alpha rays, the semiconductor element is never irradiated with alpha rays and does not act at all. , As a result, the semiconductor element does not malfunction due to alpha rays,
It is possible to always operate normally and stably.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は本発明の半導体素子収納用パッケージの一実
施例を示す断面図であり、図中、1 は絶縁基体、2 は蓋
体である。この絶縁基体1 と蓋体2 とで半導体素子3 を
収容するための容器4 が構成される。
The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment of a package for housing a semiconductor device of the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 form a container 4 for housing the semiconductor element 3.

【0012】前記絶縁基体1 は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等から成
り、その上面の略中央部に半導体素子3 を収容するため
の空所を形成する凹部1aが設けてあり、該凹部1a底面に
は半導体素子3 がロウ材、ガラス、樹脂等の接着剤を介
して接着固定される。
The insulating substrate 1 is composed of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a glass ceramic sintered body, etc. A concave portion 1a is formed in the inner surface of the concave portion 1a for accommodating the semiconductor element 3, and the semiconductor element 3 is bonded and fixed to the bottom surface of the concave portion 1a via an adhesive such as a brazing material, glass, or resin.

【0013】前記絶縁基体1 は例えば、酸化アルミニウ
ム質焼結体から成る場合、アルミナ(Al 2 O 3 ) 、シリ
カ(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等のセ
ラミック原料粉末に適当な有機溶剤、溶媒を添加混合し
て泥漿状となすとともにこれを従来周知のドクターブレ
ード法やカレンダーロール法等によりシート状に成形し
てセラミックグリーンシート( セラミック生シート) を
得、しかる後、前記セラミックグリーンシートに適当な
打ち抜き加工を施すとともに複数枚積層し、高温( 約16
00℃) で焼成することによって製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, it is suitable for a ceramic raw material powder such as alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), magnesia (MgO). A simple organic solvent, a solvent is added and mixed to form a slurry, and this is molded into a sheet by a conventionally known doctor blade method, calendar roll method, etc. to obtain a ceramic green sheet (ceramic green sheet). Appropriate punching is performed on the ceramic green sheet and multiple sheets are laminated, and high temperature (about 16
It is manufactured by firing at 00 ℃.

【0014】また前記絶縁基体1 には凹部1a周辺から外
周部にかけて複数個のメタライズ配線層5 が被着形成さ
れており、該メタライズ配線層5 の凹部1a周辺部には半
導体素子3 の電極がボンディングワイヤ6 を介して電気
的に接続され、また絶縁基体1 の外周部に導出する部位
には外部リード端子7 がロウ材を介してロウ付けされ
る。
A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the recess 1a to the outer periphery thereof, and the electrodes of the semiconductor element 3 are formed on the periphery of the recess 1a of the metallized wiring layer 5. An external lead terminal 7 is brazed via a brazing material to a portion that is electrically connected via a bonding wire 6 and is led to the outer peripheral portion of the insulating base 1.

【0015】前記絶縁基体1 に設けたメタライズ配線層
5 はタングステン、モリブデン、マンガン等の高融点金
属粉末から成り、該メタライズ配線層5 は外部電気回路
に接続される外部リード端子7 に半導体素子3 の各電極
を電気的に導通させる作用を為す。
Metallized wiring layer provided on the insulating substrate 1
5 is made of a high melting point metal powder such as tungsten, molybdenum or manganese, and the metallized wiring layer 5 electrically connects each electrode of the semiconductor element 3 to an external lead terminal 7 connected to an external electric circuit.

【0016】前記メタライズ配線層5 は例えば、タング
ステン等の高融点金属粉末に有機溶剤、溶媒を添加混合
して得た金属ペーストを絶縁基体1 となるセラミックグ
リーンシートに予め従来周知のスクリーン印刷法により
所定パターンに印刷塗布しておくことによって絶縁基体
1 の所定位置に被着形成される。
For the metallized wiring layer 5, for example, a metal paste obtained by adding and mixing an organic solvent and a solvent to a high melting point metal powder such as tungsten is preliminarily formed on a ceramic green sheet serving as the insulating substrate 1 by a conventionally known screen printing method. Insulating substrate by printing and applying in a predetermined pattern
1 is formed in a predetermined position.

【0017】尚、前記メタライズ配線層5 はその露出す
る表面にニッケル、金等の耐蝕性に優れ、且つロウ材と
濡れ性の良い金属をメッキ法により1.0 乃至20.0μm の
厚みに層着させておくとメタライズ配線層4 の酸化腐食
を有効に防止することができるとともメタライズ配線層
5 とボンディングワイヤ6 及び外部リード端子7 とのロ
ウ付け接合を強固なものとなすことができる。従って、
前記メタライズ配線層5 の表面にはニッケル、金等の耐
蝕性に優れ、且つロウ材と濡れ性が良い金属をメッキ法
により1.0 乃至20.0μm の厚みに層着させておくことが
好ましい。
The metallized wiring layer 5 is formed by depositing a metal such as nickel and gold, which has excellent corrosion resistance and has a good wettability with a brazing material, on the exposed surface to a thickness of 1.0 to 20.0 μm by a plating method. The metallized wiring layer 4 can effectively prevent oxidative corrosion of the metallized wiring layer 4.
It is possible to strengthen the brazing connection between the 5, the bonding wire 6, and the external lead terminal 7. Therefore,
On the surface of the metallized wiring layer 5, it is preferable to deposit a metal such as nickel or gold having excellent corrosion resistance and good wettability with the brazing material to a thickness of 1.0 to 20.0 μm by a plating method.

【0018】また前記絶縁基体1 に被着したメタライズ
配線層5 にロウ付けされる外部リード端子7 は鉄ーニッ
ケルーコバルト合金や鉄ーニッケル合金等の金属材料か
ら成り、半導体素子3 の各電極を外部電気回路に電気的
に接続する作用を為す。
The external lead terminals 7 brazed to the metallized wiring layer 5 adhered to the insulating substrate 1 are made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy, and each electrode of the semiconductor element 3 is It acts to electrically connect to an external electric circuit.

【0019】前記外部リード端子7 は鉄ーニッケルーコ
バルト合金等のインゴット( 塊) を圧延加工法や打ち抜
き加工法等、従来周知の金属加工法を採用し、所定の板
状に成形することによって製作される。
The external lead terminal 7 is formed by forming an ingot (lump) of iron-nickel-cobalt alloy or the like into a predetermined plate shape by adopting a conventionally known metal processing method such as a rolling processing method or a punching processing method. Produced.

【0020】また一方、前記絶縁基体1 の上面には半導
体素子3 を収容する凹部1aを塞ぐように蓋体2 が半田等
から成る封止材を介して接合され、これによって絶縁基
体1と蓋体2 とから成る容器4 内部に半導体素子3 が気
密に収容される。
On the other hand, a lid 2 is joined to the upper surface of the insulating base 1 via a sealing material made of solder or the like so as to close the recess 1a for accommodating the semiconductor element 3, whereby the insulating base 1 and the lid are joined together. A semiconductor element 3 is hermetically housed in a container 4 composed of a body 2.

【0021】前記蓋体2 は例えば絶縁基体1 と同様、酸
化アルミニウム質焼結体、ムライト質焼結体、窒化アル
ミニウム質焼結体、炭化珪素質焼結体、ガラスセラミッ
クス焼結体等から成り、絶縁基体1 と同様の方法によっ
て板状に形成される。
Like the insulating substrate 1, the lid 2 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a glass ceramic sintered body, or the like. It is formed in a plate shape by the same method as the insulating substrate 1.

【0022】更に前記蓋体2 はその内面で、容器4 の半
導体素子3 を収容する空所と対向する領域に容量素子A
が取着されている。
Further, the lid 2 is provided on its inner surface with a capacitive element A in a region of the container 4 facing the void for accommodating the semiconductor element 3.
Is attached.

【0023】前記容量素子A はAg、AgPd、AgPt、Cu、N
i、Au等から成る一対の電極8 、10と、該一対の電極8
、10の間に挟まれ、SrTiO 3 、BaTiO 3 、Pb(Mg 1/3 N
b2/3 )O3 、Pb(Fe 1/3 Nb2/3 )O3 Pb(Fe 2/3 W 1/3 )
等から成る誘電体層9 とで形成されており、一対の電
極8 、10を半導体素子3 の電源電極及び接地電極に接続
させて半導体素子3 の電源電極及び接地電極の間に一定
の静電容量が付与させれば、該静電容量が半導体素子3
への供給電源電圧の変動によって生じるノイズを有効に
吸収して半導体素子3 へのノイズの入り込みによる誤動
作を有効に防止することができる。
The capacitive element A is Ag, AgPd, AgPt, Cu, N.
A pair of electrodes 8 and 10 made of i, Au, etc., and the pair of electrodes 8
, SrTiO 3 , BaTiO 3 , Pb (Mg 1/3 N
b 2/3 ) O 3 , Pb (Fe 1/3 Nb 2/3 ) O 3 Pb (Fe 2/3 W 1/3 )
And a dielectric layer 9 made of, for example, a pair of electrodes 8 and 10 connected to the power supply electrode and the ground electrode of the semiconductor element 3 to provide a constant electrostatic capacitance between the power supply electrode and the ground electrode of the semiconductor element 3. If a capacitance is applied, the capacitance will be
It is possible to effectively absorb the noise generated by the fluctuation of the power supply voltage to the semiconductor element 3 and effectively prevent the malfunction caused by the noise entering the semiconductor element 3.

【0024】前記容量素子A は蓋体2 の表面にAg、AgP
d、AgPt、Cu、Ni、Au等から成る電極8 を印刷法や蒸着
法、スパッタリング法等により所定厚みに被着させ、次
に前記電極8 上にSrTiO 3 、BaTiO 3 、Pb(Mg 1/3 Nb
2/3 )O3 、Pb(Fe 1/3 Nb2/3 )O3Pb(Fe 2/3 W 1/3 ) 等
から成る誘電体層9 を印刷法や蒸着法、スパッタリング
法等により所定厚みに被着させ、最後に前記誘電体層9
上にAg、AgPd、AgPt、Cu、Ni、Au等から成る電極10を印
刷法や蒸着法、スパッタリング法等により所定厚みに被
着させることによって形成される。
The capacitive element A has Ag and AgP on the surface of the lid 2.
An electrode 8 made of d, AgPt, Cu, Ni, Au or the like is deposited to a predetermined thickness by a printing method, a vapor deposition method, a sputtering method or the like, and then SrTiO 3 , BaTiO 3 , Pb (Mg 1 / Mg 1 / 3 Nb
2/3 ) O 3 , Pb (Fe 1/3 Nb 2/3 ) O 3 Pb (Fe 2/3 W 1/3 ), etc. are used to form a dielectric layer 9 by printing, vapor deposition, sputtering, etc. Deposited to thickness and finally the dielectric layer 9
It is formed by depositing an electrode 10 made of Ag, AgPd, AgPt, Cu, Ni, Au or the like on the upper surface to a predetermined thickness by a printing method, a vapor deposition method, a sputtering method or the like.

【0025】また前記容量素子A の半導体素子3 の電源
電極及び接地電極への接続は、絶縁基体1 の上面に予め
半導体素子3 の電源電極及び接地電極が接続されるメタ
ライズ配線層より分岐する電源電極用導出パッド5aと接
地電極用導出パッド5bを設けておき、絶縁基体1 に蓋体
2 を封止材を介し接合させる際に、蓋体2 に被着されて
いる容量素子A の一方の電極10を電源電極用導出パッド
5aに、他方の電極8 を接地電極用導出パッド5bに各々半
田を介し接合させることによって行われる。
The connection of the capacitive element A to the power electrode and the ground electrode of the semiconductor element 3 is performed by a power source branched from a metallized wiring layer to which the power electrode and the ground electrode of the semiconductor element 3 are previously connected to the upper surface of the insulating substrate 1. An electrode lead-out pad 5a and a ground electrode lead-out pad 5b are provided in advance, and the insulating base 1 is covered with a lid.
When joining 2 via the sealing material, one electrode 10 of the capacitive element A attached to the lid 2 is connected to the lead-out pad for the power electrode.
5a, the other electrode 8 is joined to the ground electrode lead-out pad 5b via solder, respectively.

【0026】尚、本実施例の場合、容量素子A の一方の
電極8 が、電気絶縁材料から成る蓋体2 を絶縁基体1 に
封止材を介して接合させる際の下地金属層としても作用
し、容量素子A の一方の電極8 を絶縁基体1 の上面に設
けた接地電極用導出パッド5bに半田等を介し接合させ
ることによって蓋体2 は絶縁基体1 に容器4 内部に半
導体素子3 を気密に収容するように接合される。
In the case of the present embodiment, one electrode 8 of the capacitive element A also acts as a base metal layer when the lid 2 made of an electrically insulating material is joined to the insulating base 1 via the sealing material. Then, the one electrode 8 of the capacitive element A is bonded to the lead-out pad 5b for the ground electrode provided on the upper surface of the insulating substrate 1 by soldering or the like, so that the lid 2 is attached to the insulating substrate 1 and the semiconductor element 3 is placed inside the container 4. It is joined so that it can be hermetically sealed.

【0027】更に前記容量素子A はその表面がSiO 2
CaO ZnO ガラス、SiO 2 BaO ZnO ガラス、SiO 2
エポキシ樹脂、ポリイミド樹脂もしくはこれらの混合物
等のアルファ線の放出が少ない材料から成る保護膜B で
被覆されており、該保護膜B は容量素子A から多量のア
ルファ線が放出され、これが容器4内部に収容する半導
体素子3 に照射、作用するのを有効に阻止す作用を為
し、これによって半導体素子3 がアルファ線によって誤
動作することはなく、常に正常、且つ安定に作動するこ
とが可能となる。
Further, the surface of the capacitive element A is SiO 2
CaO ZnO glass, SiO 2 BaO ZnO glass, SiO 2 ,
It is covered with a protective film B made of a material such as epoxy resin, polyimide resin, or a mixture of these which emits little alpha rays. The protective film B emits a large amount of alpha rays from the capacitive element A, and this is inside the container 4. The semiconductor element 3 housed in is effectively prevented from irradiating and acting, so that the semiconductor element 3 does not malfunction due to alpha rays and can always operate normally and stably. .

【0028】前記保護膜B はSiO 2 CaO ZnO ガラス
等に適当な有機溶剤、溶媒を添加混合して得たぺースト
や液状のエポキシ樹脂等を容量素子A の表面に従来周知
の印刷法により被着させ、しかる後、これを熱処理する
ことによって容量素子A 表面に所定厚み(10 〜100 μm)
に被着される。
The protective film B is formed by coating a suitable organic solvent, a paste obtained by mixing and mixing a solvent such as SiO 2 CaO ZnO glass, or a liquid epoxy resin on the surface of the capacitive element A by a conventionally known printing method. And then heat-treating it to give a predetermined thickness (10 to 100 μm) on the surface of the capacitive element A.
Be attached to.

【0029】かくして、上述の半導体素子収納用パッケ
ージによれば、絶縁基体1 の凹部1a底面に半導体素子3
をロウ材、ガラス、樹脂等の接着剤を介して接着固定す
るとともに該半導体素子3 の各電極をボンディングワイ
ヤ6 を介してメタライズ配線層5 に電気的に接続し、し
かる後、絶縁基体1 の上面に蓋体2 を半田等の封止材を
介し接合させ、絶縁基体1 と金属製蓋体2 とから成る容
器4 内部に半導体素子3 を気密に封止することによって
最終製品としての半導体装置となる。
Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is formed on the bottom surface of the recess 1a of the insulating substrate 1.
Are bonded and fixed via an adhesive such as a brazing material, glass, or resin, and each electrode of the semiconductor element 3 is electrically connected to the metallized wiring layer 5 via a bonding wire 6, and then the insulating substrate 1 The lid 2 is bonded to the upper surface via a sealing material such as solder, and the semiconductor element 3 is hermetically sealed inside the container 4 composed of the insulating base 1 and the metallic lid 2 to form the final semiconductor device. Becomes

【0030】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist of the present invention.

【0031】[0031]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子を収容する容器の蓋体内面で、半導
体素子を収容する空所と対向する領域に容量素子が取着
されていることから、該容量素子の一対の電極を半導体
素子の電源電極及び接地電極に接続させ、半導体素子の
電源電極及び接地電極の間に一定の静電容量をもたせ
ば、半導体素子への供給電源電圧の変動によって生じる
ノイズは前記静電容量に有効に吸収されることとなり、
その結果、半導体素子へのノイズの入り込みによる誤動
作がなくなり、半導体素子を常に正常、且つ安定に作動
させることが可能となる。
According to the package for accommodating a semiconductor element of the present invention, the capacitive element is attached to the inner surface of the lid of the container accommodating the semiconductor element in a region facing the void for accommodating the semiconductor element. Therefore, if a pair of electrodes of the capacitive element is connected to the power electrode and the ground electrode of the semiconductor element and a constant capacitance is provided between the power electrode and the ground electrode of the semiconductor element, the power supply voltage to the semiconductor element is Noise caused by fluctuations will be effectively absorbed by the capacitance,
As a result, malfunction due to noise entering the semiconductor element is eliminated, and the semiconductor element can always be operated normally and stably.

【0032】また本発明の半導体素子収納用パッケージ
によれば、容量素子をアルファ線の放出が少ない材料か
ら成る保護膜で被覆したことから半導体素子にアルファ
線が照射され、作用することは一切なく、その結果、半
導体素子がアルファ線によって誤動作することはなく、
常に正常、且つ安定に作動させることが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, since the capacitive element is covered with the protective film made of a material that emits less alpha rays, the semiconductor element is never irradiated with alpha rays and does not act at all. , As a result, the semiconductor element does not malfunction due to alpha rays,
It is possible to always operate normally and stably.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基体 1a・・・・・凹部 2・・・・・・蓋体 3・・・・・・半導体素子 4・・・・・・容器 5・・・・・・メタライズ配線層 7・・・・・・外部リード端子 A・・・・・・容量素子 B・・・・・・保護膜 1 ... Insulating substrate 1a ... Recessed portion 2 ... Lid body 3 ... Semiconductor element 4 ... Container 5 ... Metallization Wiring layer 7: External lead terminal A: Capacitive element B: Protective film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体と蓋体とから成る容器の内部空所
に半導体素子を気密に収容する半導体素子収納用パッケ
ージであって、前記蓋体の内面で、半導体素子を収容す
る空所と対向する領域に容量素子を取着するとともに該
容量素子の表面をアルファ線の放出が少ない材料から成
る保護膜で被覆したことを特徴とする半導体素子収納用
パッケージ。
1. A semiconductor element housing package for hermetically housing a semiconductor element in an inner space of a container composed of an insulating base and a lid, wherein the inner surface of the lid is a space for housing the semiconductor element. A package for accommodating a semiconductor element, characterized in that a capacitor element is attached to a region facing each other, and a surface of the capacitor element is covered with a protective film made of a material that emits less alpha rays.
【請求項2】前記保護膜がSiO 2 CaO ZnO ガラス、
SiO 2 BaO ZnO ガラス、SiO 2 、エポキシ樹脂、ポ
リイミド樹脂もしくはこれらの混合物で形成されている
ことを特徴とする請求項1に記載の半導体素子収納用パ
ッケージ。
2. The protective film is SiO 2 CaO ZnO glass,
The package for housing a semiconductor element according to claim 1, which is made of SiO 2 BaO ZnO glass, SiO 2 , epoxy resin, polyimide resin, or a mixture thereof.
JP7035004A 1995-02-23 1995-02-23 Package of semiconductor element Pending JPH08236651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7035004A JPH08236651A (en) 1995-02-23 1995-02-23 Package of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7035004A JPH08236651A (en) 1995-02-23 1995-02-23 Package of semiconductor element

Publications (1)

Publication Number Publication Date
JPH08236651A true JPH08236651A (en) 1996-09-13

Family

ID=12429960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7035004A Pending JPH08236651A (en) 1995-02-23 1995-02-23 Package of semiconductor element

Country Status (1)

Country Link
JP (1) JPH08236651A (en)

Similar Documents

Publication Publication Date Title
EP0180219A2 (en) Capacitor built-in integrated circuit packaged unit and process of fabrication thereof
JPH08139269A (en) Package for containing semiconductor element
JPH08236651A (en) Package of semiconductor element
JPH03250659A (en) Semiconductor device package
JPH05144953A (en) Electronic component containing package
JP2962921B2 (en) Manufacturing method of semiconductor device storage package
JP2735759B2 (en) Package for storing semiconductor elements
JP2514094Y2 (en) Package for storing semiconductor devices
JP2750232B2 (en) Electronic component storage package
JP2997379B2 (en) Semiconductor device
JP2958201B2 (en) Package for storing semiconductor elements
JP2962951B2 (en) Package for storing semiconductor elements
JP3441199B2 (en) Package for storing semiconductor elements
JP2750241B2 (en) Package for storing semiconductor elements
JPH05275608A (en) Semiconductor element housing package
JP2713841B2 (en) Package for storing semiconductor elements
JP3187239B2 (en) Package for storing semiconductor elements
JP2958211B2 (en) Package for storing semiconductor elements
JP2577088Y2 (en) Package for storing semiconductor elements
JPH0677348A (en) Package for encapsulation of semiconductor element
JPH0637205A (en) Ceramic wiring substrate
JPH06244301A (en) Package for containing semiconductor element
JPH06236938A (en) Package for semiconductor-element housing
JPH0951069A (en) Package for housing semiconductor chip
JPH06283624A (en) Package for housing semiconductor device