JPH08235771A - Method and circuit for read/write control in memory for sound recording/reproducing device - Google Patents

Abstract

PURPOSE: To prevent interruption of reproduced sound by making a changeover between a write priority and a read priority depending on whether the arrangement of data to be inputted to memory is in the normal direction or the reverse one when a read request and a write request to memory occur concurrently. CONSTITUTION: Reproduced data is written into a DRAM of a sound recording/ reproducing device such as VTR with a speed faster than the reading speed through a DRAM controller. The DRAM controller is provided with a judging circuit which includes logic gates, 25 to 24, 26 and D type EF 20, 25, etc., and to which UPDOWN signals showing whether the direction of reproduction is normal or reverse, switching signals SW inversed every read/write operation, and judgment timing signals JUDGE outputted in one byte unit are supplied. When a read request RREQ and a write request WREQ2 are concurrently generated, a first priority in outputting is given to the write enable signal WEB at the time of reproduction in the normal direction and to the read enable signals REB at the time of reproduction in the reverse direction to prevent reproduced sound from being interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio recording / reproducing apparatus for recording / reproducing an audio signal, and relates to read / write control of a memory for storing audio data.

[0002]

2. Description of the Related Art In recent years, a function called a digest play has been added to a VTR so that a reproduced voice can be heard naturally during high speed reproduction. This function allows the VTR to hear the voice at a normal speed when it is played back at a high speed of 3 times or 5 times, and the high speed reproduced voice data is once written in the memory. The audio data stored in the memory is read and reproduced at a normal speed.

In this case, since the read speed is slower than the write speed, only the readable amount of audio data is stored in the memory, and the remaining reproduction data is discarded without being stored. For example, during the 5 × speed reproduction, the audio data for 15 seconds is reproduced at a high speed for 3 seconds in the normal reproduction, but the data is written to the memory only for 0.6 seconds, and this data is read for 3 seconds at the normal speed. The sound is emitted, and the sound for the remaining 12 seconds is thinned out.

[0004]

In the digest play function described above, when the VTR playback direction is the forward direction, the addressing direction during read / write to the memory is, for example, from the lower address to the upper address in the same direction. Since the write speed is set and the write speed is faster than the read speed, the write operation always precedes the read operation.

Therefore, when a read request and a write request occur simultaneously, if the write priority is given, the voice based on the data read from the memory is reproduced without interruption. However, when the playback direction of the VTR is the reverse direction, the arrangement of the audio data input to the memory is reversed. Therefore, when writing to the memory with this arrangement as it is, the addressing direction at the time of reading is opposite to the direction at the time of writing. That is, when writing is performed from the lower address to the upper address, it is not possible to listen to the voices in the order in which they are sounded unless the upper address is read toward the lower address.

Therefore, it is conceivable to change the addressing direction according to the arrangement of the input audio data. However, since the addressing direction is opposite during read and write, a read request is issued during operation. There is always a point that write requests are simultaneously issued to the same address. Figure 6
The movements of the read address and the write address in the case of such high speed reverse reproduction are shown in FIG. This figure is an example of 5 × speed reverse reproduction, where the horizontal axis represents time and the vertical axis represents the memory address. The read address is shown by a solid line and the write address is shown by a wavy line.

As shown in the figure, the write operation is performed in the periods A, B and C from the lower address of the memory to the upper address, and the read operation is always continuously performed from the upper address of the memory to the lower address. . Then, in this example, the write periods B and C are each set to ⅕ of the period D for reading from the lowest address LSB of the memory to the highest address MSB.

First, in the period A, from the address P to the lowest address LSB, the voice data reproduced at high speed is sequentially written, and the voice data written in this period is D
During the period D1 of the period, data is sequentially read from the lowest address toward the higher address, and when the point c is reached, new input audio data is added to the address lower than the address Q at the point c just read. Lights will start. In parallel with this write operation, the data read which is written in the address higher than the address Q in the period A is continued.
When the writing and reading proceed to reach the point d, the write operation ends, and after the point d, the audio data written in the period B2 is sequentially read. After that, the same operation is performed.

Here, paying attention to the point c in which a read request and a write request are simultaneously generated, the audio data written in the period A is continuously read before and after the point c, but at the point c as in the conventional case. When the write priority is given, new data is written only at this point, the audio data at the point h, which should be read originally, is not read, and the newly written audio data is read. Therefore, a discontinuity occurs at the point c, and this discontinuity appears as noise when reproduced. Such a phenomenon is caused by simultaneous occurrence of a read request and a write request a, b, d, e, f.
It also happens at points.

[0010]

SUMMARY OF THE INVENTION According to the present invention, the addressing direction at the time of read / write with respect to the memory for audio recording / reproducing apparatus storing audio data is the same when the array of the input audio data is the forward direction. When the array is in the reverse direction, it is in the opposite direction, and when a read request and a write request to the memory occur at the same time, the write priority is given when the array is the forward direction, and the read priority is given when the array is the reverse direction. By solving the above, the above-mentioned problems are solved.

Further, according to the present invention, a direction signal indicating whether the arrangement of the audio data inputted to the memory for audio recording / reproducing apparatus storing the audio data is a forward direction or a reverse direction, a read request signal and a write request to the memory. Signal, and when the read request signal and the write request signal are input at the same time, the direction signal is determined, and if the array is in the forward direction, the write enable signal is output by giving write priority to the access to the memory. However, when the arrangement is in the reverse direction, the above problem is solved by providing a read / write determination circuit that outputs a read enable signal by giving priority to access to the memory.

Further, in the present invention, the read / write control circuit further includes a signal generation circuit for generating a switching signal which is inverted each time a read / write operation is executed, based on the read enable signal and the write enable signal. Prepare,
When the read request signal and the write request signal are input at the same time, the read / write determination circuit determines the switching signal, and after one of the read or write operation preferentially performed, the other operation is performed. It is characterized by outputting a write enable signal or a read enable signal for performing an operation.

[0013]

According to the present invention, when a read request and a write request for the memory occur simultaneously, the write priority or the read priority is switched depending on whether the arrangement of the audio data input to the memory is the forward direction or the reverse direction. The reproduced sound is continuous without interruption, and the generation of noise due to the discontinuity is prevented.

[0014]

FIG. 3 is a schematic block diagram of an entire audio recording / reproducing apparatus including an embodiment of the present invention, 1 being an AD converter for converting an input analog audio signal into digital audio data, and 2 being converted. DRA for storing voice data
M and 3 are DRAM controllers which are connected to the DRAM 2 and control read / write of the DRAM 2. 4 is a DSP which controls the entire audio recording / reproducing apparatus. 5 is a DA which converts the audio data read from the memory 2 into an analog audio signal.
The converter 6 is a clock generator that sends a reference clock signal to each unit.

Write request signal WRE for DRAM 2
Q and read request signal RREQ are supplied from AD converter 1 and DA converter 5 to DRAM controller 3 respectively.
Is output to the DRAM controller 3, and when the read and write operations are completed, the write acknowledge signal WA is output.
The CK and the read ACK signal RACK are returned, and the AD converter 1 and the DA converter 5 reset the write request signal WREQ or the read request signal RREQ according to these ACK signals.

Further, the DSP 4 inputs speed information ST indicating the multiple times of the high speed reproduction speed of the VTR and direction information DS indicating whether the reproduction direction is the forward direction or the reverse direction from the outside and responds to the direction information DS. And outputs the direction signal UPDOWN indicating the arrangement direction of the input voice data to the DRAM controller 3 and the speed information ST to the AD converter 1. AD
The converter 1 switches the sampling frequency according to the speed information ST and outputs the write request signal WREQ at a timing according to the speed information. Furthermore, DSP4
Outputs the clock signal CLK to the DRAM controller 3.

Next, a detailed circuit configuration of the DRAM controller 3 will be described with reference to FIG. A write request signal W from the AD converter 1 is provided in the DRAM controller 3.
Second write request signal WREQ2 generated internally based on REQ2, read request signal R from DA converter 5
Direction signal UPDOWN from REQ and DSP4, internally generated switching signal SW and determination timing signal JU
A read / write determination circuit 7 that inputs DGE and outputs a write enable signal WEB and a read enable signal REB is provided, and these enable signals are
It is input to the NAND gates 10 and 11 via the inverters 8 and 9. Also, these enable signals are inverted and input to the AND gate 12, and outputs REF and D
The clock signal CLK from SP4 is input to the RAS / CAS generation circuit 13. DRAM2 is CASbefore
A memory that performs eRAS refresh,
The AS / CAS generation circuit 13 causes the CAS to fall before the RAS when the signal REF is at the H level, and the DRAM 2
To perform a refresh operation and perform a read or write operation when the signal REF is at L level, the RAS / CAS signal is sent to the DRAM 2 at a predetermined timing.
In addition, the write enable signal WEB is output to the DRAM 2 as it is.

Further, an 8-bit counter 14 for generating an output each time the CAS signal is counted eight times is provided, and its output is inputted to the NAND gates 10 and 11.
Clock signals WACLK and R passed through these gates
ACLK is input to the address counter 15. The output of the 8-bit counter 14 is applied to the D terminal of the D flip-flop 16, the inverted signal of the clock signal CLK is applied to the clock terminal CL, and the inverted Q output becomes the determination timing signal JUDGE. That is, signal J
UDGE is periodically output every 8 counts. Also,
The clock signals WACLK and RACLK are input to the NAND gate 17 whose output is the inverted Q output of itself.
It is applied to the clock terminal CL of the D flip-flop 18 input to the terminal, and the output of this D flip-flop 18 becomes the switching signal SW.

The address counter 15 compares the contents of the read address counter 151, the write address counter 152, the write end counter 153 and the contents of the counters 152 and 153 and outputs a coincidence signal WAEND.
54, and the coincidence signal WAEND is input as the reset signal of the D flip-flop 18. A direction signal UPDOWN and enable signals WEB and REB are input to the address counter 15, and the count direction of the write address counter 152 is switched according to the direction signal and the address counters 151 and 152 are selected according to the enable signal. Either one is transmitted to the address bus 30.

Further, an AN which inputs the signal WREQ at one end
A D gate 40, an AND gate 41 that inputs signals CAS and WACLK, a D flip-flop 42 that inputs the outputs of these AND gates 40 and 41 to a D terminal and a clock terminal CL, respectively, and an H level signal to the D terminal. The latch circuit 43 which receives the Q output of the D flip-flop 42 as a latch pulse, inputs the inverted Q output thereof to the other end of the AND gate 40, and is reset by WACLK
Is provided and the inverted Q output of the D flip-flop 42 is output to the AD converter 1 as a signal WACK,
The Q output of the latch circuit 43 is the second write request signal WREQ.
It becomes 2. Further, the OR gate 44 outputs signals REB and JU.
DGE is input and its output is signal RACK
Is output to the DA converter 5.

In addition, data is written to the DRAM 2 during the write operation.
Is provided with a shift register 44 for converting the 8-bit parallel data from the AD converter 1 into serial data. The shift register 44 includes:
The output of the OR gate 45 for inputting the signals WEB and CAS is applied to the clock terminal CL, and the output of the AND gate 40 is applied to the preset terminal P. On the other hand, a shift register 46 is provided to send data to the DSP 4 during a read operation, and the output of the OR gate 47 for inputting the signals REB and CAS is applied to the clock terminal CL in the shift register 46, and the data line The data from 32 is applied to the D terminal.

FIG. 2 is a diagram showing a specific circuit of the read / write determination circuit 7, in which the signal RREQ is applied to the D terminal and the signal JUDGE is applied to the clock terminal, and the signal RREQ. AND gate 21 to which the inverted signal and the signal WREQ2 are applied, and the signal SW
And an EX-NOR gate 22 to which the signal UPDOWN is applied, an output of the EX-NOR gate 22 and a signal WREQ.
AND gate 23 to which 2 is applied, and AND gate 22
And OR gate 24 to which the outputs of
The output of the gate 24 is applied to the D terminal and the signal JUDGE
Is applied to the clock terminal of the D flip-flop 25
And an OR gate 26 to which the inverted Q output of the D flip-flop 20 and the Q output of the D flip-flop 25 are applied. The output of the OR gate 26 is output as the read enable signal REB, and the inverted of the D flip-flop 25. The Q output is output as the write enable signal WEB.

The operation of this embodiment will be described below with reference to the timing charts of FIGS. First, DRA
Prior to the access of M2, the DSP 4 sets the first read address, first write address, and end write address in the read address counter 151, write address counter 152, and end address counter 153, respectively.

In this state, if the read request signal RREQ and the write request signal WREQ simultaneously become H level as shown in FIGS. 4A and 4B, the DRAM controller 3
In the read / write determination circuit 7 in the D flip-flops 20 and 25, since the inverted Q output is at the H level until the signal JUDGE is applied, the enable signals REB and WE.
Both B are at H level, so that the output REF of the AND gate 12 is at H level. Therefore,
The RAS / CAS signal is output at a predetermined timing for refreshing.

Immediately after the signal WREQ rises, AND
Since the output of the gate 40 becomes H level and the signal WACLK is H level, when the CAS signal rises as shown in FIG. 4, the H level signal is taken into the D flip-flop 42 and this signal is used as a latch pulse in the latch circuit. 43
Is applied to the second write request signal WR, which is an output.
EQ2 becomes H level as shown in FIG. The signal WACK which is the inverted Q output of the D flip-flop 42 is shown in FIG.
The signal becomes L level like this, and this signal is AD converter 1
Is input to the signal WREQ, and the signal WREQ is reset as shown in FIG.

If the direction signal UPDOWN is at the L level indicating the forward reproduction as shown in FIG. 4E, the switching signal SW is at the L level in the initial state (FIG. 4S), so E
The output of the X-NOR gate 22 becomes H level, and the signal R
Since REQ and WREQ2 are H level as described above, the output of the AND gate 21 is L level, AND
The output of the gate 23 becomes H level. Therefore, the output V of the OR gate 24 becomes H level as shown in FIG. 4, and the D terminals of the D flip-flops 20 and 25 both become H level.

When the judgment timing signal JUDGE, which is periodically input, is applied (FIG. 4E), the inverted Q output of the D flip-flop 20 becomes L level in response to the rising edge of the judgment timing signal JUDGE. Since the Q output of the flip-flop 25 becomes H level, the read enable signal REB which is the output of the OR gate 26 maintains H level as shown in FIG.
The write enable signal WEB which is an output becomes L level as shown in FIG.

When the signal WEB becomes L level, the output signal REF of the AND gate 12 becomes L level, so that RA
The S / CAS generation circuit 13 generates a RAS / CAS signal at a predetermined timing for access, as shown in FIG.
The DRAM 2 can be accessed. At this time, the address counter 15 determines that the write address counter 1 is in response to the signal WEB being at the L level.
Since the content of 52 is output, the first write address set by the DSP 4 is output to the address bus 30.

The 8-bit parallel data sent from the AD converter 1 to the data bus 19 is preset in the shift register 44 when the output of the AND gate 40 becomes H level when the signal WREQ becomes H level. Since the CAS signal is input as a clock to the shift register 44 via the OR gate 45 while the signal WEB is at the L level, the data is shifted by this clock and the data from the data line 31 to the DRAM 2 is shifted.
Are serially sent to and written to.

As described above, the write operation is preferentially executed for the DRAM 2. In this write operation, when the CAS signal is output eight times and one byte of data is written to the DRAM 2, the counter 14 generates a pulse output, and this pulse is inverted by the NAND gate 10 to generate the clock WACLK in the address counter 15 (FIG. 4C), the corresponding write address counter 152 is incremented. Therefore, in the next write operation, 8-bit data is written to this incremented address. When the data write operation progresses and the contents of the write address counter 152 and the end address counter 153 match, the comparator 154 outputs the signal WAEND, and this signal resets the D flip-flop 18, so that the output signal SW is It becomes the L level in the initial state.

By the way, when the clock signal WACLK becomes L level, the D flip-flop 1
Since 8 takes in its own inverted Q output, the switching signal SW goes to H level as shown in FIG. 4, and the signal WREQ2 goes to L level because the latch circuit 43 is reset by the signal WACLK. When the switching signal SW becomes H level, the output of the EX-NOR gate 22 becomes L level, and at this time the signal WREQ2 is also L level, the outputs of the AND gates 21 and 22 both become L level, which causes The output V of the OR gate 24 also becomes L level. Therefore, when the signal JUDGE is applied in this state, the output WEB of the D flip-flop 25 goes to the H level and the write operation ends, while the inverted Q output of the D flip-flop 20 at the L level is fed to the OR gate 26. It is input, and this time, its output signal REB changes to L level.

When the signal REB changes to the L level, the content of the read address counter 151 is transmitted to the address bus 30 in the address counter 15, and the signals RAS and CAS are output from the RAS / CAS generation circuit 13 as in the case of writing. Occurs, and the read operation that has been waited for is executed for the DRAM 2. The read data is input to the shift register 46 via the data line 32, and the CAS signal is input as a clock to the shift register 46 via the OR gate 47 while the signal REB is at the L level. Data serially input by this clock is taken into the shift register 46.

Also in this read operation, when the CAS signal is output eight times and one byte of data is read from the DRAM 2, the counter 14 generates a pulse output, and this pulse is inverted by the NOR gate 11 to generate the clock RACLK. Is input to the address counter 15 (FIG. 4), the corresponding read address counter 151
Is incremented. Therefore, in the next read operation, data read is performed for this incremented address.

By the way, when the clock signal RACLK becomes L level, the D flip-flop 1
Since 8 takes in its own inverted Q output, the switching signal SW becomes L level as shown in FIG. Switching signal SW is L
When it goes to the level, the output of the EX-NOR gate 22 goes to the H level, and at this time, the signal WREQ2 is at the L level, so the outputs of the AND gates 21 and 22 both go to the L level, whereby the OR gate 24 to the D The signal V to the flip-flop 25 also becomes L level.

In this state, when the signal JUDGE goes to L level, the signal REB is still at L level, so the OR gate 44
The RACK signal is output from the DA converter 5
Sent to Therefore, the DA converter 5 outputs the signal RR.
The EQ is reset and the signal RREQ is displayed as shown in FIG.
Falls to L level. D flip-flops 20, 25
Takes in the input at the rising edge of the signal JUDGE, the inverted Q outputs of both flip-flops become H level, both signals REB and WEB become H level, and the read operation ends.

As described above, when the reproduction direction is the forward direction, when the read request and the write request are generated at the same time, the access is performed with the write priority, and the read operation is executed after the write operation is completed. Next, a case where the reproduction direction is the reverse direction will be described with reference to FIG. In this case,
As shown in, the direction signal UPDOWN becomes H level. Therefore, write and read request signals WREQ2, R
When both REQ are at H level, D flip-flop 2
Since the D terminal of 0 becomes the H level and the signal SW is at the L level in the initial state (FIG. 5), the output of the EX-NOR gate 22 becomes the L level, which causes the outputs of the AND gates 21 and 23. L level, therefore OR
The output V of the gate 24 becomes L level as shown in FIG.

Here, when the judgment timing signal JUDGE is applied (FIG. 5E), D
The inverted Q output of the flip-flop 20 becomes L level,
Since the Q output of the D flip-flop 25 also becomes L level, the read enable signal REB from the OR gate 26
Becomes L level as shown in FIG. 5, while the write enable signal WEB which is the inverted Q output of the D flip-flop 25 maintains H level as shown in FIG.

When the signal REB becomes L level, the output signal REF of the AND gate 12 becomes L level, so that RA
The S / CAS generation circuit 13, as shown in FIG.
The / CAS signal is set to the L level so that the DRAM 2 can be accessed. At this time, the address counter 15 outputs the content of the read address counter 151 in response to the signal REB being at the L level, so that the first read address set by the DSP 4 is output to the address bus 30.

Therefore, the read operation is preferentially executed for the DRAM 2. In addition, data DSP4
The data is sent to the shift register in the same manner as described above. In this read operation, the CAS signal is 8
When the 1-byte data is output once and read from the DRAM 2, the counter 14 generates a pulse output, and the pulse is inverted by the NOR gate 11 to generate the clock R.
Since it is input to the address counter 15 as ACLK (FIG. 5), the corresponding read address counter 151 is incremented. Therefore, at the next read operation, data read is performed to this incremented address.

When the clock signal RACLK becomes L level, the D flip-flop 18 takes in its own inverted Q output at the falling edge thereof, so that the switching signal SW becomes H level as shown in FIG. When the switching signal SW becomes H level, the direction signal UPDOWN is at H level, so EX-N
The output of the OR gate 22 becomes H level, and since the signal WREQ2 is kept at H level at this time, the output of the AND gate 23 becomes H level, and the output V of the OR gate 24 also becomes H level.

In this state, when the signal JUDGE becomes L level, the signal REB is still L level, so the OR gate 44
The RACK signal is output from the DA converter 5
Sent to Therefore, the DA converter 5 outputs the signal RR.
EQ is reset and signal RREQ is displayed as shown in FIG.
Falls to L level. D flip-flops 20, 25
Takes in the input at the rising edge of the signal JUDGE, the inverted Q output of the flip-flop 20 becomes H level and the inverted Q output of the D flip-flop 25 becomes L level. Therefore, the signal REB goes high and the read operation ends, and the signal WEB goes low this time.

When the signal WEB becomes L level, the address counter 15 sends the contents of the write address counter 152 to the address bus 30, and at the same time,
Similar to the read operation, signals RAS and CAS are generated from the RAS / CAS generation circuit 13, and the write operation that has been on standby is thereby executed for the DRAM 2. Incidentally, D
The transmission of data to the RAM 2 is performed by the shift register 44 as described above.

In this write operation, the CAS signal is 8
When the data is output once and 1-byte data is written to the DRAM 2, the counter 14 generates a pulse output, and this pulse is inverted by the NAND gate 10 to generate the clock W.
Since ACLK is input to the address counter 15 (FIG. 5), the corresponding write address counter 152 is incremented. Therefore, at the next write operation, data write is performed to the incremented address. When the data write operation progresses and the contents of the write address counter 152 and the end address counter 153 match, the comparator 154 outputs the signal WAEND, and this signal resets the D flip-flop 18, so that the output signal SW is It becomes the L level in the initial state.

By the way, when the clock signal WACLK becomes L level, the D flip-flop 1
Since 8 takes in its own inverted Q output, the switching signal SW becomes L level as shown in FIG. Further, since the latch circuit 43 is reset by the signal WACLK, the signal WREQ2 becomes L level. When the switching signal SW becomes L level, the output of the EX-NOR gate 22 becomes L level, and at this time, the signal WREQ2 is at L level, so that the outputs of the AND gates 21 and 22 both become L level. The signal V from the OR gate 24 to the D flip-flop 25 also becomes L level. Furthermore, since the input RREQ to the D flip-flop 20 is also at L level, when the signal JUDGE is applied in this state, the inverted Q outputs of both D flip-flops become H level, and the signals REB and WEB Both become H level, and the write operation ends.

As described above, when the reproduction direction is the reverse direction, when a read request and a write request are generated at the same time, access is performed with read priority, and the write operation is executed after the read operation is completed. Therefore, in FIG. 6, points a, b, c, d, at which read requests and write requests occur at the same time.
In e and f, the read operation is prioritized, so that no discontinuous point occurs and the reproduced sound is continuous.

When only one of the read and write request signals is input, of course, only the requested operation is performed.

[0047]

According to the present invention, when a read request and a write request to the memory are simultaneously made to the same address, whether the access to the memory is the write priority or the read priority depending on the arrangement direction of the input voice data. Since it is properly switched to, it is possible to reproduce continuous voice and reliably prevent the generation of noise due to discontinuity points.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM controller as an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a read / write determination circuit in this embodiment.

FIG. 3 is a block diagram showing the overall configuration of a voice recording / playback apparatus including this embodiment.

FIG. 4 is a timing chart for explaining an operation during forward reproduction in the present embodiment.

FIG. 5 is a timing chart for explaining an operation at the time of backward reproduction in the present embodiment.

FIG. 6 is an explanatory diagram showing an address designation state at the time of reverse reproduction in the present embodiment.

[Explanation of symbols]

 1 AD Converter 2 DRAM 3 DRAM Controller 4 DSP 5 DA Converter 7 Read / Write Judgment Circuit 10, 11, 17 NAND Gate 13 RAS / CAS Signal Generation Circuit 14 8-bit Counter 15 Address Counter 151 Read Address Counter 152 Write Address Counter 16, 18 , 20, 25, 42 D flip-flop 19 Data bus 12, 21, 23 40, 41 AND gate 22 EX-NOR gate 24, 26, 44, 45, 47 OR gate 43 Latch circuit 44, 46 Shift register

Claims (3)

[Claims] 1. A read / write control method for a memory for an audio recording / reproducing apparatus for storing audio data, wherein an addressing direction at the time of reading / writing to the memory is such that an array of input audio data is a positive direction. If the array is in the reverse direction and the array is in the opposite direction, the read direction and the write request to the memory occur simultaneously. In this case, the read / write control method of the memory for the audio recording / reproducing apparatus is characterized in that the read priority is given. 2. A read / write control circuit of a memory for an audio recording / reproducing apparatus for storing audio data, wherein the audio data input to the memory is a direction signal indicating whether the array is forward or backward. A read request signal and a write request signal for the memory are input, and when the read request signal and the write request signal are input at the same time, the direction signal is determined, and when the array is in the forward direction, the access to the memory is written. An audio recording / reproducing apparatus comprising a read / write determination circuit which outputs a write enable signal with priority and outputs a read enable signal with read priority when accessing the memory when the array is in the reverse direction. Memory read / write control circuit. 3. The read / write control circuit according to claim 2, further based on the read enable signal and the write enable signal, a switching signal generation that generates a switching signal that is inverted every time a read / write operation is executed. The read / write determination circuit determines the switching signal when the read request signal and the write request signal are input at the same time, and determines whether the read or write operation is performed with priority. A read / write control circuit for a memory for a voice recording / reproducing apparatus, which outputs a write enable signal or a read enable signal for performing the other operation later.