JPH08305399A - Reversal reproduction processing method and processing circuit for voice record reproducing device - Google Patents

Abstract

PURPOSE: To continuously reproduce all voice signals stored in a whole region of a voice memory without interruption by specifying a method by which a voice signal is written in a voice memory, it is read, and a voice signal is reproduced. CONSTITUTION: Read-operation and write-operation are alternately performed in parallel being preceded by read-operation from the highest order address of a DRAM 2 to the lowest order address. When a write-address reaches the lowest order address being the end address, a direction of a write-address is reversed and write-operation of an input voice signal is repeated. In a memory controller 10, in order that read-operation is performed preceding write- operation, voice data written in the lowest order address is first read, after that, voice data newly inputted to this lowest order address is written. Thereby, since all voice data written from the highest order address to the lowest order address are read from the inverse direction, a direction of reversal-reproduced voice data is changed in the order of utterance and the data is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio recording / reproducing apparatus for recording / reproducing an audio signal, and more particularly to a processing method and a processing circuit for an audio memory for 1 × speed reverse reproduction.

[0002]

2. Description of the Related Art In recent years, a VTR has been provided with a function called digest play which allows a natural reproduced sound to be heard during high speed reproduction. This function allows the VTR to hear the voice at a normal speed when it is played back at a high speed such as 3 times or 5 times, and the high speed played audio data is once written in the audio memory. The stored voice data is read from the voice memory and reproduced at a normal speed.

In this case, since the read speed is slower than the write speed, only the readable amount of audio data is stored in the memory, and the remaining reproduction data is discarded without being stored. For example, during the 5 × speed reproduction, the audio data for 15 seconds is reproduced at a high speed for 3 seconds in the normal reproduction, but the data is written to the memory only for 0.6 seconds, and this data is read for 3 seconds at the normal speed. The sound is emitted, and the sound for the remaining 12 seconds is thinned out.

In such a digest play function, not only when the playback direction of the VTR is the forward direction but also when the playback direction is the reverse direction, it is possible to cope with this. In the reverse playback, the audio data input to the memory is reproduced. Since the array is reversed, when writing to the memory as it is,
The address specification direction at the time of read is opposite to that at the time of write,
That is, when writing from the upper address to the lower address, the voice cannot be heard in the order of sound generation unless the lower address is read toward the upper address.

Therefore, conventionally, as shown in FIG. 3, the read / write operation of the memory is performed. FIG. 3 is an example of 5 × speed reverse reproduction, in which the horizontal axis represents time and the vertical axis represents the memory address. The read address is shown by a solid line and the write address is shown by a broken line. As shown in the figure, the write operation is performed from the upper address of the memory toward the lower address in the periods A, B, and C, and the read operation is always continuously performed from the lower address of the memory toward the upper address. In this example, the write periods B and C are each set to ⅕ of the period (D1 + B) of reading from the lowest address LSB of the memory to the highest address MSB.

First, in the period A, high-speed reverse-reproduced voice data is sequentially written from the address P to the lowest address LSB, and the voice data written in this period is D
During the period D1 of the period, data is sequentially read from the lowest address toward the higher address, and when the point c is reached, new input audio data is added to the address lower than the address Q at the point c just read. Lights will start. In parallel with this write operation, the reading of the data written in the address higher than the address Q in the period A is continued. When the writing and reading proceed to reach the point d, the write operation ends, and after the point d, the audio data written in the period B2 is sequentially read.

Thereafter, the same operation is repeated, and the reverse reproduction of the voice is realized so that the silent period cannot be performed.

[0008]

In the conventional high-speed reverse playback, all the reverse voices written from the highest address to the lowest address of the voice memory can be continuously played back in the order of pronunciation. Furthermore, no silence period occurs during reproduction. However, similar to high-speed reverse playback, the audio data is written from the highest address to the lowest address of the audio memory, and the read operation is performed in the opposite direction in parallel with this write operation to achieve 1 × speed reverse playback. Then, the audio data is rewritten while the data in the entire area of the audio memory is being read, so the sounded content is interrupted and it becomes impossible to grasp the sounded content. .

Therefore, as shown in FIG. 4, when the 1 × speed reverse reproduction is performed, it is considered that the read operation and the write operation are performed in a time division manner, and the read operation and the write operation are performed in the opposite directions to the memory address. To be In this way, all the audio data written from the highest address to the lowest address can be read from the lowest address to the highest address in the next read operation, and the voice of There is no break.

However, in the method shown in FIG. 4, since the read operation is stopped during the write operation, this period becomes a silent period.

[0011]

According to the present invention, in a voice recording / reproducing apparatus for writing a voice signal to a voice memory and reading the voice signal to reproduce the voice signal, a limit address indicating an upper limit and a lower limit of the voice memory is set. Input voice signals are sequentially written from one side to the other, and when the limit address is reached, the write address direction is reversed and the write operation of the input voice signal is repeated, and the read operation to the voice memory is written. The operation is performed in the same direction as the operation in parallel, and the read operation for the same address is executed prior to the write operation.

According to the present invention, in an audio recording / reproducing apparatus for writing an audio signal to an audio memory and reading the audio signal to reproduce the audio signal, the address clock is counted and either direction is detected in accordance with an up / down direction signal. A write address counter and a read address counter for respectively updating a write address and a read address, and an address selector for selecting the output of the write address counter and the read address counter at the time of a write operation and sending them to the audio memory, respectively. Supplying the up / down direction signals in the same direction to both of the address counters, and responding to the fact that the content of one of the address counters reaches a limit address of the voice memory, the up / down of both address counters With a control circuit that inverts the direction signal A read operation for a voice memory, comprising: a memory controller that applies an address clock to the read address counter prior to the application of the address clock to the write address clock, and then alternately applies the address clock to the both address counters. And write operation are performed in the same direction in parallel, and
It is characterized in that the read operation for the same address is executed prior to the write operation.

Furthermore, the present invention is characterized in that the read address counter and the write address counter are set to the same start address at the start of the read / write operation.

[0014]

According to the present invention, the input voice signal is sequentially written from one of the limit addresses of the voice memory toward the other, and when the limit address is reached, the write address direction is reversed to perform the write operation of the input voice signal. repeat. Since the read operation to the voice memory is performed in the same direction as the write operation in parallel, the voice signal written from one of the limit addresses to the other is transmitted in the opposite direction from the other of the limit addresses to the voice memory. When you lead the, all are lead and emitted without interruption. Further, in this read period, since the write operation is performed in parallel with the read operation in parallel with the read operation after the end of the read operation, new audio signals sequentially input in this write operation go from the other of the limit addresses to one. Will be stored in the voice memory. By repeating the above operation, all the reverse voices sequentially written between the limit addresses of the voice memory are continuously reproduced in a sounding order without generating a silent period during reproduction.

[0015]

FIG. 2 is a block diagram showing a configuration of an audio recording / reproducing apparatus including an embodiment of the present invention, in which 1 is an AD for converting an input analog audio signal into digital audio data based on a sampling signal fs. A converter 2 is a DRAM for storing the converted audio data, and a DRAM 3 is connected to the DRAM 2 and controls the read / write of the DRAM 2.
The interface circuit, 4 is a DSP that controls the entire audio recording / reproducing apparatus, and 5 is D based on the sampling signal fs.
The DA converter converts the audio data read from the RAM 2 into an analog audio signal.

Write request signal WRE for the DRAM 2
The Q and the read request signal RREQ are output from the AD converter 1 and the DA converter 5, respectively, and are input to the memory controller 10 provided in the DRAM interface circuit 3. And this memory controller 1
0 generates a RAS signal, a CAS signal, and a write enable WEB to the DRAM 2 in response to these request signals to control the read / write operation.

In addition to this, the DARM interface circuit 3 counts the write address clock WACLK and updates the write address, and the write address counter 11 and the read address clock RACLK. A read address counter 12 composed of an up-down counter to be updated, an end address counter 13 for holding a write end address, and a match signal when the contents of the write address counter 11 and the contents of the end address counter are compared and match. A comparator 14 that outputs WAEND, and a selector 15 that selects one of the addresses output from the write address counter 11 and the read address counter 12 according to the write enable signal WEB.
Is provided, and the write address clock WACLK is provided.
The read address clock RACLK is output from the memory controller 10, and the match signal WAEND is input to the memory controller 10.

The start address is set to the write address counter 11 and the read address counter 12, the write end address is set to the end address counter 13, and the up / down direction signals WU / D,
The RU / D is supplied by the DSP 4, and the DSP 4 also inputs the write start signal WSTART for instructing the memory controller 10 to start the write operation and the reference clock signal CLK.

The operation of the embodiment will be described below with reference to FIG. First, before accessing the DRAM 2, the DSP 4
Sets the same highest address as the start address in the two address counters 11 and 12 for writing and reading, and sets the lowest address in the end address counter 13 as the end address. Further, as the up / down direction signals WU / D and RU / D, the same L level signal indicating the down direction is supplied to the two address counters 11 and 12.
To the memory controller 10 and outputs the write start signal WSTART to the memory controller 10.

AD converter 1 and DA converter 5
Generates the request signals WREQ and RREQ at the same timing in synchronization with the sampling signal fs when the conversion process is completed, and the memory controller 10 gives priority to the read operation when the write and read request signals are simultaneously input. Is configured to do so. Therefore, when the DSP 4 outputs the write start signal WSTART after the access is ready as described above, the memory controller 10
Of the two request signals output at the same time, first, the read request signal RREQ is accepted, the write enable signal WEB is set to the L level indicating the disabled state, and the RAS and CAS signals are sent to the DRAM 2. When the write enable signal WEB becomes L level, the selector 15 selects the read address from the read address counter 12 and supplies it to the DRAM 2.

Therefore, 1-byte audio data is read from the highest address of the DARM 2 and sent to the DA converter 5 via the data bus 6, where it is DA converted and output as an audio signal. In this way, when the read operation is executed prior to the write operation and the reading of one byte is completed, the memory controller 10 sends out one clock of the read address clock RACLK, whereby the content of the read address counter is decremented by one. In addition, the read acknowledge signal RAC is sent to the AD converter 5.
K is output.

Next, the memory controller 10 receives the write request signal WREQ, sets the write enable signal WEB to the H level indicating the enabled state, and sends the RAS and CAS signals to the DRAM 2. Therefore, the selector 15 selects the write address from the write address counter 11 and supplies it to the DRAM 2. The AD-converted 1-byte audio data is transferred to the DARM 2 via the data bus 6 and the memory controller 10.
It is written to the highest address which is the start address of. After writing, the write address clock WACLK is sent from the memory controller 10 for one clock, whereby the content of the write address counter is decremented by 1, and the write acknowledge signal WAC is sent to the AD converter 1.
K is output.

In the case of high speed reverse reproduction, the write request signal WR is performed during the period in which the read request signal RREQ is output once because the write operation is performed n times for one read operation.
Although EQ is output n times, in the case of 1 × speed reverse reproduction, since the input / output speed is the same, a read request and a write request are output once during the same period. Therefore, the write address clock WACLK and the read address clock RACLK are alternately supplied from the memory controller 10 to the write address counter 11 and the read address counter 12 in response to the read and write request signals, whereby each address of the DRAM 2 is supplied. For, the read and write operations are alternately repeated.

Therefore, in the period A of FIG. 1, the read operation and the write operation are alternately executed in parallel from the highest address to the lowest address of the DRAM 2 while the read operation precedes. When the write address reaches the lowest address, which is the end address, the contents of the write address counter and the contents of the end address counter 13 match, so the comparator 14 outputs a match signal WAEND, and this signal is output by the memory controller 10 and the DSP 4.
Is supplied to.

The memory controller 10 uses the coincidence signal WA.
When END is input, the write and read operations are stopped and the DSP 4 makes new settings. That is, DSP4
The same lowest address is set as the start address in both address counters, and the end address counter 13
The uppermost address is set as the end address, and the same H level signal indicating the up direction is set as the up / down direction signals WU / D and RU / D.
Send to 1 and 12. Then, after this setting, the write start signal WSTART is output to the memory controller 10.

Since the memory controller 10 performs the read operation prior to the write operation, the audio data written to the lowest address in the period A is first read and then newly input to this lowest address. The audio data is written. Thereafter, the read operation and the write operation are alternately performed in parallel from the lowest address to the highest address, as described above.

Therefore, by these operations, all the voice data written from the highest address to the lowest address in the period A are read in the reverse direction in the period B, so that the voice data reproduced in reverse is The direction will be changed and output in the order of pronunciation.
Moreover, in the period B, new audio data is sequentially written in parallel, so that audio reproduction is executed without a silent period. The same operation is repeated in the subsequent periods such as C and D.

At the highest and lowest addresses indicated by circles, the audio contents change, so it is advisable to mute this part. In addition, since valid audio data is not read in the period A, it is better to mute also in this period. By the way, in the present embodiment, the write and read address counters are always updated alternately. However, in the first state of the read operation, not only the highest or lowest address but also the addresses in the vicinity thereof Read operation is performed continuously, and after that,
The read operation and the write operation may be alternately performed.

[0029]

According to the present invention, all the audio signals stored in the entire area of the audio memory can be continuously reproduced without interruption, and a silent period does not occur during the reproduction. Real 1x speed reverse playback can be realized.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an addressing state during 1 × speed reverse reproduction according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an addressing state during high speed reverse reproduction in the audio recording / reproducing apparatus.

FIG. 4 is an explanatory diagram showing an addressing state during 1 × speed reverse reproduction in a conventional example.

[Explanation of symbols]

 1 AD Converter 2 DRAM 3 DRAM Interface Circuit 4 DSP 5 DA Converter 6 Data Bus 10 Memory Controller 11 Write Address Counter 12 Read Address Counter 13 End Address Counter 14 Comparator 15 Selector

Claims (3)

[Claims] 1. In a voice recording / reproducing apparatus for writing a voice signal to a voice memory and reading the voice signal to reproduce the voice signal, input from one of the limit addresses representing the upper limit and the lower limit of the voice memory toward the other. Audio signals to be sequentially written, and when the limit address is reached, the write address direction is inverted and the write operation of the input audio signal is repeated, and the read operation to the audio memory is performed in parallel with the write operation in the same direction. A reverse reproduction processing method for an audio recording / reproducing apparatus, characterized in that a read operation for the same address is executed prior to a write operation. 2. A voice recording / reproducing apparatus for writing a voice signal to a voice memory and reading the voice signal to reproduce the voice signal, counting an address clock, and writing a write address in either direction according to an up / down direction signal. A write address counter and a read address counter for updating the read address, an address selector for selecting the outputs of the write address counter and the read address counter during the write operation and the read operation, and sending them to the audio memory, and both addresses. The up / down direction signals in the same direction are supplied to the counters, and the up / down direction signals to the both address counters are inverted in response to the content of any one of the address counters reaching the limit address of the voice memory. Control circuit, and the write add A memory controller that applies an address clock to the read address counter prior to the application of the address clock to the address clock, and then alternately applies the address clock to both of the address counters. A reverse reproduction processing circuit of an audio recording / reproducing apparatus, wherein an operation is performed in parallel in the same direction, and a read operation for the same address is executed prior to a write operation. 3. The read address counter and the write address counter are set with the same start address at the start of a read / write operation.
Reverse rotation reproduction processing circuit of the described audio recording and reproducing apparatus.