JPH0736473A - Storage circuit - Google Patents

Abstract

PURPOSE:To access plural addresses of a memory at the same time. CONSTITUTION:A controller 32 controls whether address counters 34 and 35 are used as one counter or as two individual counters. Namely, when the address counters are used as one counter, a memory 31 is accessed after the memory 30 is accessed and when they are used as two counters, two addresses are accessed with the outputs of the two address counters 34 and 35. Consequently, the memories 30 and 31 can be utilized by being switched to one memory or two memories at need.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit used in a delay circuit or the like used for generating surround sound of an audio device.

[0002]

2. Description of the Related Art Conventionally, a surround sound of an audio device is generated by delaying a reproduced sound for a predetermined time and attenuating it. Then, there are a stadium mode, a church mode, etc. as a mode at the time of reproducing, and the reproduced sound delayed by different methods is superimposed.

As a delay circuit used for such an application, there is one shown in FIG. In this circuit, the analog reproduction signal is once converted into digital data by the A / D converter 10 and stored in the memory 12. In addition, the data read from the memory 12 is stored in the D / A converter 1
In 4, it is converted back into analog data. In this circuit, the write time and the read time to the memory 12 are made different, and this difference becomes the delay time.

That is, data is written in the memory 12 in the order of addresses, and the data at a place where the addresses are separated by a predetermined time (data before a predetermined time or a place where the data is written) is sequentially read out, so that a predetermined delay time is obtained. You can get a signal.

However, in the case of the church mode, for example, a reproduced sound having a large number of echoes like a church is required.
Therefore, a delay time due to a large number of reverberations is required, and it is necessary to generate a signal obtained by delaying the signal to which the delayed signal is added and further superimpose it. Therefore, delayed signals of a plurality of signals are required. On the other hand, in the stadium mode, a signal with a large delay time is required because the echo in a wide space must be created. Therefore, in the church mode, a plurality of delay circuits are required, a plurality of memories are required, and in the stadium mode, a large capacity memory is required. Therefore, a plurality of large-capacity memories are provided to support all modes.

[0006]

However, since the delay time is short in the church mode, the capacity of the memory does not need to be so large. Further, in the stadium mode, only one memory is required. Therefore, there is a problem that an unnecessary portion of the memory is generated depending on the mode and the memory cannot be effectively used.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory circuit capable of efficiently obtaining a plurality of delayed signals and a signal with a large delay time. To do.

[0008]

A memory circuit according to the present invention controls a memory for storing data, an address determining means for counting a predetermined clock and determining an access address to the memory, and controlling the address determining means. And a control means for controlling whether to output a plurality of addresses or a single address, and it is possible to switch between sequentially accessing a plurality of locations in the memory and sequentially accessing a single location. Characterize.

[0009]

In this way, the address determining means accesses a plurality of addresses or a single address under the control of the control means. Therefore, by simultaneously accessing a plurality of addresses, different addresses of the memory can be accessed at the same time, and a plurality of memories can be used in parallel. Further, by accessing a single address, one memory can be used as a large capacity memory. As a result, the memory can be used as a plurality of memories having a small capacity in the church mode, and the memory can be used as a memory having a large capacity in the stadium mode. Therefore, the memory capacity can be reduced by using the memory effectively.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the storage circuit of the embodiment, in which two memories 30 and 31 store data. DRAMs, for example, are used as the memories 30 and 31. The controller 32 stores the input 1-system or 2-system digital data in the memory 3
Supply to 0 and 31. Further, two address counters 34 and 35 are provided to determine an access address for the memories 30 and 31, and the values of the address counters 34 and 35 are supplied to the address decoders 36 and 37 via an address bus. The controller 32 sets the input data on the data bus to write the input data to the corresponding addresses in the memories 30 and 31. When the controller 32 receives the input data of two systems and writes them in the memories 30 and 31 in parallel, the address counters 34 and 35 individually output the access addresses and the controller 32 outputs the input data of one system. When receiving and sequentially writing data in the memories 30 and 31, the address counters 34 and 35 output serial access addresses.

The controller 32 has a mode of receiving data of one system and supplying it to the memory 36 or 37, and a mode of receiving data of two systems and supplying these to the memories 36 and 37, respectively. There is.

For example, when writing data of one system, the outputs of the two address counters 34 and 35 are serially used, and the memories 30 and 31 are used as one memory. In this case, the output B1 of the address counter 34
Depending on B2 and B3, the address "000" of the memory 30
"111" (8 addresses) is designated, and then the output of address counter 35 B4, B5, B6 causes memory 30
Addresses "000" to "111" (8 addresses) are designated, and the data of one system output from the controller 32 is sequentially written therein. Therefore, the memories 30 and 31 function as a memory having an address of 16 bits.

When data of one system is written, the outputs of the two address counters 34 and 35 are used sequentially (serially) and the two memories 30 and 31 are used as one memory. That is, after the addresses "000" to "111" (8 addresses) of the memory 30 are designated by the outputs B1, B2, B3 of the address counter 34 and data is output from there, the outputs B4, B5, B6 of the address counter 35 are output. Causes the address "0" of the memory 30 to
00 "to" 111 "(8 addresses) are designated and data is output from here. Therefore, both memories 30, 31 are
It functions as one memory and the output data is also one system. Note that the specific number of bits here is small for the sake of explanation.

By using the memories 30 and 31 as one memory in this way, it is possible to store the data for a longer time, and the delay time can be lengthened. Therefore, it is effective in the stadium mode and the like.

On the other hand, when writing data of two systems, the outputs of the two address counters 34 and 35 are used in parallel, and the memories 30 and 31 are used as two separate memories. In this case, the output of the address counter 34 B1, B2, B3 causes the address "00
0 "to" 111 "(8 addresses) are designated, and the output of the address counter 35 B4, B5, B6 causes the memory 30
Addresses “000” to “111” (8 addresses) are designated, and the two systems of data output from the controller 32 are written therein in parallel. Therefore, the memories 30, 31
Each function as a memory with an address of 8 bits.

When the data of two systems are written, the outputs of the two address counters 34 and 35 are used in parallel, and the memories 30 and 31 are used as two memories. In this case, the output B of the address counter 34
1, B2, B3, the address of the memory 30 "00
At the same time as specifying 0 to 111 (8 addresses),
By the outputs B4, B5, B6 of the address counter 35,
Addresses "000" to "111" (8 addresses) of the memory 30 are designated, and read data from both memories 30 and 31 are output in parallel.

As described above, when the memories 30 and 31 are used as two memories, a plurality of input signals can be separately written into each memory and separately output. Therefore, it is suitable for generating a plurality of delayed signals, and is suitable for the church mode, for example.

Since the data is output serially or in parallel from the memories 30 and 31, the output is
It is output via the selection unit 38. That is, the memory 30,
The outputs of 31 are performed sequentially (serial) or separately (parallel), and both outputs are output via the selection unit 38.
The selection unit 38 controls whether the outputs from the memories 30 and 31 are output in parallel as they are or the outputs from the memories 30 and 31 are sequentially selected and output according to the output from the controller 32.

The read address when reading from the memories 30 and 31 is smaller than the write address by a predetermined value. That is, the data is read from the address written in the predetermined time. For this purpose, the address buses from the counters 34 and 35 are provided with conversion units 40 and 41, in which a predetermined number is added to the write address to generate an address which was written a predetermined time ago. . Note that this conversion can be performed by inverting predetermined bits "1" and "0". Then, in the case of reading, this conversion unit 40,
The data is read from the address converted by 41, and in the case of writing, the data is written in the address which is not converted.

In this way, it is possible to obtain data that is far from the currently written data.
Then, by using the memories 30 and 31 as one memory, data with a long delay time can be obtained, and the data in the stadium mode can be obtained by subjecting the data to a predetermined attenuation and superimposing the data on the audio signal which has not been delayed. You can get a signal. On the other hand, the memory 30,
By using 31 as two memories, the two audio signals that are input and the signal in which the delay signal has already been superimposed are separately written into the memories 30 and 31, and read separately, so that two echo signals are generated. Obtainable. Therefore, a reproduction mode having two reverberant sounds can be achieved by subjecting the obtained reverberant signal to predetermined attenuation and superimposing it on an audio signal that is not delayed.

FIG. 2 shows the configuration of another embodiment, which has a memory 50, a controller 52, an address counter 60, and an address decoder 62.
Two outputs are provided. Then, the selection means 64 appropriately switches the input and output of the two systems of data.

FIG. 3 shows an example of the configuration of the selection means 64. In this way, the selection means 64 includes two A / D converters 70,
72, two D / A converters 74 and 76, and four changeover switches 80, 82, 84 and 86. A /
The D converter 70 converts the input 1 into digital data and A /
The D converter 72 converts the input 2 into digital data. Further, the D / A converter 74 converts the read data into an analog signal to obtain a signal of output 1, and the D / A converter 76 converts the read data into an analog signal to obtain a signal of output 2.

When writing and reading one system of audio input signal (input 1), the switch 80 is used.
Down and 86 down. Since the switch 80 is set to the lower position, no signal is input to the A / D converter 72. Moreover, since the switch 86 is set to the lower position, no signal is output to the output 2. Then, by setting the switch 82 upward, the input 1 becomes the A / D converter 70.
Through the columns of “1” to “8” and “9” of the memory 50.
It is supplied to the column of "16". Then, in accordance with the signal from the address decoder 62, “1” to “16” of the memory 50.
Are sequentially designated, the signal of the input 1 is sequentially written to "1" to "16" of the memory.

When the data of "1" to "8" is read by the switch 84 by the signal from the predetermined address decoder 62, the data of "9" to "16" is read. The signal from here is output as an analog signal by the D / A converter 74 by setting it to the lower side when the signal is present.

On the other hand, when writing and reading two audio signals (input 1 and input 2), the switch 80
Is set up, 82 is set down, 84 is set up, and 86 is set up. By setting the switch 80 to the upper side and the switch 82 to the lower side, the input 1 is converted into a digital signal by the A / D converter 70 and supplied to "1" to "8" of the memory 50, and at the same time, the input 2 is input. Is converted into a digital signal by the A / D converter 72 and supplied to "9" to "16" of the memory 50. Therefore, by the signal from the address decoder 62, the data from the input 1 is written in parallel to "1" to "8" of the memory 50, and the input 2 is written to "9" to "16" of the memory 50 in parallel.

Further, since the switch 84 is set to the upper position, the A / D converter 74 is always loaded with "1" of the memory 50.
The data of "8" is supplied, which is converted into an analog signal and obtained at the output 1. Since the switch 86 is set to the upper position, the data "9" to "16" in the memory 50 is always supplied to the A / D converter 76, and this is converted into an analog signal and obtained at the output 2. Therefore, according to the signal from the address decoder 62, “1”-
These read data are output 1 and output 2 by being designated in parallel with “8” and “9” to “16”.
Obtained in parallel with.

By making writing and reading different for one column of addresses, for example, the delay time differs by the time corresponding to this. Note that the conversion unit 61 obtains a desired delay time by differentiating the write address and the read address by a predetermined amount, as in the above-described embodiment.

[0028]

As described above, according to the storage circuit of the present invention, the memory can be divided into one or a plurality of pieces for use by switching. Therefore, the memory can be divided to obtain a plurality of signals with a small delay time, and one memory can be used to obtain a signal with a long delay time.
Therefore, it is possible to effectively use the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a memory circuit.

FIG. 2 is a block diagram illustrating another configuration example of a memory circuit.

FIG. 3 is a diagram showing a configuration of a memory circuit selection 64.

FIG. 4 is a block diagram showing a schematic configuration of a delay circuit.

[Explanation of symbols]

 30, 31, 50 Memory 32, 52 Controller 34, 32, 35, 60 Address Counter 36, 37, 62 Address Decoder 38, 64 Selector

Claims (1)

[Claims] 1. A memory for storing data, an address deciding means for counting a predetermined clock and deciding an access address for the memory, and controlling the address deciding means to output a plurality of addresses or a single address. And a control means for controlling whether or not to output the address of the memory circuit, and it is possible to switch between sequentially accessing a plurality of locations of the memory and sequentially accessing a single location of the memory circuit.