JPH08234700A - Liquid crystal display device and liquid crystal driving method - Google Patents

Abstract

PURPOSE: To provide a liquid crystal display device capable of displaying an image having multi-level and high quality. CONSTITUTION: A display line number is counted by a line counter 12, and a frame number is counted by a frame counter 13. Values corresponding to the count values of the line counter 12 and the frame counter 13 are subtracted from the image data of six bits read out of an image storage device 11, and the obtained value is multiplied by 1/8 to obtain the image data of three bits. A voltage corresponding to the obtained image data of three bits is applied to a liquid crystal display element 16. The image data the same for an even numbered line and an odd numbered line is read out of the image storage device 11 to be displayed. Thus, by synthesizing displays of two lines and four frames, the gradation instructed by the image data of six bits is displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a liquid crystal driving method for displaying a gradation or a color according to an applied voltage, and more particularly to a liquid crystal display device and a liquid crystal for displaying a multi-gradation image in a pseudo manner. It relates to a driving method.

[0002]

2. Description of the Related Art FIG. 8 shows the basic structure of a conventional liquid crystal display device. The liquid crystal display device shown in FIG. 8 displays 8 (2) pixels on each dot of the liquid crystal display element 82 by the liquid crystal driver 81 in order to display an image of 8 gradations designated by 3-bit image data.
³ ) Apply one of the ^three types of voltage. With such a configuration, when the liquid crystal display element 82 is a color liquid crystal display element, 8 × 8 × 8 = 512 colors can be displayed.

In the liquid crystal display device having such a structure,
In order to increase the number of display gradations and the number of display colors, the number of bits of image data may be increased and the number of effective voltages applied by the liquid crystal driver 81 to the liquid crystal display element 82 may be increased. However, in this method, for example, PWM (pulse width modulation)
In the case of the method, a large number of pulse signals having different pulse widths must be generated. Also, PAM (pulse amplitude modulation)
In the case of the law, it is necessary to generate many different voltages. Therefore, the configuration of the liquid crystal driver 81 becomes complicated,
In addition, power consumption increases.

In order to solve such a problem, as shown in FIG. 9, a method of displaying a multi-gradation image by visually synthesizing display images of a plurality of frames (combining by a residual image phenomenon) is also proposed. ing.

In the configuration shown in FIG. 9, even number of frames is 4
The subtraction circuit 91 decrements the bit image data by -1, and the divider 92 divides it by 1/2 (shifts to the LSB side by 1 bit) to obtain 3-bit image data. Then, the effective voltage corresponding to the 3-bit image data is applied to the liquid crystal display element 9
3 In an odd frame, the same 4-bit image data is halved to 3 bits, and an effective voltage corresponding to this is applied to the liquid crystal display element 93.

According to this driving method, by applying 8 kinds of effective voltages to the liquid crystal display element 93, a pseudo 16 ×
16 × 16 = 4096 colors can be displayed.

[0007]

However, even with this method, the number of display gradations is small, and when a single gradation such as a still image is displayed, the boundary portion of the gradation becomes clear, and the display quality is There is a problem that

The present invention has been made in view of the above situation, and an object of the present invention is to provide a liquid crystal display device and a liquid crystal driving method capable of displaying a high quality image with multiple gradations.

[0009]

In order to achieve the above object, a liquid crystal display device according to a first aspect of the present invention is a liquid crystal display device having a plurality of lines, and image data for storing i-bit image data. A storage unit, a line counter that counts the number of lines of the display image of the liquid crystal display element and outputs K-bit data, and a number of frames of the display image of the liquid crystal display element that outputs L-bit data. A frame counter, bit conversion means for converting the image data read from the image data storage means into j-bit data according to the output data of the line counter and the frame counter, and liquid crystal display based on the bit conversion means. It is composed of a driver that drives the elements, and the gradation specified by the image data is 2 ^L lines and 2 ^K frames. Characterized by expressing.

In order to achieve the above object, the second aspect of the present invention
In the liquid crystal driving method for displaying the gradation designated by the i-bit image data by synthesizing images of adjacent K dots and L frames in one frame, The image data is converted into j bits, and an effective voltage corresponding to the j bits of image data is applied to the liquid crystal of 2 ^K line dots in a 2 ^L frame period.

[0011]

With this structure, the image designated by the image data is displayed by combining the display image of 2 ^K lines and 2 ^L frames. Therefore, a multi-tone image can be displayed in a state where the types of effective voltage applied to the liquid crystal of the liquid crystal display element are limited. That is, the same effect as that obtained by expanding the j-bit image data on the K + L-bit time axis can be obtained, and the image instructed by the i-bit original image data can be displayed in a pseudo manner.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display device and a driving method according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the liquid crystal display device of this embodiment. As shown in the figure, this liquid crystal display device includes an image data storage device (memory) 11 for storing 6-bit image data,
A 1-bit line counter 12 for counting the number of lines in the writing state (the number of lines in the display image);
A 2-bit frame counter 13 for counting the number of frames, a bit conversion device 14 for converting each image data read from the image data storage device 11 into 3-bit image data, and a bit conversion device 14 are supplied. Three
It is composed of a liquid crystal display device 16 and a liquid crystal driver 15 which selects one of eight types of effective voltages according to bit image data and applies the selected voltage to the liquid crystal display device 16.

Number of lines of the liquid crystal display element 16 (number of scanning lines)
Is m, the image data storage device 11 stores m / 2 lines of image data, and each image data indicates the gradation of two dots at the same position on the adjacent even line and odd line. The line counter 12 has "0" on even-numbered lines and has "1" on odd-numbered lines.
The frame counter 13 displays "0" at any 0th frame.
0 ", first frame is" 01 ", second frame is" 1 "
0 ", and takes a value of" 11 "in the third frame.

The bit conversion device 14 has the configuration shown in FIG. In FIG. 2, the decoder 21 uses 0 to 7 (“0” based on the 1-bit data from the line counter 12 and the 2-bit data from the frame counter 13).
3-bit selection data indicating which of the constant data "00" to "111" is selected is output. The multiplexer 22 selects and outputs the constant data according to the selection data.

FIG. 3 shows the relationship between the input of the decoder 21 and the constant data selected and output by the multiplexer 22.
As shown in the figure, the constant data is selected so as to change discontinuously with respect to the change of the 3-bit data input to the decoder 21.

The subtraction circuit 23 is provided in the image data storage device 11
Subtracting the 3-bit constant data supplied from the multiplexer 22 from the 6-bit image data supplied from
The obtained 6-bit image data is output. Divider 24
Is the 1/8 of the 6-bit image data from the subtractor 23.
(Shift to 3 bits LSB side) and convert to 3 bits,
Output.

The liquid crystal display element 16 is a color liquid crystal display element having R, G and B dots, and may be either a simple matrix type liquid crystal display element or an active matrix type liquid crystal display element. The liquid crystal driver 15 selects one corresponding to the image data from the eight types of effective voltages in accordance with the 3-bit image data supplied from the bit conversion device 14 and sets the liquid crystal of the corresponding dot of the liquid crystal display element 16. Apply.

Next, the operation of the liquid crystal display device having the above structure will be described. For example, at the display timing of the 0th line (even line) of the 0th frame, the count value of the line counter 12 is “0”, the count value of the frame counter 13 is “00”, and the multiplexer 22 outputs “111”. . The subtractor 23 subtracts “111” from each 6-bit image data read from the image data storage device 11. The divider 24 outputs the output of the subtractor 23 to the 3-bit LS.
It is shifted to the B side and supplied to the liquid crystal driver 15. The liquid crystal driver 15 applies the effective voltage corresponding to the 3-bit image data output from the bit converter 14 to the liquid crystal of the corresponding dot of the liquid crystal display element 16.

For example, when the 6-bit image data read from the image memory 11 is "101010", the output of the subtractor 23 is "100011" and the subtractor 24
Is output as "100". Therefore, the liquid crystal driver 15
Applies an effective voltage for displaying the fourth gradation to the corresponding dot on the 0th line of the liquid crystal display element 16.

Subsequently, at the display timing of the first line (odd line) of the 0th frame, the count value of the line counter is "1" and the count value of the frame counter is "0".
Then, the multiplexer 22 outputs “011”. The image data storage device 11 again reads the same image data as the image data read for the 0th line, and sequentially outputs the read image data. The subtractor 23 subtracts “011” from each 6-bit image data read from the image data memory 11. The divider 24 shifts the output of the subtractor 23 by 3 bits to the LSB side. The liquid crystal driver 15 applies an effective voltage corresponding to 3-bit image data to the liquid crystal of the corresponding dot of the second line of the liquid crystal display element 16.

Similarly to the above, the 6-bit image data read from the image data storage device 11 is "10101".
When set to "0", the output of the subtractor 23 becomes "100111" and the output of the subtractor 24 becomes "100". Therefore,
The liquid crystal driver 15 applies an effective voltage for displaying the fourth gradation to the corresponding dot of the liquid crystal display element 16.

Subsequently, at the display timing of the second line, the count value of the line counter 12 becomes "0" again. After that, in the same way, 2 of even line and odd line
The same image is displayed line by line.

When the scanning progresses and the display timing of the 0th line of the 1st frame comes, the count value of the line counter 12 becomes "0", the count value of the frame counter 13 becomes "01", and the multiplexer 22 sets "101". Output. The subtractor 23 subtracts “101” from each 6-bit image data read from the image data storage device 11, and the divider 24 shifts the output data of the subtractor 23 to the LSB side by 3 bits, and the liquid crystal driver 15 applies an effective voltage corresponding to image data to each dot. Therefore, when the 6-bit image data is “101010”, the subtracter 2
The output of 3 becomes "100101", and the output of the subtractor 24 becomes "100". Therefore, the liquid crystal driver 15 applies an effective voltage for displaying the fourth gradation to the corresponding dot of the liquid crystal display element 16.

The same drive is performed for the first and subsequent lines of the first frame, and for the second and third frames. In the fourth frame, the count value of the frame counter 13 becomes "00", and the same driving as in the 0th frame is performed.

As described above, in the liquid crystal display device of this embodiment, as shown in FIG. 4, (1) 7 is subtracted from the image data for the dots of the even lines of the 0th frame, and it is set to 1
The effective voltage corresponding to the image data which is / 8 is applied, 3 is subtracted from the image data to the dots of the odd-numbered lines, and the effective voltage corresponding to the image data which is ⅛ is applied. 5 is subtracted from the image data and the effective voltage corresponding to 1/8 of the image data is applied to the dots of the even lines of one frame, and 1 is subtracted from the image data to the dots of the odd lines. An effective voltage corresponding to the image data obtained by ⅛ is applied, and (3) 6 is subtracted from the image data to the dots of the even lines of the second frame, and the dot is obtained by ⅛ corresponding to the image data. An effective voltage is applied to the dots in the odd-numbered lines, 2 is subtracted from the image data, and an effective voltage corresponding to the image data obtained by ⅛ is applied. (4) The dots in the even-numbered lines in the third frame The image 4 is subtracted from over data, it 1/8
The effective voltage corresponding to the image data is applied, and the dots of the odd-numbered lines are applied with the effective voltage corresponding to the image data obtained by subtracting 0 from the image data and ⅛.

In this way, as shown in FIG. 5, it is possible to display two dots on two adjacent lines and a gray scale designated by 6-bit image data in four frames. For example, when the image data is “101010”, the dot 1 in the 0th frame is “100” and the dot 2 is
The gradation corresponding to "100" is displayed on the screen, "100" for dot 1 and "101" for dot 2 in the first frame.
, The gradation corresponding to “100” is displayed on the dot 1 of the second frame, the gradation corresponding to “101” is displayed on the dot 2 of the second frame, and “100” is displayed on the dot 1 of the third frame.
A gradation corresponding to “101” is displayed on the dot 2.
Then, these display images are visually combined by the observer, and the combined gradation is displayed.

As described above, in this embodiment, the voltage applied to the liquid crystal display element is set to 3 bits, and 3 lines are secured on the time axis by lines and frames. Therefore,
As in the conventional case, 6 bits of color can be displayed while the effective voltage applied to the liquid crystal remains in 8 steps corresponding to 3 bits.

Since the liquid crystal display device of this embodiment has the image data storage device 11, the frame frequency can be increased by increasing the reading speed from the image data storage device 11. For example, 1 / the frame period (field period) of a general television
Image data for 4 frames can be read out in 60 seconds, and even if 4 frames are used, flicker can be reduced. Further, when converting the bit number of the image data, a numerical value that changes discontinuously with respect to the change of the count value of the line counter 12 and the frame counter 13 is subtracted from the image data, so that a pseudo contour is generated. Can be prevented.

Further, when displaying the data of less than half the number of lines of the liquid crystal display device, normally, the same data is displayed twice (2 lines). Therefore, according to this embodiment, the vertical resolution does not decrease. .

Next, a specific structural example of the liquid crystal display device shown in FIG. 1 will be described with reference to FIG. In FIG. 6, the liquid crystal display element 31 is composed of a simple matrix type liquid crystal display element having _m scanning electrodes X _{0 to} X _m−1 and n signal electrodes Y _{0 to} Y _n−1 . In this embodiment, dots of the same color are arranged at the same positions on the even line and the odd line which are adjacent to each other.

The image memory 32 stores 6-bit image data indicating the display gradation of each dot of the liquid crystal display element 31. The image memory 32 stores image data (gradation data) for m / 2 lines. The display control circuit 33 is D
6-bit image data from the image memory 32, including a circuit for reading image data stored in the image memory 32, a line counter, a frame counter, a bit conversion device, a timing control circuit, etc. Is read out, converted into 3-bit image data D _{0 to} D ₂ and output, and further a frame signal SA and a shift clock SB are output.

The scan electrode drive circuit 35 is the display control circuit 3
7C according to the frame signal SA from FIG.
As illustrated in (D), selection signals whose polarities are inverted are sequentially applied to the scan electrodes X _{0 to} X _m−1 of the liquid crystal display element 31 for each frame.

The signal electrode drive circuit 36 includes a gradation signal generation circuit 37, a shift register 38, and a data latch circuit 3.
9, a gradation signal synthesizing circuit 40, a level shifter 41,
It is composed of a driver 42.

The gradation signal generating circuit 37 is arranged so that the frame signal S
According to A, pulse signals P _{0 to} P ₇ having pulse widths different from each other and whose polarities are inverted for each frame are output in each horizontal scanning period. FIG. 7E illustrates the pulse signal P ₅ .
The shift register 38 has a digit number corresponding to the number n of signal electrodes of the liquid crystal display element 31, and sequentially outputs a sampling signal which becomes H level for one dot period in accordance with the shift clock signal SB from the display control circuit 33. The data latch circuit 39 sequentially latches the 3-bit image data D _{0 to} D ₂ indicating the display gradation of each dot supplied from the display control circuit 41 in accordance with the sampling signal output from the shift register 38.

The gradation signal synthesizing circuit 40 outputs eight pulse signals P _{0 to} P ₇ supplied from the gradation signal generating circuit 37 according to the image data D _{0 to} D _{2 of} each dot latched by the data latch circuit 39. Any one is selected and output. The level shifter 41 converts the voltage signal of the signal processing system output from the gradation signal synthesizing circuit 40 into a voltage signal of the driving voltage system applied to the liquid crystal display element 31, and outputs the voltage signal. Driver 42
Applies a drive voltage to the signal electrodes Y _{0 to} Y _n−1 according to the output signal of the level shifter 41 and the control signal from the display control circuit 33.

Next, the operation of the liquid crystal display device having the above structure will be described. At the timing of the 0th frame and 0th horizontal scanning period, the count value of the line counter in the display control circuit 33 is “0” as shown in FIG. 7A, and the count value of the frame counter is as shown in FIG. 7B. It is "00". The display control circuit 33 sequentially reads the image data for the 0th line stored in the image memory 32, subtracts “111” from the read image data, shifts this by 3 bits to the LSB side, and outputs it. The output data D _{0 to} D ₂ are sequentially stored in the data latch circuit 39 according to the shift clock SB.

When the first horizontal scanning period starts, the scan electrode driving circuit 35 causes the 0th scan electrode X ₀ of the liquid crystal display element 31.
Then, as shown in FIG. 7C, a selection signal is applied. Also,
The image data latched by the data latch circuit 39 in the 0th horizontal scanning period is latched in parallel by the gradation signal synthesis circuit 40.

The gradation signal generating circuit 37 includes the display control circuit 3
In accordance with the control signal SA supplied from the No. 3, pulse signals P _{0 to} P ₇ having different pulse widths whose polarities are inverted for each frame are output as illustrated in FIG. 7 (E). The gradation signal synthesizing circuit 40 generates the gradation signal P according to the latched image data.
_The corresponding one is selected from _{0 to} P ₇ and output. The gradation signals P _{0 to} P ₇ output from the gradation signal synthesizing circuit 40 are signals having a signal processing system voltage, and the level shifter 41 converts this into a signal having a driving system voltage. The driver 42 is the level shifter 4 supplied from the display control circuit 33.
The pulse signal supplied from _{No. 1} is applied to the signal electrodes Y _{0 to} Y _{m-1 as shown} in FIG. At this time, the selection signal is applied to the scan electrode X ₀ , and the voltage shown in FIG. 7G is applied to the liquid crystal of each dot on the 0th line.

On the other hand, the display control circuit 33 sequentially reads the same image data as in the 0th scanning period from the image data memory 32. At this point, as shown in FIGS. 7A and 7B, the line counter value is "1", the frame counter value is "00", and the multiplexer 32 is "011".
Is output. The subtractor 33 subtracts "011" from each image data read from the image data memory 11, and the divider 34 shifts the output of the subtractor 33 to the LSB side by 3 bits and outputs it. The output data D _{0 to} D ₂ are sequentially latched by the data latch circuit 39 according to the output of the shift register 38.

When the second horizontal scanning period is disclosed, the scan electrode driving circuit 35 applies a selection signal to the first scan electrode X ₁ as shown in FIG. 7D, and the signal electrode driving circuit 36 makes the data latch circuit. A voltage signal having a pulse width corresponding to the image data stored in 39 is applied to each of the signal electrodes Y _{0 to} Y _n-1 .

When the scanning progresses and the first frame is reached, the count value of the frame counter becomes "01", and 6-bit image data is converted into 3-bit image data according to this value. Further, as shown in FIGS. 7C to 7G, the polarities of the voltages applied to the scan electrodes X _{0 to} X _m and the signal electrodes Y _{0 to} Y _n-1 are inverted. The other driving methods are the same as those in the 0th frame. After that, the same operation is repeated.

As described above, according to the configuration of FIG. 6, by applying eight kinds of pulse voltages to the scan electrodes X _{1 to} X _m-1 of the liquid crystal display element 31, the instruction is given by 6-bit image data. The displayed gradation can be displayed.

In the above embodiment, the number of bits of the line counter is 1, the number of counts of the frame counter is 2, and the gray scale indicated by 6-bit image data is 2.
(2 ¹ ) lines and 4 (2 ² ) frames were combined and displayed. However, these values are arbitrary. For example, the line counter may be set to 2 bits, the frame counter may be set to 1 bit, and the grayscale indicated by the 6-bit image data may be displayed by combining the display of 4 lines and 2 frames.

Also, the number of bits of the original image data is i, the number of bits of the image data after bit conversion is j, the number of bits of the line counter is K, and the number of counts of the frame counter is L.
(I-K-L = j, i, K, L, and j are all positive integers), and the gradation designated by the original image data of i bits is combined with 2 ^K lines and 2 ^L frames. You may display it. In this case, the constant data is set to any of 0 to 2 ^{K + L} -1. The constant data may have other values. The correspondence shown in FIG. 3 can be changed arbitrarily. However, it is desirable to use a numerical value that changes discontinuously with respect to changes in the count values of the line counter and the frame counter.

The structure of the liquid crystal display element 31 is an example, and an active matrix type may be used. Although an example of a color display element is shown in the above embodiment, the present invention can be applied to a monochrome type liquid crystal display element.

[0046]

As described above, according to the present invention, the number of bits is substantially expanded on the time axis, the number of bits of image data actually applied to the liquid crystal is reduced, and many gradations are obtained. Can be displayed.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of the bit conversion device shown in FIG.

FIG. 3 is a diagram for explaining operations of the decoder and the multiplexer shown in FIG.

FIG. 4 is a diagram for explaining the operation of the liquid crystal display device shown in FIG.

FIG. 5 is a diagram illustrating a method for displaying a gray scale designated by 6-bit image data.

6 is a diagram showing a specific configuration example of the liquid crystal display device shown in FIG.

7A to 7G are timing charts for explaining the operation of the liquid crystal display device shown in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional liquid crystal display device.

FIG. 9 is a diagram showing a configuration and an operation of a conventional liquid crystal display device.

[Explanation of symbols]

11 ... Image data storage device, 12 ... Line counter,
13 ... Frame counter, 14 ... Bit conversion device, 1
5 ... Liquid crystal driver, 16 ... Liquid crystal display element, 21 ... Decoder, 22 ... Multiplexer, 23 ... Subtraction circuit, 2
4 ... Divider, 21 ... Liquid crystal display element (liquid crystal panel), 2
2 ... Image memory, 23 ... Display control circuit, 25 ... Scan electrode driving circuit, 26 ... Signal electrode driving circuit, 27 ... Grayscale signal generating circuit, 28 ... Shift register, 29 ... Data latch circuit, 40 ... Gradation signal synthesizing circuit, 41 ... Level shifter, 42 ... Driver

Claims (8)

[Claims] 1. A liquid crystal display device having a plurality of lines, image data storage means for storing i-bit image data, and counting the number of lines of a display image of the liquid crystal display device,
A line counter that outputs K-bit data, a frame counter that counts the number of frames of a display image on the liquid crystal display element, and outputs L-bit data, and the image according to the output data of the line counter and the frame counter. Gradation designated by the image data, which is composed of a bit conversion unit that converts the image data read from the data storage unit into j-bit data and a driver that drives the liquid crystal display element based on the bit conversion unit. Liquid crystal display device characterized by expressing 2 ^L lines and 2 ^K frames. 2. The bit converting means subtracts a value corresponding to K + L bit data from the line counter and frame counter from the i-bit image data, and an i-bit output to the subtracting means. Image data 2 ^{K + L}
2. The liquid crystal display device according to claim 1, further comprising: a division circuit that divides by 1 to convert the image data into j-bit image data. 3. The subtracting means subtracts a value that changes discontinuously from the i-bit image data in response to a change in K + L bit data from the line counter and the frame counter. Item 3. The liquid crystal display device according to item 2. 4. The liquid crystal display device according to claim 2, wherein the subtracting means subtracts any one of the values 0 to 2 ^{K + L} −1 from the i-bit image data. . 5. The image data storage means comprises means for repeatedly reading the same image data for 2 ^K lines of the liquid crystal display element.
The liquid crystal display device according to 3 or 4. 6. The liquid crystal display according to claim 5, wherein the image data storage means stores image data for m / 2 ^K lines, where m is the number of lines of the liquid crystal display element. apparatus. 7. A liquid crystal driving method for displaying a gradation designated by i-bit image data by synthesizing images of adjacent K dots and L frames in one frame, wherein the i-bit image data is j A method for driving a liquid crystal, wherein the liquid crystal is converted into bits, and an effective voltage corresponding to the j-bit image data is applied to the liquid crystal of 2 ^K line dots in a 2 ^L frame period. 8. A line number and a frame number of a display image of a liquid crystal display element are counted, a value which changes discontinuously corresponding to the count value is subtracted from the i-bit image data, and the image after the subtraction is performed. 8. The data is divided by a predetermined number to be converted to j-bit image data.
The method for driving a liquid crystal as described in.