JPH0822431A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To send and receive data to and from a peripheral device at a high speed by informing a CPU of a bus error according to a prescribed address number unless the address number is correct, and receiving an actuation signal from an address check part when the address number is correct and accessing the peripheral equipment corresponding to the address number by an access control part. CONSTITUTION:An address check part 16 inputs the address number outputted by the CPU 10 and checks whether or not the address number of a long word unit is correct according to the prescribed address number of the long word unit. When the address number is not correct, the CPU 10 is informed of the bus error, but when the address number is correct, an actuation signal is outputted in long word units. The access control part 15 once receiving the actuation signal accesses the I/O module 2 of the peripheral equipment corresponding to the address number outputted by the CPU 10. Consequently, data can be sent to and received from the I/O module 2 at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device for exchanging data in a data unit different from that of a peripheral device, and more particularly to an arithmetic processing device capable of exchanging data at high speed.

[0002]

2. Description of the Related Art A programmable controller is a CPU
When the module accesses the I / O module via the bus, the CP depends on the data width handled by the I / O module.
Since the address number output by the CPU of the U module is different, it is necessary to check the address output by the CPU in order to prevent malfunction. A configuration of such a device and a programmable controller is shown in FIG. In the figure, 1
Is a CPU module which is an arithmetic processing unit, and 2 is an I / O module which is a peripheral device, which exchanges data with an external device and also exchanges data with the CPU module 1 via the bus 3.

In the CPU module 1, 10 is a CP
U and 11 are ROMs (Read Only Memory), CPU
A program executed by 10 is stored. 12 is R
It is an AM (Random Access Memory) and has the information of the I / O module 2 and the work area of the CPU 10. 13 is a word / long setting register for the CPU 10
Holds the setting whether the data to be accessed by is in word units (16 bits) or in longword units (32 bits). Here, "0" is held in word units, and "1" is held in longword units. Reference numeral 14 is an address check unit, which inputs the address number output from the CPU 10 when the word / long setting register 13 is set in units of long words, and checks whether the address number is correct,
If it is not correct, notify the CPU 10 of the bus error,
When it is correct, a start signal is output. Reference numeral 15 is an access control unit, and when the setting of the word / long setting register 13 is a word unit, a word unit access is performed by the CPU.
10 to the I / O module 2 corresponding to the address number output by the CPU 10. Also, in the longword unit, the start signal is received from the address check unit 14 and the I / O module 2 corresponding to the address number output by the CPU 10 is received. Access in units of longwords. I / O module 2
In the figure, 20 is a RAM that stores 16-bit data. An input / output unit 21 receives data from an external device and stores it in the RAM 20, or extracts data from the RAM 20 and outputs it to the external device. 22 is a bus control unit,
Depending on the address and data output from the access control unit 15, it is stored in the RAM 20 or the RAM
Access control unit 15 by taking out 20 data
Pass the data to.

The operation of such a device will be described below. CP
When the U10 exchanges data in word units with the I / O module 2, the CPU 10 designates the address of the word / long setting register 13 and outputs data "0".
As a result, the word / long setting register 13 is "0".
Hold. Then, since the value held in the word / long setting register 13 is “0”, the address check unit 14
Do nothing In the access control unit 15, since the value held in the word / long setting register 13 is “0”, C
I / O having the RAM 20 corresponding to the address number when receiving the address number and the read / write signal from the PU 10
Exchanges data in word units with the O module 2.

When the CPU 10 exchanges data in units of long words with the I / O module 2, the CPU 1
0 indicates the address of the word / long setting register 13 and outputs data "1". As a result, the word / long setting register 13 holds "1". Then, the address check unit 14 inputs the held value “1” of the word / long setting register 13 so that the CPU 10
It is checked whether the address output from is a multiple of 4. If it is correct, a start signal is output, and if not, a bus error is notified to the CPU 10. Then, it is sequentially checked whether or not the address output from the CPU 10 is the previous address +2. If the address is correct, a start signal is output, and if not, a bus error is detected by the CPU 10.
To notify. In response to the activation signal, the access control unit 15 receives the address number and the read / write signal from the CPU 10 and receives the RA corresponding to the address number.
It exchanges data in units of long words with the I / O module 2 having M20. That is, the access control unit 15 performs the access of the I / O module 2 by the address number from the CPU 10 and the access of the I / O module 2 by the address number + 1 from the CPU 10 to obtain the data in the longword unit.

[0006]

In such a structure, there are the following problems. When the CPU 10 wants to alternately process data in word units and long word units, the CPU 10 must set the word / long setting register 13 and then exchange data with the I / O module 2. Therefore, the CPU module 1 There was a problem that the processing speed of was slow.

An object of the present invention is to realize an arithmetic processing unit capable of exchanging data with a peripheral device at high speed without setting a data unit for exchanging data in advance.

[0008]

SUMMARY OF THE INVENTION The present invention is a CP for exchanging data of different data units with a peripheral device via a bus.
In an arithmetic processing unit having U, the address number output by the CPU is input, and it is checked whether the address number is correct according to the specified address number, and if not, a CPU is notified of a bus error, When correct, an address check unit that outputs a start signal and an access control unit that receives the start signal from the address check unit and accesses the peripheral device corresponding to the address number output by the CPU are provided. It is characterized by that.

[0009]

According to the present invention, the CPU outputs the address number of the peripheral device. Then, the address check unit checks whether or not the address number is correct by the address number output from the CPU, and when it is correct, notifies the access control unit of a start signal, and when not correct, notifies the CPU of a bus error. To do. Upon receiving the activation signal, the access control unit exchanges data with the peripheral device.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The same parts as those in FIG. 3 are designated by the same reference numerals. In the figure, 16 is an address check unit, which inputs an address number output from the CPU 10 and checks whether or not the longword unit address number is correct according to a prescribed longword unit address number. The CPU 10 is notified of the bus error, and when it is correct, a longword unit activation signal is output. When the address number from the CPU 10 is an address number in word units, a start signal in word units is output. The access control unit 15 receives a start signal in word units or long word units from the address check unit 16 and accesses the I / O module 2 corresponding to the address number output by the CPU 10. The specific configuration of the address check unit 16 is shown in FIG. In the figure, 161 is a decoder which inputs an address number and outputs a signal in accordance with the address number. That is, if it is an address in word units, it outputs a word signal for activating access in word units to the access control unit 15, and if it is an address in longword units, it outputs a longword signal notifying that it is in longword units. A check unit 162 receives the longword signal from the decoder 161, checks whether the address number is correct as a longword unit address, and when it is correct, a signal for activating the access in the longword unit to the access control unit 15. Is output, and if not correct, a bus error is notified to the CPU 10.

The operation of such a device is described below.
Here, the I / O module 2 that handles data in word units
The address of RAM20 is "$ 700000",
The address of the RAM 20 of the I / O module 2 that handles longword units of data, that is, the prescribed address of longword units is "$ 740000". CPU1
0 outputs the address number of the RAM 20 of the I / O module 2 desired to access. Then, the decoder 161
The address number output from the CPU 10 is "$ 7000.
The word signal or longword signal is output depending on whether it is "00" or "$ 740000". As a result, "$ 700"
When the number is "000", the access is started in word units to the access control unit 15. When it is "$ 740000", the check unit 162 checks whether the address number from the CPU 10 is a multiple of 4, and if it is correct. Activates the processing of data in units of long words to the access control unit 15, and when it is incorrect, notifies the CPU 10 of a bus error.
It is checked whether or not the address number from the CPU 10 is a multiple of 4 + 2, and if it is correct, the access control unit 15 is activated to start the data processing in longword units.
If not correct, a bus error is notified to the CPU 10.
Then, the access control unit 15 accesses the I / O module 2 in accordance with a start signal in word units or long word units.

As described above, by providing the address check unit 16 for checking whether or not the data in the longword unit is correct according to the address number output from the CPU 10, the setting in the word unit or the longword unit is made in advance. Since there is no need, the processing speed of the CPU module 1 can be increased.

The present invention is not limited to this, and the address check unit 16 is configured to check whether the first address number is a multiple of 4, but whether it is a multiple of 2 from the beginning. It may be configured to check. Further, in the word unit, the address is not checked, but it may be checked. Further, in the embodiment, only the data in word units and long word units are described, but data in other units may be handled.

[0014]

According to the present invention, an address check unit for checking whether or not the address number of a data unit is correct is provided by the address number output by the CPU, so that it is necessary to set the data unit in advance. Since there is no such processing, the processing speed of the arithmetic processing device can be increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of an address check unit 16 of the device shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional programmable controller.

[Explanation of symbols]

 1 CPU module 2 I / O module 3 Bus 10 CPU 15 Access control unit 16 Address check unit

Claims (1)

[Claims] 1. An arithmetic processing device having a CPU for exchanging data of different data units with a peripheral device via a bus, wherein an address number output by the CPU is input, and the address number is changed according to a prescribed address number. If it is not correct, a bus error is notified to the CPU if it is not correct, and if it is correct, an address check unit that outputs a start signal and a start signal from this address check unit
An arithmetic processing unit, comprising: an access control unit for accessing the peripheral device corresponding to an address number output from the PU.