JPH08223479A - Sampling frequency conversion circuit - Google Patents

Abstract

PURPOSE: To reduce a circuit scale by reducing a video signal in the horizontal direction and sampling frequency simultaneously and converting them so as to reduce deterioration in high frequency response in the horizontal direction so as to obtain an excellent image. CONSTITUTION: When magnification obtained by multiplying an inverse frequency conversion ratio with magnification or reduction of an image is less than the unity, the processing is the reduction processing as a whole and changeover switches 3, 9 are thrown to the position of reduction and a reduction interpolation arithmetic circuit 1, a reduction interpolation coefficient calculation circuit 21, a line memory 4, a write control circuit 5 and a read control circuit 60 are used for reduction processing. Conversely when the magnification is the unity or over, the changeover switches 3, 9 are thrown to the position of magnification for magnification processing. That is, the reduction interpolation is conducted and the resulting data are written in a line memory 4 by using a clock signal before frequency conversion and read by using clock signals after frequency conversion while conducting address control corresponding to the synthesis magnification to realize horizontal direction reduction processing and sampling frequency conversion simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting a sampling frequency of a video signal by digital signal processing, and more particularly to a video for performing both horizontal scaling processing for scaling up or down an input video signal and sampling frequency conversion. The present invention relates to a sampling frequency conversion circuit in a signal processing circuit.

[0002]

2. Description of the Related Art In the prior art, when an image is enlarged or reduced in a system that requires sampling frequency conversion in digital video signal processing, the sampling frequency conversion and the image enlargement / reduction processing are performed independently. .

Regarding the image enlargement / reduction processing, for example,
As shown in Japanese Patent Application Laid-Open No. 6-46306, a field memory is used to perform image enlargement in the horizontal and vertical directions. Horizontal scaling processing is extracted from the field memory and input to multiple line memories.
The interpolation processing is performed by linear interpolation in the horizontal direction on the data that has been subjected to the enlargement processing in the vertical direction.

In the case of performing image enlargement or reduction processing only in the horizontal direction, a line memory, a write control circuit, and a read control circuit are provided, and in the case of enlargement processing, the data stored in the line memory is enlarged. This is performed by a method in which reading is performed twice while reading at intervals according to the magnification, and interpolation processing is performed using sequentially read data. On the other hand, the reduction processing is performed by a method in which the input data is first interpolated, then written in the line memory, and read while thinning out at intervals according to the reduction ratio.

On the other hand, there are some methods for converting the sampling frequency, but if the conversion ratio becomes complicated to some extent, there is a method of using a RAM, for example. Although the interpolation depends on the conversion ratio and the like, it is simply performed by linear interpolation calculation. For example, in the case of conversion that raises the frequency, the input data is written in the memory at the clock before conversion, and is read while being read twice at the interval after the conversion clock according to the conversion ratio, and this is interpolated by linear approximation. It is done by the method of doing. On the other hand, in the case of conversion for lowering the frequency, linear interpolation is first performed on the input data, writing is performed in the memory at the clock before conversion, and reading is performed while thinning out at the clock after conversion.

An example of the configuration of the horizontal direction reduction processing and the sampling frequency conversion processing in such a conventional system is shown in FIG. 4 in the case of the clock lowering conversion and in FIG. 5 in the case of the clock increasing conversion.

Regarding the horizontal reduction processing method and the sampling frequency conversion method described above, FIG. 7 shows a horizontal reduction processing at 4/5 times, and FIG. 8 shows a schematic view of the frequency conversion processing with a conversion ratio of 4: 5.

[0008]

[Problems to be Solved by the Invention]

(Problem 1) However, in the conventional configuration as shown in FIG. 4 or FIG. 5, for the image signal whose image quality is once degraded by the linear interpolation calculation due to the horizontal reduction processing, band limitation for frequency conversion and re-interpolation calculation are further performed. Since this is a process, there is a problem that image quality is greatly deteriorated.

This will be described below with reference to FIG. 11 showing the frequency characteristics of the base band. First, horizontal reduction processing as shown in FIG. 7 is performed on the input signal (a).

Here, the interpolation ratio is 1: 0 as shown in FIG.
3/4: 1/4, 1/2: 1/2, 1/4: 3/4,
Although it changes in the order of 1: 0 and 0: 1, the output frequency characteristic is as shown in (b) at the point of the interpolation ratio of, for example, 1/2: 1/2. Further, sampling frequency conversion processing as shown in FIG. 8 is performed on this. The output frequency characteristic by this sampling frequency conversion processing is
It becomes like (c).

It should be noted that the frequency characteristic diagram only for the interpolation calculation is shown in (b), but since the aliasing distortion occurs when the horizontal reduction processing is performed, it is necessary to limit the band of the input signal. is there. Further, FIG. 7C is a simplified view of the state in which only the sampling frequency conversion is performed on FIG.

In practice, if horizontal reduction and frequency conversion are performed with band limitation, a filter like (c) is applied to (b), and as a result, the total frequency characteristic is as shown in (d). Therefore, the effect of double filtering is obtained, and the response of the high frequency component of the signal is double deteriorated.

Incidentally, this is similarly deteriorated even if frequency conversion is performed first and then horizontal reduction processing is performed.

In the conventional circuit configuration, the memory 16 and the write / read control circuit (1
7 and 18), the interpolation calculation circuit 14 and the interpolation coefficient calculation circuit 15 are required separately, and the horizontal enlargement processing circuit needs to have substantially the same circuit configuration, so that the circuit configuration is redundant and has a large scale. It was

Regarding the capacity of the frequency conversion memory 16, the required capacity is determined by the conversion ratio, and a simple conversion ratio may be small, but a complicated conversion ratio requires a large memory capacity.

Further, in an actual circuit, in the case of a signal having a high frequency and a small amplitude, the bit precision of the interpolation operation is deteriorated by repeating the interpolation computation. Therefore, in order to maintain the bit precision, the interpolation computation circuit or line is required. The circuit scale of memory and the like becomes large.

The present invention solves the above-mentioned conventional problems, and the sampling which can perform the horizontal reduction processing and the sampling frequency conversion processing at the same time with a simple structure and while suppressing the deterioration of the image quality to be small. A frequency conversion circuit is provided.

(Problem 2) However, in the conventional configuration, in the frequency conversion, in the conversion for lowering the frequency as shown in FIG. 4, it is necessary to perform the linear interpolation calculation before writing in the frequency conversion memory, and as shown in FIG. In the conversion for increasing the frequency, it is necessary to perform the linear interpolation calculation after writing the frequency conversion memory.

Similarly, with respect to image scaling,
In the reduction processing, the interpolation calculation needs to be performed before writing in the line memory, and in the enlargement processing, the interpolation calculation needs to be performed after writing in the frequency conversion memory.

As described above, in the conventional configuration, it is necessary to adopt the configuration of the image enlargement / reduction processing and the sampling frequency conversion processing according to each video signal processing system.

The present invention solves the above-mentioned conventional problems, and performs horizontal enlargement / reduction processing and sampling frequency conversion processing of an arbitrary ratio at the same time with a simple structure while suppressing deterioration of image quality. The present invention provides a sampling frequency conversion circuit capable of performing the above.

[0022]

[Means for Solving the Problems]

(Means 1 for Solving Problem 1) The sampling frequency conversion circuit of the first invention of the present invention uses a line memory capable of operating write and read with different operation clocks, and the horizontal frequency is directly obtained from an input signal. The reduction processing and the sampling frequency conversion processing are simultaneously performed.

(Means 2 for Solving Problem 2) The sampling frequency conversion apparatus of the second invention of the present invention uses a line memory capable of operating write and read with different operation clocks, and uses a reduction processing circuit. And an enlarging processing circuit are provided, and the enlarging / reducing circuit and the sampling frequency conversion are simultaneously performed directly from the input signal by switching to either one according to the magnification.

(Means 3 for Solving Problem 2) The sampling frequency conversion apparatus of the third invention of the present invention uses a line memory capable of operating write and read with different operation clocks, and performs scaling interpolation. An arithmetic circuit and a scaling interpolation coefficient calculation circuit are provided, and the operation clocks for these circuits are switched according to the magnification to operate, and the scaling processing circuit and the scaling processing circuit are shared and horizontal scaling is performed directly from the input signal. The processing and the sampling frequency conversion are performed at the same time.

[0025]

[Action]

(Operation by Means 1) According to the configuration of the first aspect of the present invention, the reduction interpolation operation is performed with the combined magnification ratio obtained by multiplying the reduction ratio of the horizontal reduction process and the inverse conversion ratio of the frequency conversion, and the data is line-processed. After writing to the memory with the clock before frequency conversion, while performing address control corresponding to the synthesis ratio, while reading with the clock after frequency conversion, horizontal reduction processing and sampling frequency conversion can be performed at the same time. To work.

Here, the sampling frequency conversion is explained on the premise of the conversion for lowering the clock, but it can also correspond to the conversion for increasing the clock in the range in which the composite magnification ratio is 1 or less.

(Operation by Means 2) According to the configuration of the second aspect of the present invention, the composite magnification obtained by multiplying the enlargement / reduction ratio of the horizontal enlargement / reduction processing by the inverse conversion ratio of the frequency conversion is:
If the total is less than 1, the data is written to the line memory after the reduction processing, and is read at the converted clock. On the other hand, if it is 1 or more, by writing to the line memory at the clock before conversion, reading at the clock after conversion, and then performing the enlargement process, the horizontal enlargement or reduction process and the sampling frequency conversion of an arbitrary ratio are performed simultaneously from the input signal. It acts like it does.

(Operation by Means 3) According to the configuration of the third aspect of the present invention, the scale-down interpolation calculation circuit and the scale-down interpolation coefficient calculation circuit are provided with a pre-conversion clock during reduction and a post-conversion clock during expansion. By selectively inputting as the operation clock, the reduction processing and the enlargement processing can be shared by the same circuit, and the input / output and output sections of the line memory can be switched between signals, allowing horizontal expansion directly from the input signal with a simple configuration. Alternatively, the reduction processing and the sampling frequency conversion with an arbitrary ratio are performed at the same time.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. A block diagram of a first embodiment of the present invention is shown in FIG.

First, the interpolation coefficient calculation circuit 20 calculates the composite magnification obtained by multiplying the image reduction magnification set by the system controller or the like by the inverse conversion ratio of the frequency conversion.

The input signal is subjected to linear interpolation calculation by the interpolation calculation circuit 10 according to the synthesis magnification. The input signal subjected to the interpolation calculation is address-controlled by the write control circuit 5 and written in the line memory 4 in an arbitrary range in the horizontal direction at the clock rate before conversion. Then, the read control circuit 6 is read from the line memory 4 at the converted clock rate while performing the read skip address control so that the data corresponding to the interpolation operation is obtained in the corresponding horizontal range, and the read rate is changed. The converted horizontal reduced image signal is output.

The above-mentioned processing will be described below with reference to FIG. 9 which is a schematic flow chart of signal processing. FIG. 9 shows an example in which the sampling frequency is converted at a ratio of 3/5 horizontal reduction ratio and before conversion: after conversion = 3: 4.

First, in the interpolation coefficient calculation circuit 20 of FIG.
If the composite ratio is r and the composite interpolation ratio is k, then r = reduction ratio × 1 / clock conversion ratio = 3/5 × 4/3 = 0.8 k = 1 / composite ratio = 1 / 0.8 = 1. 25 is calculated.

In the interpolation calculation circuit 10, the synthetic interpolation ratio k = 1.
If there are 25, then 0, 0.25, 0.5, 0.75, 0 and interpolation coefficients are sequentially input according to the synthetic interpolation ratio, and interpolated from the data before and after the input signal a to obtain b. This data is written in the line memory within the horizontal writing range frame designated by the pre-conversion clock as shown by c.

On the other hand, the read control circuit 6 skips every fifth data so as to correspond to the composite magnification of 0.8 within the horizontal read frame designated by the converted clock, and reads the data like d.

In this way, the input signal a is reduced and the sampling frequency is converted simultaneously to obtain the output signal d.

Actually, the output signal d is obtained with a delay of 1H with respect to the input signal a. FIG. 6 shows an example of the interpolation calculation circuit.

In FIG. 6, assuming that the input signal at time n is X _n , the output signal is Y _n , and the sequentially input interpolation coefficient is K _n , Y _n = (1−K _n ) X _n−1 + K _n A linear interpolation calculation of X _n is performed.

Next, the effect of suppressing image quality deterioration will be described with reference to FIG. Here, in order to compare with FIG. 11, the case where the reduction ratio is 4/5 times and the frequency conversion ratio is 4: 5 is shown.

Assuming that the band limitation with respect to the aliasing distortion due to the reduction processing is applied to the input signal as in the description of FIG. 11, the composite ratio of the input signal (a) is 1: 4:
Since the sampling frequency conversion of 5 is performed at the same time,
A filter as shown in (b) is passed through, and when the band is limited, the result is as shown in (c). Although the example shown here is a somewhat peculiar example, it can be expressed in the same manner in a normal case where the composite magnification is not 1.

As described above, in this method, since the filtering is effective only once, the deterioration of the response of the high frequency component of the signal can be suppressed lower than that shown in FIG.

In the above embodiments, the case where the frequency conversion is converted into the clock faster than the pre-conversion clock is explained. However, the clock is raised in the range where the synthesis magnification is 1 or less as in these examples. Frequency conversion can also be performed.

For the conversion to lower the clock, any reduction ratio is possible. A second embodiment of the present invention will be described with reference to the drawings. A block diagram of a second embodiment of the present invention is shown in FIG.

First, a case where the composite magnification obtained by multiplying the magnification of image enlargement or reduction and the inverse conversion ratio of frequency conversion is less than 1 will be described. In this case, reduction processing is performed as a whole, and the changeover switches 3 and 9 are operated. Switching to the reduction side, the reduction interpolation calculation circuit 1, the reduction interpolation coefficient calculation circuit 21, the line memory 4, the write control circuit 5, the read control circuit 60.
Is used to perform the reduction processing described in the embodiment of the first invention.

On the contrary, if the composite magnification is 1 or more, the enlargement process is performed as a whole, and the changeover switches 3 and 9 are switched to the enlargement side to perform the enlargement process described below.

In the enlargement processing, the input signal is address-controlled by the write control circuit 5 and an arbitrary range in the horizontal direction of the input signal is written in the line memory 4 at the clock rate before conversion. In addition, the expansion interpolation coefficient is calculated by the expansion interpolation coefficient calculation circuit 8 based on the combination magnification set by the system controller or the like. With this coefficient, the read control circuit 60 performs address control so that the data necessary for performing the expansion interpolation calculation of the composite magnification in the corresponding range can be read,
The data is read from the line memory 4 at the converted clock rate. The data read out in this manner is used for the expanded interpolation calculation circuit 7
Then, linear interpolation calculation is performed by the enlargement interpolation coefficient, and the result is output as a horizontally enlarged image signal with a converted sampling frequency.

The signal processing flow in the case of the above-described enlargement processing will be described below with reference to FIG.

FIG. 10 shows an example in which the sampling frequency is converted at a horizontal expansion ratio of 1.5 times and a ratio of before conversion: after conversion = 6: 5.

The input signal a is directly written in the line memory within the horizontal writing range frame designated by the pre-conversion clock as shown by b.

Further, in the expansion interpolation coefficient calculation circuit 8 of FIG. 2, if the composite magnification is r and the composite interpolation ratio is k, r = enlargement magnification × 1 / frequency conversion ratio = 1.5 × 1 / 1.2 = Calculate 1.25 k = 1 / combining magnification ratio = 1 / 1.25 = 0.8.

On the other hand, in the read control circuit 60, every four data are read twice like c in the horizontal read frame designated by the converted clock so as to correspond to the composite magnification of 1.25.

Then, in the enlarged interpolation calculation circuit 7, if the synthetic interpolation ratio k = 0.8, then 0, 0.8, 0.6, 0.4, in that order.
In accordance with 0.2 and the synthetic interpolation ratio, interpolation coefficients are sequentially input and interpolated from the data before and after, and linear interpolation calculation is performed with the converted clock as shown by d. In this way, the input signal a is enlarged and the sampling frequency is converted at the same time to obtain the output signal d.

As described above, the horizontal enlargement / reduction processing and the sampling frequency conversion processing with an arbitrary ratio can be performed at the same time while suppressing the deterioration of the image quality.

A third embodiment of the present invention will be described with reference to the drawings. A block diagram of a third embodiment of the present invention is shown in FIG.

First, a case where the composite magnification obtained by multiplying the magnification of image enlargement or reduction and the inverse conversion ratio of frequency conversion is less than 1 will be described. In this case, the overall reduction processing is performed and the following operation is performed. The changeover switches 3, 9 and 11 are switched to the reduction side, and the pre-conversion clock (shown as Wclk in FIG. 3) is input to the enlargement / reduction interpolation calculation circuit 12 and the enlargement / reduction interpolation coefficient calculation circuit 13 as an operation clock to synthesize the composite magnification. (Less than 1) is set and the reduction interpolation processing is performed. Then, the reduction processing described in the embodiment of the second invention is performed using the line memory 4, the write control circuit 5, and the read control circuit 61.

On the contrary, if the composite magnification is 1 or more, the enlargement processing is performed as a whole, and the changeover switches 3, 9 and 11 are switched to the enlargement side, and the enlargement / reduction interpolation calculation circuit 12 and the enlargement / reduction interpolation coefficient calculation circuit 13 The converted clock (shown as Rclk in FIG. 3) is input as the operation clock, the composite magnification (1 or more) is set, and the enlargement interpolation processing is performed.

In this way, the enlargement processing described in the embodiment of the second invention is similarly performed.

[0058]

As is apparent from the above description, according to the first aspect of the present invention, it is possible to obtain a good image in which the deterioration of the high frequency response in the horizontal direction is suppressed to a small level, and
Also in terms of the circuit scale, the circuit scale can be significantly reduced as compared with the case where the horizontal reduction processing and the sampling frequency conversion are performed independently.

As is clear from the above description, according to the second aspect of the present invention, any combination of horizontal enlarging or reducing processing and clock raising or lowering conversion can be arbitrarily performed with a simple configuration. You can Also, in terms of the circuit scale, the circuit scale can be significantly reduced as compared with the case where the horizontal enlargement / reduction processing and the sampling frequency conversion are performed independently. Further, it is possible to obtain a good image in which the deterioration of the horizontal high frequency response is suppressed to a small level.

As is clear from the above description, according to the third aspect of the present invention, any combination of horizontal enlargement or reduction processing and simultaneous clock increase or decrease conversion can be performed with a simple configuration. You can Further, in terms of circuit scale, it is possible to further reduce the circuit scale as compared with the case of the embodiment of the second invention. Further, it is possible to obtain a good image in which the deterioration of the horizontal high frequency response is suppressed to a small level.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a horizontal reduction and frequency conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a horizontal reduction / enlargement and frequency conversion circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a horizontal reduction / enlargement and frequency conversion circuit according to a third embodiment of the present invention.

FIG. 4 is a configuration block diagram of a horizontal reduction circuit unit and a frequency conversion circuit unit (lowering a clock) of a conventional example.

FIG. 5 is a configuration block diagram of a horizontal reduction circuit unit and a frequency conversion circuit unit (increasing a clock) in a conventional example.

FIG. 6 is a block diagram showing a configuration of an interpolation operation circuit according to the first to third embodiments of the present invention.

FIG. 7 is an explanatory diagram of a method of only horizontal reduction.

FIG. 8 is an explanatory diagram of a method only for sampling frequency conversion.

FIG. 9 is an explanatory diagram of a signal processing method of reduction interpolation in the first to third embodiments of the present invention.

FIG. 10 is an explanatory diagram of a signal processing method of enlarged interpolation in the second and third embodiments of the present invention.

FIG. 11 is a frequency characteristic diagram in the case of the conventional method of performing frequency conversion after reduction processing.

FIG. 12 is a frequency characteristic diagram in the case of the reduction processing and the frequency conversion method according to the first embodiment of the present invention.

[Explanation of symbols] 1 reduction interpolation calculation circuit 3, 9, 11 changeover switch 4 line memory 5 write control circuit 6, 60, 61 read control circuit 7 enlargement interpolation calculation circuit 8 enlargement interpolation coefficient calculation circuit 10 interpolation calculation circuit 12 enlargement / reduction Interpolation calculation circuit 13 Enlargement / reduction interpolation coefficient calculation circuit 20 Interpolation coefficient calculation circuit 21 Reduction interpolation coefficient calculation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 7/01 H04N 5/93 C

Claims (3)

[Claims] 1. An interpolation calculation circuit for horizontally reducing a digital video signal, a line memory capable of operating writing and reading at different operation clocks, and data calculated by the interpolation calculation circuit for the line memory. A write control circuit for writing to, a read control circuit for controlling the reading of the line memory, an interpolation calculation circuit and an interpolation coefficient calculation circuit for controlling the read control circuit, and a horizontal direction of a video signal. Sampling frequency conversion circuit characterized by simultaneously performing the above-mentioned reduction processing and sampling frequency conversion. 2. A reduction interpolation calculation circuit for reducing a digital video signal in a horizontal direction, a line memory capable of operating write and read with different operation clocks, and write control for performing write control on the line memory. A circuit, a read control circuit for performing read control of the line memory, a reduction interpolation coefficient calculation circuit for controlling the reduction interpolation calculation circuit and the read control circuit, and a digital video signal read from the line memory horizontally. An expansion interpolation calculation circuit that expands in the direction
An enlargement interpolation coefficient calculation circuit that controls the enlargement interpolation calculation circuit and the read control circuit, and a switching circuit that switches between reduction processing and enlargement processing,
A sampling frequency conversion circuit characterized by simultaneously performing horizontal direction reduction processing or enlargement processing of a video signal and sampling frequency conversion. 3. An interpolation calculation circuit for reducing or enlarging a digital video signal in the horizontal direction, a line memory capable of operating writing and reading with different operation clocks, and writing control for the line memory. A write control circuit, a read control circuit that performs read control of the line memory, an interpolation coefficient calculation circuit that controls the interpolation calculation circuit and the read control circuit, and a reduction process or an enlargement process. A switching circuit for switching, and as the operation clock for the interpolation calculation circuit and the interpolation coefficient calculation circuit, a clock before sampling frequency conversion is selected and input during expansion processing, and a clock after sampling frequency conversion is selected and input during expansion processing. Horizontal signal reduction or enlargement processing and support A sampling frequency conversion circuit characterized by simultaneously performing sampling frequency conversion.