CN1319372C - Method and device for sampling digital image - Google Patents

Abstract

The present invention provides a method and a device for sampling digital images in a lowered frequency mode. By processing on a time axis, the complexity of calculation and a device architecture is decreased, and the problems of a blurring effect and loss of information of a part of image caused by sampling in a lowered frequency mode are solved. Thus, the purpose of sampling digital image in a lowered frequency mode is obtained.

Description

A kind of method and apparatus of digital picture sampling

Technical field

The present invention relates to the method and apparatus of a kind of digital picture frequency reducing sampling, refer to especially a kind of by the processing on time shaft, to reach the method and apparatus of frequency reducing sampling.

Background technology

In digital image system, the conversion of picture format must be reached by the corresponding conversion of DID being made sampling frequency.For example, the image frame of 800 * 600 pixels is enlarged into 1024 * 768 pixels, then is equivalent to view data is carried out the raising frequency sampling on level and vertical two dimension.Otherwise,, then be equivalent to the frequency reducing sampling if the image frame of 1024 * 768 pixels will be reduced into 800 * 600 pixels.

On the implementation method that image frame dwindles, common have two kinds of the method for giving up and interpolation methods.The practice of giving up method is directly to be used as the result that frequency reducing is taken a sample near the pixel of frequency reducing sample position in the original image.The interpolation rule is the mode with linear interpolation or other numerical method interpolation, makes to calculate the result who obtains after frequency reducing is taken a sample near the pixel data of frequency reducing sampling point position by picture position in the original image.Fig. 1 is to give up method and interpolation method and tries to achieve the schematic diagram of (5: 4) frequency reducing sampling result.

Generally speaking, the frequency reducing of interpolation method sampling can obtain changing comparatively accurately, but still can make the image information distortion because of frequency reducing.But because this method must be tried to achieve the result after via multiplication and addition with plural pixel data in the original image, and the pixel data of picture width more than one times at least in must the storage original image in device, cost in realization is quite high.Fig. 2 is the circuit diagram of interpolation method, comprises the horizontal interpolative operation circuit 12 of vertical interpolation computing circuit 11 or (reaching), line data buffer 13, frequency reducing sampling calculating control circuit 14 and Data Buffer Register (FIFO) 15.Wherein, the interpolation method computing circuit can need multiplier and adder usually, and only two minutes one accuracy then only needs adder.

Give up method and realize that hardware is very simple, Fig. 3 is the circuit diagram of giving up method, comprises frequency reducing sampling calculating control circuit 21, vertically gives up method and select output circuit 22 or (reach) level to give up method selection output circuit 23 and data buffer 24.Yet since this method directly by the part pixel of taking out the fixed position in the original image as the frequency reducing sampling result, directly give up some image information, so can't possess enough image informations.For example, the T pattern in the raw frames, after through the frequency reducing sampling of giving up method, according to the difference of pattern place picture position, the possibility of result can become-or I, or even can't see pattern fully.Wherein,

Because no matter be any frequency reducing sampling, information is run off, can not keep complete original image information; And make the purpose that frequency reducing is taken a sample, be under this situation, still can obtain the suitable information of image by content displayed; Therefore accurate interpolation method, not necessarily meaningful for the user; And simple interpolation (1/2 accuracy) is just sacrificed image quality to have saved multiplier, and hsrdware requirements are still big; But can't allow the people accept but give up method, because real significant information, may can't interpretation with regard to being rejected.Therefore will utilize and give up method and still can keep the information of image, even the effect of simple interpolation (1/2 accuracy) is arranged, be the target that the present invention will realize.

Summary of the invention

Because the problems referred to above the purpose of this invention is to provide a kind of characteristic of utilizing time shaft, take a sample.

Another object of the present invention is to provide a kind of method and apparatus of digital picture sampling, utilize the mechanism of initial offset, after the frequency reducing sampling, still can keep original graphical information.

Another purpose of the present invention is to provide a kind of realization cost and to give up method identical, but after the frequency reducing sampling, can also provide the enough image informations of user to understand, even than interpolation method more distinct image be beneficial to the user and understand, or near the device and method of the effect of simple interpolation (1/2 accuracy).

Traditional practice is all only considered individual picture, but is not the angle thinking of continuous pictures from output image.The present invention proposes to be handled for the digital picture of continuous pictures, for adjacent A, B two pictures,, can reappear at the B picture, for the user to give up the information that method is given up at the A picture, still keeping complete image information can interpretation, on hardware, only need the mechanism of many initial offsets on frequency reducing sampling calculating control circuit, promptly can reach the effect of frequency reducing sampling.

For the image of literal, keep how original more information clearly, can obtain best deciphering effect.Interpolation method can be made the effect of obfuscation to image, is unfavorable for the interpretation of literal on the contrary, utilizes this method Billy to keep how original information clearly with interpolation method, for the interpretation of user for literal, provides better effect.Except original information clearly, utilize setting in initial offset values, the different information of few more A/B picture are switched, and also the image to literal has better deciphering effect.

On the other hand, for the image of figure, accurate interpolation method can obtain effect preferably.This method can utilize the persistence of vision on time shaft human eye to be caused the average of image information, makes the effect of approximate simple interpolation (1/2 accuracy), also is that the setting that sees through initial offset values reaches.

For reaching above-mentioned purpose, the device of digital picture frequency reducing sampling of the present invention comprises: the Data Buffer Register of a first in first out pattern (FIFO) stores the pixel data after frequency reducing is taken a sample, to overcome the asynchronous read and write problem of data in the real-time system; A frequency reducing sampling calculating control circuit, the pixel data that whether will import at present in order to control reads in the result of Data Buffer Register (FIFO) as the frequency reducing sampling, and the setting of initial offset values.Via the pixel data of in consecutive image, accepting or rejecting the different pictures position, reach the purpose of digital picture frequency reducing sampling with persistence of vision effect.

The present invention is described in detail with instantiation below in conjunction with accompanying drawing.

Description of drawings

Fig. 1 is that tradition is tried to achieve the schematic diagram of (5: 4) frequency reducing sampling result to give up method and interpolation method;

Fig. 2 is the circuit diagram of traditional interpolation method;

Fig. 3 is the circuit diagram that tradition is given up method;

Fig. 4 is the device schematic diagram of digital picture frequency reducing sampling of the present invention;

Fig. 5 is the device signal controlling figure of digital picture frequency reducing sampling of the present invention;

Fig. 6 A and Fig. 6 B are the oscillograms of the various output signals of digital picture;

Fig. 7 is the device architecture figure of digital picture frequency reducing sampling of the present invention;

Fig. 8 A is an embodiment of the odd even picture decision logic of Fig. 7;

Fig. 8 B is the input and output oscillogram of Fig. 8 A;

Fig. 9 is the device architecture figure that the pixel of Fig. 7 is chosen logic;

Figure 10 A to Figure 10 C is the inventive concept figure of digital picture frequency reducing sampling of the present invention;

Figure 11 B is the preferred embodiment that the initial offset of Offset0=0 of the present invention, Offset1=(M/N)-1 is selected accumulation buffer;

Figure 11 A is the oscillogram of Figure 11 B;

Figure 12 is the preferred embodiment that 8 initial offsets of the present invention's numeral Offset0=1/4, Offset1=3/4 are selected accumulation buffer;

Figure 13 utilizes the present invention to carry out the emulation embodiment data list of frequency reducing sampling.

Drawing reference numeral explanation: 40-digital picture frequency reducing sampler; The data of 41-first in first out pattern are towards buffer; 42-frequency reducing sampling calculating control circuit; 71-three ends input AND logic lock; 72-odd even picture decision logic; 73, the 74-pixel is chosen logic; The 91-initial offset is selected accumulation buffer; The 92-adder; 93-D type flip-flop; The 94-multiplexer; 75-two ends input AND logic lock.

Embodiment

Describe the method and apparatus of the continuous digital picture frequency reducing sampling of the present invention in detail below in conjunction with accompanying drawing.

Fig. 4 is the device schematic diagram of digital picture frequency reducing sampling of the present invention.As shown in the drawing, the continuous digital picture frequency reducing sampler 40 of the present invention comprises the Data Buffer Register (FIFO) 41 of a first in first out pattern, with and frequency reducing sampling calculating control circuit 42.The read control logic of the control circuit 42 in the continuous digital picture frequency reducing sampler 40 of the present invention, be to produce required WE (the Write Enable of Data Buffer Register 41 according to the picture position of image zoom ratio, pixel and picture ordinal number, WE) signal writes Data Buffer Register 41 with the Pixel of Digital Image data.The pixel data of being read by Data Buffer Register 41 is the result of the continuous digital picture frequency reducing sampler 40 of the present invention.

Fig. 5 is the device signal controlling figure of digital picture frequency reducing sampling of the present invention.The embodiment of input signal ICLK, IVS, IHS, IDEN, its pattern of IDATA is shown in Fig. 6 A and Fig. 6 B.Input picture is constituted by continuous picture, and the minimum component unit of picture is a pixel, is the each point in the picture.The pixel of set same vertical position promptly constitutes a horizontal pixel line, and the horizontal pixel line of gathering all upright positions again promptly constitutes complete two-dimensional picture.In the signal waveform shown in Fig. 6 A and Fig. 6 B, ICLK is the clock signal of input picture; IVS is the initial signal of input picture, and the cycle of IVS signal is the cycle of single picture in the image; IHS is the initial signal of horizontal pixel line in the input picture; IDEN is the pixel data index signal; The IDATA signal is 1 o'clock at IDEN, is the pixel data that clock is sent picture with ICLK.In the above-mentioned signal, the variation of IDATA, IHS and IDEN is synchronized with ICLK, and the variation of IVS is synchronized with IHS, and ICLK, IVS, IHS, the IDEN of all pictures all keeps fixed relationship in the image.Signal as shown in Figure 6A is the horizontal viewdata signal schematic diagram in an image frame, when IDEN is 1 (high), the IDATA signal is the single horizontal pixel data signal that clock is sent this image frame with ICLK, then being the horizontal pixel data signal of next bar when next IDEN is 1 again, is the interval of each horizontal line pixel data signal of 0 (low) Shi Zewei and work as IDEN.Signal shown in Fig. 6 B then is to comprise plural horizontal viewdata signal schematic diagram in the entire image picture, wherein, the plural horizontal line pixel data that each IDATA signal is transmitted when IVS is 0 (low) can demonstrate the entire image picture, and when IVS be each image frame of 1 (high) Shi Zewei between the interval.

Input signal OCLK and RE among the figure five, for downstream component (not being presented on the figure) read the clock signal (OCLK) of frequency reducing sampling result by Data Buffer Register 41 and read enable signal (Read Enable, RE); Output signal ODATA is the frequency reducing sampling result of reading.

Input signal HR among Fig. 5 and VR level and the vertical frequency reducing sampling ratio in order to set this device, each is with N bit representation.For instance, if N is 4, and desire is sampled as 16 * 8 picture with 20 * 9 picture frequency reducing, and then the ratio of level and vertical frequency reducing sampling respectively is 5/4 and 9/8; Represent the decimal part of frequency reducing sampling ratio to obtain HR=1/4*2 with bit ⁴=[0100], VR=1/8*2 ⁴=[0010].

Fig. 7 is the device architecture figure of digital picture frequency reducing sampling of the present invention.As shown in the figure, the read control logic of frequency reducing sampling calculating control circuit 42 comprises: three ends input AND logic lock 71, odd even picture decision logic 72, pixel are chosen logic 73, horizontal pixel line selection fetch logic 74, two ends input AND logic lock 75.

The function of three ends inputs AND logic lock 71 be with pixel choose that logic 73 and horizontal pixel line selection fetch logic 74 produce choose signal NCR and external input signal IDEN does the logic AND computing, as view data IDATA being deposited in Data Buffer Register 41 required WE (Write Enable, WE) signal.If it is 0 (Low) that pixel is chosen the NCR of logic 73 outputs, represent that this pixel data need not write Data Buffer Register 41, promptly this pixel is rejected.If the NCR of horizontal pixel line selection fetch logic 74 outputs is 0 (Low), represent that these whole piece horizontal pixel data need not write Data Buffer Register 41, promptly this whole piece horizontal pixel is rejected.One embodiment of odd even picture decision logic 72 is a D type flip-flop shown in Fig. 8 A.This D type flip-flop is the triggering source with input picture initial signal IVS, produces the SEL signal that anti-phase period of change equals picture cycle, as Fig. 8 B.Continuous pictures in the image can be divided into interlaced odd number picture and even number picture according to the SEL signal.

It is identical with the framework of horizontal pixel line selection fetch logic 74 that pixel is chosen logic 73, as shown in Figure 9.TRI is a triggering signal, and when TRI took place by 0 to 1 variation, the initial offset that the Sum output of adder 92 can be pushed the N bit length was selected accumulation buffer 91, and the overflow indicating bit of the adder 92 of N bit length is pushed D type flip-flop 93.The value that outputs to adder in order to control multiplexer 94 on the occasion of output Q of D type flip-flop 93 is 0 or INC; Negative value output QB chooses signal NCR, and when NCR is output as 0, input image data IDATA will not be written into Data Buffer Register 41 this moment.When reset signal RST is 1, remove the output (NCR=1) of flip-flop 93; When SEL=0, initial offset selects accumulation buffer 91 to be reset to Offset0, and when SEL=1, initial offset selects accumulation buffer 91 to be reset to Offset1.

The notion of digital picture frequency reducing sampler 40 of the present invention is shown in Figure 10 A, Figure 10 B1, Figure 10 B2 and Figure 10 C.Figure 10 A is one 6 * 6 single picture, the single for this reason picture of being seen image play continuously form.If this picture is sampled as 4 * 4 with frequency reducing, then the frequency reducing ratio is 3: 2, so desirable picture frequency reducing sample position is 0,1.5,3,4.5 of level and upright position.Realize that to give up method the frequency reducing sampling can be a sampling result with the pixel data of picture position 0,1,3,4 then, as Figure 10 B1.Can't present original graphical information on the picture already with the frequency reducing result who gives up the method realization as seen from the figure.If desirable picture frequency reducing sample position 0,1.5,3,4.5 is added side-play amount 0.5, become 0.5,2,3.5,5, then giving up the pixel data that the frequency reducing sampling of method can change with picture position 0,2,3,5 this moment is sampling result, as Figure 10 B2.Similar to Figure 10 B1, add that the frequency reducing result after the side-play amount still can't present original graphical information on the picture.Yet, examine will find original graphical information dispersed and distributed on the picture in Figure 10 B1 and Figure 10 B2 in.Anticipate promptly, the totalling of Figure 10 B1 and Figure 10 B2 has comprised all former graphical informations.If Figure 10 B1 and Figure 10 B2 are constantly replaced the result who takes a sample as frequency reducing, then because of the visual persistence effect of human eye, being seen image will be for the totalling of Figure 10 B1 and Figure 10 B2, as Figure 10 C.The graphical information of original picture just not reason give up method and can't completely present.

By last routine result as can be known, image is made of continuous pictures, image can be considered as interlaced even number picture and odd number picture.According to the notion of digital picture frequency reducing sampler 40 of the present invention, if desire with the frequency reducing of the point of the M on level in the digital picture or vertical line pixel data be sampled as the N point (wherein M, N are positive integer, and N＜M＜2N), then the practice is as follows:

For the even number picture, M/N*X is added that side-play amount Offset0 is as desirable frequency reducing sample position (X is 0 to N-1 integer ascending series), equal the integer-valued N of a M/N*X+Offset0 pixel by extracting position in the former M point pixel data, to constitute the frequency reducing sampling result of even number picture;

For the odd number picture, M/N*X is added side-play amount Offset1 as desirable frequency reducing sample position, equal the integer-valued N of (M/N*X)+Offset1 pixel by extracting position in the former M point pixel data, to constitute the frequency reducing sampling result of odd number picture.

By the consecutive image that the frequency reducing sampling result of even number picture and odd number picture is constituted, because of comprising all Pixel Information in the original image, the graphical information of original picture is able to complete presenting because of the visual persistence effect of human eye.

It is the mechanism of number Offset0 and Offset1 that initial offset is selected accumulation buffer 91, can make different designs because of different purposes, the present invention proposes the design of two notions, the one, minimum picture changes, and another is to level off to the effect of simple interpolation (1/2 accuracy).

Be changed to target with minimum picture, just make consecutive image that identical output point is at most arranged, so image has more stable effect, also has effect more clearly, and the image that makes literal can easier interpretation for the user.The design of its side-play amount is the difference of Offset0 and Offset1, equals the remainder of M/N frequency reducing multiple, just | and Offset1-Offset0|=(M/N)-1.Make Offset=0, Offset1=(M/N)-1 then can be as the example that is designed to of Figure 11 A and Figure 11 B, be the embodiment of initial offset selection accumulation buffer 91a, after the RST end, produce a RST_Pulse such as Figure 11 A, when RST=1, it is 0 that Offset removes; If during SEL=1, RST-Pulse is used as the sum loading of adder as Offset1, as Figure 11 B.Figure 11 B is the embodiment that the initial offset of Offset0=0, Offset1=(M/N)-1 is selected accumulation buffer 91a.

Another is a target to level off to the effect of simple interpolation (1/2 accuracy), according to the persistence of vision that continuous pictures changes, can be considered as average on the time shaft, therefore can accomplish the interpolation method effect of 1/2 accuracy, for the image of figure, have ratio effect preferably.Frequency reducing sampling by the calculating 1024 → 800 of the example of Figure 13 can obtain with Offset0=1/4, and the setting of Offset1=3/4 has the interpolation method effect that is same as 1/2 accuracy.

Suppose K= M/N*X) , promptly be the integer part of (M/N*X), P is the fractional part of (M/N*X),

If 0≤P＜1/4, $\mathrm{Effect}\_\mathrm{pixel}=\frac{K+\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="C0213052300111.png"\; state="\{\{state\}\}">K</figure-callout>}}{2}=K;$

If 1/4≤P＜3/4, $\mathrm{Effect}\_\mathrm{pixel}=\frac{K+(K+1)}{2}=K+0.5;$

If 3/4≤P＜1, $\mathrm{Effect}\_\mathrm{pixel}=\frac{(K+1)+(K+1)}{2}=K+1;$

Figure 12 is another embodiment that 8 initial offsets of Offset0=1/4, Offset1=3/4 are selected accumulation buffer 91b, and it is to be reset at 01000000b (Offset0=1/4) or 11000000b (Offsetl=3/4) that this accumulation buffer 91b is selected by SEL.

Change slightly and adjustment that the present invention did are used, will do not lost main idea of the present invention place, also do not break away from the spirit and scope of the present invention.

Claims (14)

1. digital picture sampler receives at least one input picture and takes a sample, and comprising:

One picture decision logic circuit according to the variation of time shaft, should be imported image area and be divided at least two groups sampling image; And,

One chooses logical circuit, the sampled picture of reception after by the differentiation of this picture decision logic circuit output, and organize sampled picture each carries out the sampling of pixel with a corresponding sampling point at each, and, according to this not on the same group the selected corresponding sampling point of sampling image to have part at least be complementary.

2. digital picture sampler as claimed in claim 1 also comprises:

One Data Buffer Register is accepted and is temporaryly become a output image data after taking a sample by choosing export after the pixel that logic takes a sample again, and the pixel that is not selected then is rejected.

3. digital picture sampler as claimed in claim 2, wherein, at least can be divided into one first group of pictures and one second group of pictures by choosing the output image data that logical circuit carries out after the pixel sampling, wherein the data of giving up in this first group of pictures are retained in second group of pictures that continues with this first group of pictures.

4. digital picture sampler as claimed in claim 1, wherein, this picture decision logic circuit is that input picture is divided into two groups of continuous on clock sampled picture, and this is chosen logical circuit and is respectively 1/4 and 3/4 at the side-play amount of these two groups of selected described corresponding sampling points of sampled picture.

5. digital picture sampler as claimed in claim 2, wherein, this picture decision logic circuit is divided into two groups of continuous on clock sampled picture with input picture, and this is chosen logic and is respectively 0 and (M/N)-1 at the side-play amount of these two groups of selected corresponding sampling points of sampled picture, wherein M is the vertical/horizontal pixel of above-mentioned input picture, and N is the vertical/horizontal pixel of above-mentioned output image.

6. digital picture sampler as claimed in claim 1, wherein, this is chosen logical circuit and also comprises:

One horizontal pixel line selection fetch logic circuit carries out the pixel sampling of each horizontal pixel line according to the sampled picture of being imported, and exports a horizontal sampled signal; And

One vertical pixel is chosen logical circuit, carries out the vertical pixel sampling according to the sampled picture of being imported, and exports a vertical sampling signal;

Output image data after wherein this horizontal sampled signal and this vertical sampling signal formation one is taken a sample.

7. digital picture sampler as claimed in claim 1, wherein above-mentioned picture decision logic circuit is a flip-flop.

8. digital picture sampling method is to be applied to receive a continuous input picture and to take a sample, and this sampling method comprises:

Produce sampled signal, this sampled signal comprises at least two group sampling patterns, and this continuous input picture is to be divided at least two group sampled picture of taking over continuously according to the variation of clock;

Sampling, respectively organize sampling pattern according to aforementioned sampled signal, respectively organize sampled picture each carry out the sampling of pixel respectively with a corresponding sampling point aforementioned respectively, and, according to this not on the same group the selected corresponding sampling point of sampling image to have part at least be complementary;

Output image will be taken over output image after image is output as a sampling continuously after will organizing sampling pattern and take a sample according to each.

9. digital picture sampling method as claimed in claim 8, the pixel that wherein is not selected then is rejected.

10. digital picture sampling method as claimed in claim 8, wherein, the output image that carries out after pixel is taken a sample can be distinguished into one first group of pictures and one second group of pictures alternately according to the time variation at least, wherein the data of giving up in this first group of pictures are retained in second group of pictures that continues with this first group of pictures.

11. digital picture sampling method as claimed in claim 8, wherein, this input picture is to be divided into two groups of continuous on clock sampled picture, and is to be respectively 1/4 and 3/4 with its these corresponding two groups of sampling patterns at the side-play amount of these two groups of selected described corresponding sampling points of sampled picture.

12. digital picture sampling method as claimed in claim 8, wherein, this input picture is to be divided into two groups of continuous on clock sampled picture, and be respectively 0 and (M/N)-1 with the side-play amount of its these corresponding two groups of selected corresponding sampling points of sampling pattern, wherein M is the vertical/horizontal pixel of above-mentioned input picture, and N is the vertical/horizontal pixel of above-mentioned output image.

13. digital picture sampling method as claimed in claim 8 wherein, also comprises in the step of this sampling:

Step is got in one horizontal pixel line selection, carries out the pixel sampling of each horizontal pixel line according to the sampled picture of being imported, and exports a horizontal sampled signal; And

One vertical pixel is chosen step, carries out the vertical pixel sampling according to the sampled picture of being imported, and exports a vertical sampling signal;

Wherein this horizontal sampled signal and this vertical sampling signal form the output image after this sampling.

14. digital picture sampling method as claimed in claim 8, each wherein above-mentioned sampling pattern part each other are complementary.

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