JP2000209480A - Electronic zoom circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a reduction zoom processing by an interpolation processing. SOLUTION: Image signals for one frame outputted from a signal processing part 31 are divided by line, the image signals of even-numbered lines are written in a 1/2 frame memory 1a and the image signals of odd-numbered lines are written in a 1/2 frame memory 1b. A signal selector 2 rearranges the image signals for two lines adjacent in the vertical direction outputted from the 1/2 frame memories 1a and 1b as needed and outputs them to a vertical interpolation circuit 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic zoom circuit suitable for use in a camera-integrated video tape recorder or the like.

[0002]

2. Description of the Related Art FIG. 6 is a diagram for explaining a conventional electronic zoom circuit. An image signal subjected to predetermined signal processing by a signal processing circuit 31 is written in a frame memory 32. Then, a read address corresponding to the magnification of the electronic zoom is determined by a CPU (not shown) or the like, and an image signal is read for each line based on the read address.

[0003] Image signals read from the frame memory 32 are input to the vertical interpolation circuit 34 via the first line memory 33 one line at a time.
Are also directly input to the vertical interpolation circuit 34. here,
Since the first line memory 33 outputs the input image signal for one line with a delay of a predetermined time, the image signal for two lines adjacent in the vertical direction is simultaneously input to the vertical interpolation circuit 34. Is done. Then, the vertical interpolation circuit 34
Then, pixel interpolation is performed in the vertical direction according to the magnification of the electronic zoom, and an image signal of a line that interpolates between the two adjacent lines is output. Note that the vertical interpolation circuit 34 does not perform vertical pixel interpolation when image signals for two lines adjacent in the vertical direction, such as the upper end and the lower end of the screen, are not input simultaneously.

[0004] FIG. 7 is a diagram showing how an image at the center of the screen is enlarged when a double zoom process is performed in the horizontal and vertical directions of the screen. As shown in FIG. An image signal for a line in the vertical direction a is interpolated from an image signal for line a / 2 in the direction. That is, a CPU (not shown) that repeatedly reads an image signal of a line necessary for vertical zoom processing from the frame memory 32 and performs vertical interpolation processing on the read image signal.
And the like, an image signal for a vertical line a is interpolated from an image signal for a / 2 lines in the vertical direction.

[0005] The image signal that has been subjected to such vertical zoom processing is then supplied to the second line memory 35 one line at a time.
The second line memory 35 outputs this image signal to the horizontal interpolation circuit 37 via the flip-flop 36 (FF) one pixel at a time, and also directly to the horizontal interpolation circuit 37.

Since the flip-flop 36 outputs the input image signal for one pixel with a delay of a predetermined time, the flip-flop 36 is adjacent to the horizontal interpolation circuit 37 in the horizontal direction.
Image signals for pixels are input simultaneously. Then, the horizontal interpolation circuit 37 performs horizontal pixel interpolation according to the magnification of the electronic zoom, and outputs image signals for the number of pixels constituting one line. Note that the horizontal interpolation circuit 37 does not perform horizontal pixel interpolation when image signals for two pixels adjacent in the horizontal direction, such as the left end and the right end of the screen, are not input simultaneously. Then, the horizontal pixel interpolation is performed for the number of lines constituting one frame.

[0007] In the horizontal interpolation process, an image signal for b pixels in the vertical direction is generated by interpolation from an image signal for b / 2 pixels in the horizontal direction, as shown in FIGS. That is, image signals of pixels required for horizontal zoom processing are repeatedly read from the second line memory 35, and a CPU or the like (not shown) controls the read image signals to perform horizontal interpolation processing. b
An image signal for b pixels in the vertical direction is interpolated from an image signal for / 2 pixels.

[0008]

However, in the above-described conventional electronic zoom circuit, a continuously variable magnification which is not an integer unit such as 1.5 times, 3 times, or 4.5 times for image enlargement. The zoom processing can be performed by using the following method, but with respect to the reduction of the image, the zoom processing can be performed only by an integral multiple such as 1/2 or 1/3.

Here, image signals of two lines adjacent in the vertical direction which are simultaneously input to the vertical interpolation circuit 34 will be described in detail. First, the image enlargement processing will be described. When the image signal of the m-th line and the image signal of the (m + 1) -th line are input to the vertical interpolation circuit 34, and the image signal of the first line after interpolation is obtained, In order to obtain an image signal on the second line following the image signal on the first line after the interpolation, the image signal on the m-th line and the image signal on the (m + 1) -th line are input to the vertical interpolation circuit 34 (for both lines). The same image signal) or the image signal of the (m + 1) th line and the (m +
An image signal of a second line (an image signal of a new line in which one line is the same and the other line is adjacent thereto) may be input.

[0010] That is, by controlling the read address from the frame memory 32 and controlling the write inhibition of the first line memory 33 shown in FIG. Image signals for two lines can be obtained.

However, when the image is reduced, for example, the image signal of the m-th line and the m-th
When the image signal of the + 1st line is input and the image signal of the first line after the interpolation is obtained, in order to obtain the image signal of the second line following the image signal of the first line after the interpolation,
The vertical interpolation circuit 34 supplies the image signal of the (m + 4) th line with the mth
In some cases, an image signal for two new lines, such as an image signal on the + 5th line, which is completely different from the line used to obtain the first line after interpolation may be required.

That is, in the conventional electronic zoom circuit as shown in FIG. 6, since only one image signal for each line is output from the frame memory 32, an image for such a new two lines vertically adjacent to each other is output. A signal cannot be input to the vertical interpolation circuit 34, and cannot be handled except for a 1-to-integer reduction process in which unnecessary line information is thinned out and output.

[0013] Further, the reduction process in the horizontal direction is exactly the same, and an image signal for two new pixels adjacent in the horizontal direction cannot be input to the horizontal interpolation circuit 37, and unnecessary line information is not transmitted. It is not possible to cope with it except for a reduction process of 1 / integer which is output by thinning out.

[0014]

In order to solve the above-mentioned problems, an electronic zoom circuit according to the present invention provides an image signal of M lines (M is an integer of 2 or more) vertically adjacent to each other. A line rearranging means for rearranging and outputting M memory areas which are distributed and written, and image signals of respective lines simultaneously read out from the M memory areas in the order of line numbers; Vertical interpolation means for performing line interpolation in the vertical direction based on the image signals for the M lines simultaneously output from the means, and image signals for N pixels (N is an integer of 2 or more) adjacent in the horizontal direction for each pixel. A pixel rearrangement unit that rearranges and outputs N memory areas that are allocated and written and image signals of pixels that are simultaneously read from the N memory areas in the order of pixel numbers. And horizontal interpolation means for performing line interpolation in the horizontal direction based on the image signals of the N pixels simultaneously output from the pixel rearrangement means. The value is set to 2 in each case.
Are both set to 4.

[0015]

FIG. 1 is a diagram for explaining an electronic zoom circuit according to the present invention. The same components as those of the conventional electronic zoom circuit shown in FIG. 6 are denoted by the same reference numerals. . That is, the electronic zoom circuit according to the present invention shown in FIG.
And the configuration of the first line memory 33 is replaced with 1/2 frame memories 1a and 1b and the first signal selector 2, and the configuration of the second line memory 35 and the flip-flop 36 is replaced with the 1/2 line memory 3a. And 3b, and the second signal selector 4.

An image signal output from a CCD or a signal reproduced from a magnetic tape and subjected to predetermined signal processing by a signal processing circuit 31 is output as an image signal for each line, and Are written in a 1/2 frame memory 1a having a memory capacity of 1/2 frame, while the image signals of odd-numbered lines are written in a 1/2 frame memory 1 having a memory capacity of 1/2 frame.
b.

A read address corresponding to the electronic zoom magnification is determined by a CPU (not shown) or the like, and based on the read address, the 1/2 frame memories 1a and 1
The image signals for one line are simultaneously read from b.

FIG. 2 is a diagram showing the relationship between the image signals read from the 1/2 frame memories 1a and 1b and the line switching by the first signal selector 2. here,
If the image signal of the line to be output to the vertical interpolation circuit 34 has a small line number for the even-numbered line, for example, the image signal of the 0th line and the image signal of the 1st line, 1 / The same read address such as 0 is given to the two frame memories 1a and 1b, and at this time, the first and second switches (SW1 and SW2) in the first signal selector 2 are switched to the terminal A.

In the case where the image signal of the line to be output to the vertical interpolation circuit 34 has a small odd-numbered line number, for example, the image signal of the first line and the image signal of the second line , The half-frame memory 1a is given a read address shifted by one, such as 1 and the half-frame memory 1b is given a read address such as 0. At this time, the first and second addresses in the first signal selector 2 are given. Switches (SW1 and SW
2) is switched to the terminal B side.

In this manner, the image signals for two vertically adjacent lines on which the control of the read address and the rearrangement of the lines have been performed are simultaneously input to the vertical interpolation circuit 34, and are adjusted according to the magnification of the electronic zoom. The vertical pixel interpolation is performed, and an image signal of a line that interpolates between the two vertically adjacent lines is output.

The image signals for one line for which vertical interpolation has been completed in the vertical interpolation circuit 34 are output in order from the first pixel, and the image signals for even-numbered pixels have a memory capacity for 1/2 line. While the image signal which is an odd-numbered pixel is 1
The data is written to the ラ イ ン line memory 3b having a memory capacity of ラ イ ン line.

A read address corresponding to the magnification of the electronic zoom is determined by a CPU (not shown) or the like, and based on the read address, the 1/2 line memories 3a and 3b
, Image signals for one pixel are simultaneously read.

Here, the configuration of the second signal selector 4 is shown in FIG.
Is the same as the configuration of the first signal selector 2 shown in FIG. 2, and the image signal to be output to the horizontal interpolation circuit 37 is, for example, an image signal of the 0th pixel and an image signal of the first pixel, If the even-numbered pixel has a small pixel number, the same read address is given to the 1/2 line memories 3a and 3b as described with reference to FIG. The first and second switches (SW1 and SW2) are switched to the terminal A side.

The image signal to be output to the horizontal interpolation circuit 34 is such that the odd-numbered pixel has a small pixel number, for example, the image signal of the first pixel and the image signal of the second pixel. If there is, the 1/2 line memories 3a and 3a
As for b, a read address shifted by one as described with reference to FIG. 2 is given, and at this time, the first and second switches (SW1 and SW2) in the second signal selector 4 are switched to the terminal B side. .

As described above, the image signals of two pixels adjacent in the horizontal direction, in which the read address is controlled and the pixels are rearranged, are simultaneously input to the horizontal interpolation circuit 37,
Pixel interpolation in the horizontal direction according to the magnification of the electronic zoom is performed, and an image signal of a pixel for interpolating between two pixels adjacent in the vertical direction is output.

The above embodiment shows an example in which the vertical interpolation circuit 34 performs vertical interpolation based on image signals for two lines, and the horizontal interpolation circuit 37 performs horizontal interpolation based on image signals for two pixels. However, the vertical interpolation circuit and the horizontal interpolation circuit may be configured to perform the vertical interpolation and the horizontal interpolation based on the image signals of more lines and pixels.

That is, the electronic zoom circuit according to the present invention has a 1 / M
Using M memories having a memory capacity for a frame, M
Vertical interpolation is performed based on image signals for lines, and horizontal interpolation based on image signals for N pixels is performed using N memories having a memory capacity of 1 / N lines (where M and N are An integer of 2 or more).

FIG. 3 shows a configuration in which a vertical interpolation circuit 38 for performing vertical interpolation based on image signals for four lines and a horizontal interpolation circuit 39 for performing horizontal interpolation based on image signals for four pixels are used. is there. Thus, the vertically adjacent 4
When it is necessary to simultaneously input the image signals for the lines to the vertical interpolation circuit 38, the １ ／ frame memories 5a to 5d having the memory capacity for １ ／ frame are used.
When it is necessary to simultaneously input image signals for four pixels adjacent in the horizontal direction to the horizontal interpolation circuit 39, 1 /
1/4 line memory 7 having a memory capacity for 4 lines
a to 7d are used.

The control of the read addresses in the 1/4 frame memories 5a to 5d and the rearrangement of the lines in the third signal selector 6 are as shown in FIGS.

That is, the image signal of the line to be output to the vertical interpolation circuit 38 is a line having the smallest 4k lines (where k is an integer of 0 or more), such as the image signals of the 0th to 3rd lines. If the number is the same, the same read address such as 0, 0, 0, 0 is given to the ４ frame memories 5 a to 5 d, and the first to third memories in the third signal selector 5 are provided. Switches (SW1 to SW4) are switched to the terminal A side.

When the 4k + 1 line has the smallest line number, for example, as in the image signals of the first to fourth lines, the 1/4 frame memories 5a to 5
A different read address such as 1, 0, 0, 0 is given to d, and the first to fourth switches (SW1 to SW4) in the third signal selector 5 are switched to the terminal B side.

When the 4k + 2 line has the smallest line number, for example, as in the image signals of the second to fifth lines, the 1/4 frame memories 5a to 5d
Are given different read addresses such as 1, 1, 0, 0, for example.
Switches (SW1 to SW4) are switched to the terminal C side. For example, like the image signals on the third to sixth lines,
When the 4k + 3 line has the smallest line number, different read addresses such as 1, 1, 1, 0 are given to the １ ／ frame memories 5a to 5d. The first to fourth switches (SW1 to SW4) are switched to the terminal D side.

As described above, the image signals for the four lines adjacent in the vertical direction in which the control of the read address and the rearrangement of the lines have been performed are simultaneously input to the vertical interpolation circuit 37, and are adjusted according to the magnification of the electronic zoom. The vertical pixel interpolation is performed, and a vertical interpolated line image signal is output based on the four vertically adjacent image signals.

The configuration of the fourth signal selector 8 is also the same as the configuration of the third signal selector 5 shown in FIG. It is possible to simultaneously output image signals for four pixels to the horizontal interpolation circuit 37.

In the embodiment described above, the frame memory 32 and the first line memory 3 in the conventional electronic zoom circuit are used.
3, two 1/2 frame memories 1a and 1
b or four 1/4 frame memories 5a to 5d
And instead of the second line memory 35 and the flip-flop 36, two 1/2 line memories 3a
And 3b, or four 1/4 line memories 7a to 7d, eliminating the need to mount a line memory for vertical interpolation such as the line memory 33.

The electronic zoom circuit according to the present invention is not limited to the configuration described above, but divides one frame memory bank into four, and divides each of the four banks by １ ／. The line memories may be used as the frame memories 5a to 5d. Similarly, one line memory bank is divided into four, and the four banks obtained by the division are used as the quarter line memories 7a to 7d, respectively. No problem.

[0037]

In the electronic zoom circuit according to the present invention, image signals for M lines which are vertically adjacent to each other can be simultaneously obtained from the M memory regions, and the image signals which are horizontally adjacent to the N memory regions can be obtained. Image signals for N pixels can be obtained at the same time.
Instead of the reduction processing by thinning out the line information of 2 times, 1/3 times, etc., the reduction processing by the line interpolation and the pixel interpolation becomes possible, so that a high-quality reduced image can be obtained.

[0038]

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of an electronic zoom circuit according to the present invention.

FIG. 2 is a diagram for describing reading of an image signal from a 1/2 line memory.

FIG. 3 is a diagram for explaining another configuration of the electronic zoom circuit according to the present invention.

FIG. 4 is a diagram for explaining reading of an image signal from a ラ イ ン line memory;

FIG. 5 is a diagram showing a relationship between a read address of a ラ イ ン line memory and line switching in a signal selector.

FIG. 6 is a diagram illustrating a configuration of a conventional electronic zoom circuit.

FIG. 7 is a diagram showing how an image is enlarged when a double zoom process is performed horizontally and vertically.

[Explanation of symbols]

 1a, 1b: 1/2 frame memory 2, 4, 6, 8 ... signal selector 3a, 3b: 1/2 line memory 5a, 5b, 5c, 5d: 1/4 frame memory 7a, 7b, 7c, 7d ... 1 / 4 line memory 31 signal processing circuit 32 frame memory 33, 35 line memory 34, 38 vertical interpolation circuit 36 flip-flop 37, 39 horizontal interpolation circuit

Claims (3)

[Claims] An image signal for M lines (M is an integer of 2 or more) adjacent to each other in the vertical direction is allocated to each line and written therein. A line rearranging unit that rearranges and outputs the image signals of each line to be read in the order of line numbers, and performs vertical line interpolation based on the image signals of the M lines that are simultaneously output from the line rearranging unit. Vertical interpolation means; N memory areas in which image signals of N pixels (N is an integer of 2 or more) adjacent in the horizontal direction are distributed and written for each pixel; A pixel rearranging unit that rearranges and outputs an image signal of each pixel to be read out in the order of pixel numbers; and a pixel rearranging unit that outputs the image signals of the N pixels simultaneously output from the pixel rearranging unit. Electronic zoom circuit, characterized in that it comprises a horizontal interpolation means for performing a horizontal line interpolation can. 2. The electronic zoom circuit according to claim 1, wherein both the values of M and N are set to 2. 3. The electronic zoom circuit according to claim 1, wherein the values of M and N are both set to 4.