JPH08223407A - Image processing unit - Google Patents

Abstract

PURPOSE: To attain interpolation processing of all of four picture elements to be obtained without changing a multiplication coefficient by using an interpolation filter equivalent to one picture element to replace a received original picture element. CONSTITUTION: Original picture elements including a noted picture element E are inputted from an input terminal 101. A switch circuit 102 selects an original image required for arithmetic operation of an interpolation picture element and provides an output to each of multipliers 103-106. Data of an original picture element A are given to the multiplier 103, data of an original picture element B are given to the multiplier 104, data of an original picture element D are given to the multiplier 105, data of an original picture element E are given to the multiplier 106 and the results of products are added by an adder 107 to obtain an interpolation result E1. Similarly data of an original picture element C are given to the multiplier 103, data of an original picture element F are given to the multiplier 104, data of an original picture element B are given to the multiplier 105, data of an original picture element E are given to the multiplier 106 to obtain the interpolation result E2. Similarly results E3, E4 are obtained. Thus, interpolation picture elements E1-E4 with respect to the noted picture element E are obtained by a series of four operations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus,
In particular, the present invention relates to an image processing device that performs pixel density or enlargement processing based on an input multi-valued image signal.

[0002]

2. Description of the Related Art Conventionally, enlargement / magnification processing or pixel density conversion processing has been performed in a device such as a copying machine for processing image information.

As one method for enlarging or converting the pixel density, there is a simple so-called pre-value interpolation method in which an input original image is repeated a plurality of times, but this method causes jaggies in the contour portion and increases the magnification. As a result, block-shaped distortion occurs, which causes a large deterioration in image quality.

As a method of solving this, there is a linear interpolation method which causes little deterioration in image quality. A general conversion example using this interpolation method will be described with reference to FIG. FIG. 11 shows 2 of the original pixels.
The center of gravity points A to I on the dimensional plane and the pixel E1 after conversion are mapped onto the original image. E1 at this time
When the pixel position of x is set to x and y as shown in the figure, the pixel E1 to be obtained can be obtained by linearly interpolating from four surrounding original pixels A, B, D and E. That is, the conversion pixel E1
The pixel value (density) of is as follows.

E1 = xyA + (1-x) yB + x (1+
y) D + (1-x) (1-y) E By performing this calculation, a new pixel can be linearly interpolated.

[0006]

However, in the prior art, since eight multipliers and five subtraction adders are required to calculate one interpolation pixel, there is a problem that the amount of hardware increases. It was. Further, the position (x, y) on the original image must be obtained for each interpolation pixel, and this arithmetic circuit also requires a large amount of hardware. Original image position (x, y)
It is also possible to calculate in advance and retain the result in a memory or the like and use the result for calculation, but in this case as well, the memory and its peripheral circuits are required, and an increase in the amount of hardware is unavoidable.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to provide an image for which pixel density or enlargement processing can be realized by simple hardware without degrading image quality. It is to provide a processing device.

[0008]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems.

That is, a means for selecting a maximum of 4 pixels from 9 pixels around the target pixel according to a rule is provided, and the same processing is performed four times for one target original pixel.

[0010]

With the above construction, the deterioration of the image quality can be reduced as much as possible, and the pixel density conversion or enlargement processing can be performed with simple hardware.

[0011]

【Example】

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of an embodiment according to the present invention.

FIG. 2 is a diagram for explaining the pixel relationship of this embodiment.

In this embodiment, a case will be described in which vertical and horizontal magnifications are doubled or pixel density conversion is performed. 2A
~ I indicates the input original pixel. Interpolated pixels E1 to E4 are obtained by enlarging or converting the pixel of interest E.
The interpolation pixel E1 can be interpolated from the original pixels A, B, D and E. Similarly, the interpolation pixel E2 is interpolated from the original pixels B, C, E, and F, the interpolation pixel E3 is interpolated from the original pixels D, E, G, and H, and the interpolation pixel E4 is interpolated from the original pixels E, F, H, and I, respectively. You can

Representing the coefficients by which each original pixel is multiplied by K1 to K16, E1 = K1 ^* A + K2 ^* B + K3 ^* D + K4 ^* E E2 = K5 ^* C + K6 ^* F + K7 ^* B + K8 ^* E E3 = K9 ^* I + K10 ^* H + K11 ^* F + K12 ^* E4 = K13 ^* G + K14 ^* D + K15 ^* H + K16 ^* E
Becomes

At this time, since the interpolated pixels E1 to E4 are horizontally and vertically symmetrical with respect to the center of gravity of the original pixel E, the coefficients have the same value. Thus each computing equation ^{E1 = K1 * A + K2 *} B + K3 * D + K4 * E E2 = K1 * C + K2 * F + K3 * B + K4 * E E3 = K1 * I + K2 * H + K3 * F + K4 * E E4 = K1 * G + K2 * D + K3 * H + K4 * E Becomes

As is apparent from the above arithmetic expression, there are four types of multiplication coefficients, and it is possible to find all the interpolated pixels by replacing the original pixels.

FIG. 1 shows an embodiment of the hardware configuration.

In FIG. 1, 101 is an input terminal for image data, 102 is a switch circuit for selectively outputting pixel data from the input terminal 101, and 103 to 106 are data from the switch circuit 102 for coefficients K1, K2 and K, respectively.
3, a multiplier for multiplying by K4, 107 is the multiplier 103
An adder for adding the outputs of 106 to 108 and its interpolation output terminal 108.

First, the surrounding original pixels surrounding the pixel of interest E are input from the input terminal 101. The switch circuit 102 selects an original image required for the calculation of the interpolated pixel to be obtained, and outputs it to each of the multipliers 103 to 106. The multiplier 103 receives the original pixel A data and the multiplier 104 receives the original pixel B data.
Of the original pixel D to the multiplier 105, and the data of the original pixel E to the multiplier 106, and the respective arithmetic results are added by the adder 107 to obtain the interpolation result E1. Similarly, the multiplier 103 receives the data of the original pixel C, the multiplier 104 receives the data of the original pixel F, and the multiplier 105
When the data of the original pixel B is input to the multiplier 106 and the data of the original pixel E is input to the multiplier 106, E2 outputs the data of the original pixel I to the multiplier 103, the data of the original pixel H to the multiplier 104, and the multiplier 10
When the data of the original pixel F is input to 5 and the data of the original pixel E is input to the multiplier 106, E3, the data of the original pixel G to the multiplier 103, the data of the original pixel D to the multiplier 104, and the multiplier 1
When the data of the original pixel H is input to 05 and the data of the original pixel E is input to the multiplier 106, E4 is obtained. Interpolation pixels E1 to E4 for the target pixel E can be obtained by a series of four operations.

As described above, according to the present embodiment, interpolation processing for all four pixels to be obtained, that is, horizontal / vertical processing, is performed without changing the multiplication coefficient by replacing the input original pixel by the interpolation filter for one pixel. It is possible to perform double expansion or pixel density conversion processing, respectively.

(Second Embodiment) A second embodiment according to the present invention will be described in detail below with reference to the drawings.

In the case where the horizontal / vertical magnification is doubled or the pixel density conversion processing is performed, the calculation processing for conversion is the first.
Similar to the embodiment ^{E1 = K1 * A + K2 *} B + K3 * D + K4 * E E2 = K1 * C + K2 * F + K3 * B + K4 * E E3 = K1 * I + K2 * H + K3 * F + K4 * E E4 = K1 * G + K2 * D + K3 * H + K4 * E Becomes

At this time, since both horizontal and vertical are enlarged or pixel density converted at the same ratio, the multiplication coefficients K2 and K3 have the same value.

[0025] Thus arithmetic ^{expression, E1 = K1 * A + K2} * B + K3 * D + K4 * E E2 = K1 * C + K2 * F + K2 * B + K4 * E E3 = K1 * I + K2 * H + K2 * F + K4 * E E4 = K1 * G + K2 * D + K2 * H + K4 ^* It becomes E.

FIG. 3 shows a second embodiment of the present invention constructed based on the above arithmetic expression.

In FIG. 3, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 201 denotes a register, which is a multiplier 104.
The output from is temporarily stored and output to the adder 107.
The output of the adder 107 is output from 202 as an interpolation output.

The input original pixels A to I are input to the switch circuit 102 as in the first embodiment. Switch circuit 102
First, when calculating the multiplied pixel for the multiplication coefficient K2, the interpolation pixel E1, B or D, the interpolation pixel E2
Is output when F is calculated, H or F is output when the interpolation pixel E3 is calculated, and D or H is output when the interpolation pixel E4 is calculated. The pixel data input from the switch circuit 102 to the multiplier 104 is multiplied by K2 by the multiplier 104, and the register 2
Held by 01. Next, the switch circuit 102 outputs the original pixel data corresponding to each of the multipliers 103, 104 and 106. When the interpolation pixel E1 is calculated, the data of the original pixel A is output to the multiplier 103, the previous data of B or D is output to the multiplier 104, and the data of the original pixel E is output to the multiplier 106. . Similarly, when the interpolation pixel E2 is calculated, the data of the original pixel C is stored in the multiplier 103,
The multiplier 104 receives the other data of F or B output last time, the multiplier 106 receives the data of the original pixel E, and the interpolation pixel E
When 3 is calculated, the data of the original pixel I is output to the multiplier 103, the other data of H or F output last time is output to the multiplier 104, the data of the original pixel E is input to the multiplier 106, and the interpolation pixel E4 is output. When calculating, the data of the original pixel G is output to the multiplier 103, the other data of D or H output last time is output to the multiplier 104, and the data of the original pixel E is output to the multiplier 106. The outputs of the multipliers 103, 104 and 106 and the register 201 are added by the adder 107 and output from the interpolation output terminal 202 as an interpolation output. A series of operations is performed for each of the interpolation pixels E1 to E4.

The same effects as those of the first embodiment are obtained below.

(Embodiment 3) A third embodiment of the present invention will be described in detail below with reference to the drawings.

When the horizontal / vertical magnification is doubled or the pixel density conversion processing is performed, the multiplications K2 and K3 have the same value in order to perform the horizontal / vertical expansion or pixel density conversion at the same ratio. similar to the second embodiment ^{E1 = K1 * a + K2 *} B + K2 * D + K4 * E E2 = K1 * C + K2 * F + K2 * B + K4 * E E3 = K1 * I + K2 * H + K2 * F + K4 * E E4 = K1 * G + K2 * D + K2 * H + K4 ^* It becomes E.

To further summarize, E1 = K1 ^* A + K2 ^* (B + D) + K4 ^* E E2 = K1 ^* C + K2 ^* (F + B) + K4 ^* E E3 = K1 ^* I + K2 ^* (H + F) + K4 ^* E E4 = K1 ^* G + K2 ^* (D + H) ) + K4 ^* E.

FIG. 4 shows a third embodiment of the present invention constructed based on the above arithmetic expression.

In FIG. 4, the same parts as those in the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 301 denotes an adder, which is a switch circuit 10
The two outputs from 2 are added and the result is output to the multiplier 104. Reference numeral 302 denotes a multiplier, which is an adder that adds 103, 104, and 106 and outputs the result to the interpolation output terminal 303.

The input original pixels A to I are input to the switch circuit 102 as in the first embodiment. Switch circuit 102
Then, the data of the original pixel A is sent to the multiplier 103 by the multiplier 10
6 shows the data of the original pixel E, and the adder 301 shows the original pixels B and D.
Enter the data of. The output of the adder 301 is the multiplier 10
4 is input. The calculation result multiplied by each multiplier is added by the adder 302 and output as interpolation data E1 from the interpolation output terminal 303. Similarly, the multiplier 103
To the multiplier 106, the data of the original pixel E to the multiplier 106, the data of the original pixel I to the multiplier 103,
6 shows the data of the original pixel E and the adder 301 shows the original pixels H and F.
The interpolation data E3 is input to the multiplier 10
By inputting the data of the original pixel G to 3, the data of the original pixel E to the multiplier 106, and the data of the original pixels D and H to the adder 301, the interpolation data E4 can be obtained.

The same effects as those of the first embodiment are obtained below.

(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described in detail with reference to the drawings.

In the case where the horizontal / vertical expansion is performed three times or the pixel density conversion processing is performed, the interpolation pixel E as shown in FIG.
For 1, E3, E7, and E9, the same interpolation filter can be used by selectively switching the original pixel used for interpolation.
Similarly, the same interpolation filter can be used for the interpolation pixels E2, E4, E6, and E8. Since the interpolation pixel E5 and the center of gravity point overlap the original pixel E, the data of the original pixel E becomes the interpolation pixel data E5 as it is. That is, all the interpolation data E1 to E9 can be obtained by using the above two types of interpolation filters and selectively switching the original pixel data A to I input thereto.

[0041] When shown in the following calculation formula for the interpolation data ^{E1 = K1 * A + K2 *} B + K3 * D + K4 * E E3 = K1 * C + K2 * F + K3 * B + K4 * E E9 = K1 * I + K2 * H + K3 * F + K4 * E E7 = K1 * G + K2 ^* D + K3 ^* H + K4 ^* EE2 = K5 ^* B + K6 ^* EE6 = K5 ^* F + K6 ^* EE8 = K5 ^* H + K6 ^* EE4 = K5 ^* D + K6 ^* EE5 = E.

A fourth embodiment of the present invention constructed on the basis of the above arithmetic expression is shown in FIG.

In FIG. 5, the same parts as those in the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.

Numerals 401 to 404, 407 and 408 are multipliers, and multiplication coefficients of K1 to K6 are preset respectively. Reference numerals 405 and 409 denote adders, and 405 adds the multiplication results of the multipliers 401 to 404 and outputs the result to the interpolation output terminal 406. The interpolation output terminal 406 outputs interpolation data E1, E3, E7, E9. Adder 409
For example, the multiplication results of the multipliers 407 and 408 are added and output to the interpolation output terminal 410. The interpolation output terminal 410 outputs interpolation data E2, E4, E6, and E8. Reference numeral 411 is an interpolation output terminal for the interpolation data E5.

With the above configuration, the original pixel data of the peripheral pixels A to I of the pixel of interest E are selected and output from the switch circuit 102 based on the above conversion formula.

As described above, according to this embodiment, by interchanging the original pixels to be input by the two types of interpolation filters, the interpolation processing of all 9 pixels to be obtained without changing the multiplication coefficient, that is, each of the horizontal and vertical It is possible to perform a three-fold expansion or pixel density conversion processing.

(Fifth Embodiment) A fifth embodiment according to the present invention will be described in detail below with reference to the drawings.

In the case where the horizontal / vertical expansion is performed three times or the pixel density is converted, the horizontal / vertical expansion and the pixel density conversion are performed at the same ratio. Therefore, the method of the fourth embodiment further includes the method of the second embodiment. be able to. That is, since the multiplication coefficients K2 and K3 of the fourth embodiment are equal, K3 is replaced with K2 to obtain the following arithmetic expression.

E1 = K1 ^* A + K2 ^* B + K2 ^* D + K4 ^* E E3 = K1 ^* C + K2 ^* F + K2 ^* B + K4 ^* EE9 = K1 ^* I + K2 ^* H + K2 ^* F + K4 ^* E + 7 + K1 ^* G + K2 ^* D + K2 ^* D + K2 ^* D + K4 ^* E + ^* B + K6 ^* EE6 = K5 ^* F + K6 ^* EE8 = K5 ^* H + K6 ^* EE4 = K5 ^* D + K6 ^* EE5 = E.

FIG. 7 shows a fifth embodiment of the present invention constructed based on the above arithmetic expression.

In FIG. 7, the same parts as those in the first to fourth embodiments are designated by the same reference numerals and the description thereof will be omitted.

501 is a register 20 in FIG. 3 of the second embodiment.
A register having the same function as 1, 502 is a multiplier 40
1, 402, 404 and an adder that adds the outputs from the register 501, 503 is an interpolation output terminal that outputs the data from the adder 502, 504 is an interpolation output terminal that outputs the data from the adder 409, and 505 is an interpolation This is an output terminal for data E5.

With the above construction, the calculation is performed based on the above calculation formula, and the same effect as the fourth embodiment is obtained.

(Embodiment 6) A sixth embodiment of the present invention will be described in detail below with reference to the drawings.

In the case where the horizontal / vertical expansion is performed three times or the pixel density is converted, the horizontal / vertical expansion is performed at the same ratio or the pixel density is converted. Therefore, the method of the fourth embodiment further includes the method of the third embodiment. be able to. That is, since the multiplication coefficients K2 and K3 of the fourth embodiment are equal, K3 is replaced with K2 to obtain the following arithmetic expression.

E1 = K1 ^* A + K2 ^* (B + D) + K4 ^* E E3 = K1 ^* C + K2 ^* (F + B) + K4 ^* E E9 = K1 ^* I + K2 ^* (H + F) + K4 ^* E E7 = K1 ^* G + K2 ^* (D + H) + K4 ^* E E2 = K5 ^* B + K6 ^* E E6 = K5 ^* F + K6 ^* E E8 = K5 ^* H + K6 ^* E E4 = K5 ^* D + K6 ^* E E5 = E.

FIG. 8 shows a sixth embodiment of the present invention constructed based on the above arithmetic expression.

In FIG. 8, the same parts as those in the first to fifth embodiments are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 601 denotes an adder having a function similar to that of the adder 301 in FIG. 4 of the third embodiment, and 602 denotes multipliers 401 and 40.
It is an adder that adds the outputs from 2, 404.

With the above construction, the calculation is performed based on the above calculation formula, and the same effect as the fourth embodiment is obtained.

(Embodiment 7) Hereinafter, a seventh embodiment of the present invention will be described in detail with reference to the drawings.

When the horizontal / vertical expansion is performed by 4 times or the pixel density conversion processing is performed, the interpolation pixels E1, E6, E11, E16 are expanded as shown in FIG. The same interpolation filter can be used by selecting the original pixel used for interpolation. Similarly, the same interpolation filter can be used for the interpolation pixels E4, E7, E10, and E13.
2, E8, E9, E15 and interpolation pixels E3, E5, E1
The same interpolation filter can be used for 2 and E14. That is, all the interpolation data E1 to E16 can be obtained by using the above three types of interpolation filters and selectively switching the original pixel data A to I input thereto.

The seventh embodiment of the present invention is shown in FIG.

In FIG. 9, the same parts as those in the first to sixth embodiments are designated by the same reference numerals and the description thereof will be omitted.

Reference numerals 701 to 704 denote multipliers, each of which is K
The multiplication factors 1 to K4 are preset. 70
An adder 5 adds the multiplication results of the multipliers 701 to 704 and outputs the result to the interpolation output terminal 707. Interpolation output terminal 70
7 outputs interpolation data E1, E6, E11, E16.

The interpolation filter 706 is configured with the above configuration, and 708 and 710 are also configured in the same manner. In the interpolation filter 708, the multiplication coefficients K5 to K8 are set, and the interpolation output terminal 709 outputs interpolation data E4, E7, E10, E13.
Is output. Similarly, in the interpolation filter 710, the multiplication coefficients K9 to K12 are set, and the interpolation output terminal 711 outputs interpolation data E2, E8, E9, E15. Further, the output of the interpolation filter 710 is also connected to the register 712, is operated at a different time from the time of the operation, and is input and held in the register 712. The data from the register 712 is output from the interpolation output terminal 713 as interpolation data E3, E.
5, E12, and E14 are output.

The original pixel data of the peripheral pixels A to I of the target pixel E are selectively output from the switch circuit 102 and calculated.

As described above, according to the present embodiment, by interchanging the original pixels to be input by the three types of interpolation filters, interpolation processing of all 16 pixels to be obtained, that is, horizontal and vertical, respectively, without changing the multiplication coefficient. It is possible to perform a 4-fold enlargement or a pixel density conversion process.

The interpolation filters 706 and 708 are the second embodiment.
It may be realized by the methods of 3 and 3. In this case, the amount of hardware can be further reduced as compared with this embodiment.

In the first to seventh embodiments, the switch circuit is used to select and output from the original pixels A to I which are the peripheral pixels of the target pixel E, but it goes without saying that this is not the case, and it is needless to say that the memory or the like is held. The same applies to circuits.

[0071]

As described above, according to the present invention, enlargement processing or pixel density conversion processing can be performed with simple hardware.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a diagram showing a pixel relationship of a first embodiment according to the present invention.

FIG. 3 is a diagram showing a schematic configuration of a second embodiment according to the present invention.

FIG. 4 is a diagram showing a schematic configuration of a third embodiment according to the present invention.

FIG. 5 is a diagram showing a schematic configuration of a fourth embodiment according to the present invention.

FIG. 6 is a diagram showing a pixel relationship of a fourth embodiment according to the present invention.

FIG. 7 is a diagram showing a schematic configuration of a fifth embodiment according to the present invention.

FIG. 8 is a diagram showing a schematic configuration of a sixth embodiment according to the present invention.

FIG. 9 is a diagram showing a schematic configuration of a seventh embodiment according to the present invention.

FIG. 10 is a diagram showing a pixel relationship of a seventh embodiment according to the present invention.

FIG. 11 is a diagram illustrating linear interpolation of a conventional example.

[Explanation of symbols]

 101 original image data input terminal 102 switch circuits 103 to 106 multiplier 107 adder 201 register

Claims (3)

[Claims] 1. An image processing apparatus for enlarging a multi-valued image or converting a pixel density, comprising means for selecting a maximum of 4 pixels from 9 pixels including a target pixel, and means for performing an interpolation calculation using the selected pixels. An image processing apparatus characterized in that the series of processing is repeated four times for a target pixel. 2. The 9 pixels are the pixel of interest and 8 adjacent to the pixel of interest.
The image processing apparatus according to claim 1, which is a pixel. 3. The image processing apparatus according to claim 1, wherein the coefficient of the interpolation calculation means is fixed.