JPH0822276A - Automatic sampling clock adjusting method and its circuit - Google Patents

Abstract

PURPOSE:To provide a sampling clock with an optimum phase by automatically adjusting a sampling clock phase in a video signal processing circuit sampling an analog video signal by a clock pulse. CONSTITUTION:An input analog video signal S1 is made a binary signal by a binary signal making circuit 101, and the binary signal is made the sampling clock, and a zero signal and a one signal of a phase variable clock S3 formed in a clock oscillation circuit 107, a delay circuit 108 and a selector 109 are sampling-counted and compared, and the phase of the clock S3 is adjusted by the selector 109 so that the difference becomes zero, and the sampling clock signal S3 with the phase suitable for the input analog video signal S1 is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD) or a plasma display (PDP) for sampling and displaying an analog video signal at a constant frequency.
In a video signal processing circuit for sampling an analog video signal with a clock pulse as in 1), it relates to a means for generating a clock pulse having an optimum phase when the video signal periodically changes such as a character signal output from a personal computer. .

[0002]

2. Description of the Related Art An example of a circuit for setting the phase relationship between a video signal and a sampling clock is shown in FIG. 6 (JP-A-2-124).
691). The input video signal at the time of adjustment is a stationary signal, and when a signal for starting the phase matching is input from the input means 508 to the CUP 506, the CPU 506 causes the selector 511 to select one of a plurality of outputs of the delay line 510. Select and output. Input video signal S0 with its output clock
Is A / D converted by the A / D converter 501, and this is converted into the memory 5
Store in 02. Next, one of the outputs of the delay line 510, which is different from the previous one, is selected by the selector 511 and the signal A / D converted by the clock output and the video data stored in the memory 502 are sequentially compared by the comparator 503. Then, the number of different data is counted by the counter 504 and the result is calculated by the CPU 50.
Read at 6. By repeating the above in sequence, the CUP 506 sets the selector to the state of the selector 511 with the smallest count of the counter 504 and stores it in the EEPROM 507, and when the power is turned off and then turned on again, E
The state of the selector 511 is set according to the contents stored in the EPROM 507. Here, 509 is a phase locked loop (PLL) that generates an original sampling clock signal synchronized with the horizontal synchronizing signal of the video signal S0, and 505 is the A / D based on the synchronizing signal of the video signal S0 and the clock signal output from the selector 511. This is a sampling processing circuit that controls and operates the conversion circuit 501 and the memory 502.

[0003]

According to the above method of adjusting the phase of the sampling clock, when the input video signals have the same phase relationship, once set, the subsequent phases are automatically set to the optimum, and the screen is viewed. However, the trouble of manually adjusting the clock phase is eliminated. However, if different PCs are connected, or if the same PC displays different signals in different display modes, check the screen to see if it is in the optimum phase, and if there is a deviation, command the settings using the input means. , Every time the input is changed or the display mode is changed, the setting must be reset. Also, if the number of select of the selector is increased, the range where the count value is the minimum becomes wider and the optimum value becomes unclear. There is a possibility that it may be difficult to obtain an accurate optimum value, for example, it may occur easily. Furthermore, the setting is done by comparing the previous signal and the current signal stored in the memory,
A still input video signal is required, and at least two frame periods or more is required.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can convert an input video signal into a binary signal and use this binary signal as a clock to sample a sampling clock as data. The logical 0 of the result
The phase of the sampling clock is adjusted so that the difference between the number of 1 and the number of 1 is minimized.

[0005]

When the input video signal is a binary signal and the sampling clock is used as data for sampling with the binary signal as a clock, if the original phase of the sun-playing clock is optimum, the obtained results are almost 0 and 1. It should be the same number. Therefore, the optimum sampling clock can be obtained by adjusting the phase of the original clock so that the absolute value of the difference between the numbers of 0 and 1 is minimized.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The automatic adjustment of the sampling clock according to the present invention will be described in detail below with reference to the drawings. Figure 1
FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 2 is a schematic timing diagram of the same. Here, S1 is an input video signal. 101
Is a binary signal conversion circuit for slicing the image signal S1 with a certain threshold value TL to generate a binary signal S2. Reference numeral 102 is a 0 signal sampling circuit for sampling logic 0 data using the sampling clock S3 as data and the binary signal S2 as a clock, and 103 is a 1 signal sampling circuit for sampling logic 1 data. 104 and 105 are 0 respectively
It is a counter that counts the outputs of the signal sampling circuit 102 and the 1-signal sampling signal circuit 103. Reference numeral 106 is a comparator that compares the count values of the counters 104 and 105.
Reference numeral 107 is an original clock oscillator circuit that generates an original clock signal. Reference numeral 108 denotes a delay circuit that outputs a clock that is out of phase with the original clock. Reference numeral 109 denotes an output of the comparator 106, and one clock signal S3 serving as a sampling clock signal from a plurality of outputs of the delay circuit 108.
Is a selector for selecting.

As shown in FIG. 2, 2 of the input video signal S1
When the sampling clock signal S3 is sampled with the binarized signal S2, when the phase of the sampling clock is sequentially advanced, the value of the sampling point changes from logic 1 to 0, and the phase of the sampling clock is gradually delayed. The value of changes from 0 to 1. Therefore, for example, when the output of the comparator 106, which is a value obtained by subtracting the 1-signal sample frequency from the 0-signal sample frequency, is positive, the selector 109 is selected to delay the phase of the sampling clock, and when the output is negative, the selector 109 is selected to advance. Thus, the sampling clock with the optimum phase can be obtained. Although the sampling clock S3 is assumed to have a duty of 50% here, when the duty is other than 50%, a phase shift means having a constant phase is used to set a point deviated by 180 degrees from the sampling point as a phase point of the sampling clock. Just do it.

FIG. 3 is a block diagram of the second embodiment.
Here, S1 is an input video signal. 201 is a video signal S
It is a binary signal conversion circuit for slicing 1 with a certain threshold value to generate a binary signal S2. Reference numeral 202 denotes a 0 signal sampling circuit for sampling logic 0 data using the sampling clock S3 as data and the binary signal S2 as a clock.
Reference numeral 3 is a 1-signal sampling circuit for sampling logic 1 data. Reference numeral 204 denotes a CPU which inputs the outputs of the 0 signal sampling circuit 202 and the 1 signal sampling signal circuit 203 and outputs a selector selection signal. Reference numeral 205 denotes an original clock oscillation circuit that generates a clock signal as an original. Reference numeral 206 denotes a delay circuit that outputs a clock that is out of phase with the original clock. A selector 207 is an output of the CPU 204 and selects one clock signal S3 to be a sampling clock signal from a plurality of outputs of the delay circuit 206.

As shown in FIG. 2, 2 of the input video signal S1.
When the sampling clock signal S3 is sampled with the binarized signal S2, when the phase of the sampling clock is sequentially advanced, the value of the sampling point changes from logic 1 to 0, and the phase of the sampling clock is gradually delayed. The value of changes from 0 to 1. Therefore CP
When the value obtained by subtracting the 1-signal sample frequency from the 0-signal sample frequency in U204 is positive, the selector 207 is selected so as to delay the phase of the sampling clock, and when the value is negative, the selector 207 is selected to be advanced to the point where it becomes almost zero. By selecting,
A sampling clock with an optimum phase can be obtained. It is assumed that the sampling clock S3 has a duty of 50%, but when the duty is other than 50%, the phase shift means having a constant phase is used to obtain 18 from the sampling point.
The point shifted by 0 degrees may be used as the phase point of the sampling clock. In this embodiment, a CPU, which is generally mounted for various controls, is shared to obtain an automatic phase adjusting circuit for sampling clocks.

FIG. 4 is a block diagram of the third embodiment.
Here, S1 is an input video signal. 301 is the video signal S
It is a binary signal conversion circuit for slicing 1 with a certain threshold value to generate a binary signal S2. Reference numeral 302 is a 0-signal sampling circuit for sampling logic 0 data using the adjustment clock S4 as data and the binary signal S2 as a clock. Reference numeral 303 is a 1-signal sampling circuit for sampling logic 1 data. Reference numeral 304 denotes a CPU which inputs the outputs of the 0 signal sampling circuit 302 and the 1 signal sampling signal circuit 303 and outputs selection signals of two types of selectors. Reference numeral 305 is an original clock oscillation circuit that generates a clock signal as an original. Reference numeral 306 is a delay circuit that outputs a clock that is out of phase with the original clock. 307 is the CPU 304
Is a selector A that selects one clock serving as the adjustment clock signal S4 from a plurality of outputs of the delay circuit 306 by one of the outputs of the above. A selector B 308 is another output of the CPU 304 and selects one clock signal S3 to be a sampling clock signal from a plurality of outputs of the delay circuit 306.

If the input video signal S1 is periodic and requires phase matching with the sampling clock, such as a character signal from a personal computer, then the input video signal S2 is
When the adjustment clock signal S3 is sampled with the binarized signal S2, the value of the sampling point changes from logic 1 to 0 when the phase of the adjustment clock is sequentially advanced, and when the phase of the adjustment clock is delayed sequentially. , The value of sample point is 0
Changes from 1 to 1. On the other hand, when the input video signal S1 has no periodicity and does not need to be in phase with the special sampling clock like a general television signal, the value of the sampling point changes randomly. Therefore, when the value obtained by subtracting the 1-signal sample frequency from the 0-signal sample frequency is positive in the CPU 304, the selector A is arranged to delay the phase of the sampling clock.
307 is selected, and when negative, it is selected to advance and the phase point 180 degrees out of phase from the sampling phase point of the adjustment clock obtained with the selected value of the point that becomes substantially zero is the sampling point of the sampling clock S3. Selector B308 is selected and set so as to be the phase point. On the other hand, when the value obtained by subtracting the 1-signal sample frequency from the 0-signal sample frequency changes at random, the selection value of the selector B is not changed and remains at the previous setting value. In this embodiment, even if a signal having a periodicity and a signal having a random phase are exchanged, as in a multimedia display, for example, the clock phase matching does not cause a phase shift and a stable sampling clock can be obtained.

FIG. 5 shows a fourth embodiment. Here, S1 is an input video signal. Reference numeral 401 denotes a binary signal conversion circuit that slices the video signal S1 with a certain threshold value to generate a binary signal S2. 402 uses the sampling clock S3 as data,
A 0 signal sampling circuit for sampling logic 0 data using the binary signal S2 as a clock, and 403 is a 1 signal sampling circuit for sampling logic 1 data.
404 and 405 are counters for counting the outputs of the 0 signal sampling circuit 402 and the 1 signal sampling signal circuit 403, respectively. Reference numeral 406 is a comparator that compares the count values of the counters 604 and 605. A low frequency pass filter (LPF) 407 integrates the output of the comparator 406. 408
Is a voltage controlled oscillator (VC) that outputs a sampling clock S3 whose oscillation frequency changes with the output voltage from the LPF.
O).

As shown in FIG. 2, 2 of the input video signal S1.
When the sampling clock signal S3 is sampled with the binarized signal S2, when the phase of the sampling clock is sequentially advanced, the value of the sampling point changes from logic 1 to 0, and the phase of the sampling clock is gradually delayed. The value of changes from 0 to 1. Therefore, when the output of the comparator 406 is set to output a voltage proportional to the 0 signal sample frequency with reference to the 1 signal sample frequency, the voltage is integrated by the LPF 407 and the VCO 40
It takes 8. By setting the characteristics of the VCO so that the oscillation frequency increases when the applied voltage increases, a sampling clock having an optimum phase and frequency can be obtained. Although the sampling clock S3 is assumed to have a duty of 50% here, when the duty is other than 50%, a phase shift means having a constant phase is used to set a point deviated by 180 degrees from the sampling point as a phase point of the sampling clock. Just do it.
In this embodiment, an automatic adjusting circuit for the sampling clock is obtained in which not only the phase but also the frequency is automatically adjusted.

[0014]

EFFECT OF THE INVENTION In a video signal processing circuit for sampling an analog video signal with a clock pulse, such as a liquid crystal display (LCD) or a plasma display (PDP) which samples an analog video signal at a constant frequency and displays the video signal. In order to generate a clock pulse having an optimum phase when the frequency changes periodically, the input video signal is converted into a binary signal, and the sampling clock is used as the data to sample the sampling clock. By adjusting the phase of the sampling clock so that the difference between the resulting number of logical 0s and 1s is minimized,
The optimum sampling clock phase can be set automatically. Therefore, unlike the conventional case, there is no need to manually reset the setting after the phase shift occurs on the display screen, and the sampling clock with the optimum phase can always be obtained.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a first embodiment.

FIG. 2 is a schematic timing chart of the present embodiment.

FIG. 3 is a schematic block diagram of a second embodiment.

FIG. 4 is a schematic block diagram of a third embodiment.

FIG. 5 is a schematic block diagram of a fourth embodiment.

FIG. 6 is a schematic block diagram of a conventional example.

[Explanation of symbols]

 S1 input video signal S2 binarized signal of input video signal S3 sampling clock signal 101 binary signal conversion circuit 102 0 signal sampling circuit 103 1 signal sampling circuit 104 counter 105 counter 106 comparator 107 original clock oscillation circuit 108 selector 204 CPU 407 Low-frequency pass filter (LPF) 408 Voltage controlled oscillator (VCO)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/06 Z 7/24

Claims (5)

[Claims] 1. A video signal processing circuit for sampling an input video signal with clock pulses, a binary signal converting means for converting the video signal into a binary signal, and a clock signal generating means capable of controlling and adjusting phase and / or frequency. And a counting means for sampling the clock signal at the changing point of the binarized signal and counting the delay frequency and the advance frequency thereof, and a comparing means for comparing the respective count values, and the comparison value is minimized. A sampling clock automatic adjusting method for controlling the clock signal generating means to obtain a sampling clock having an optimum phase for the analog video signal. 2. A binary signal conversion circuit that outputs a logic 0 when an input video signal is below a certain amplitude level and a logic 1 when it is above a certain amplitude level, and the sampling is performed using a sampling clock as data and the binary signal as a clock. 0 signal sampling circuit for sampling 0 signal of clock and 1
A 1-signal sampling circuit for sampling a signal, and 0
A counter that counts the output frequency of the signal sampling circuit and the output frequency of the one-signal sampling circuit, a comparator that compares the count values of the counters, an original clock signal oscillation circuit, and a plurality of original clock signals. A delay circuit that outputs in different phases and a selector that selects the output of the delay circuit by the comparator and outputs the sampling clock signal are provided, and the output of the selector is the difference between the 0 signal sampling frequency and the 1 signal sampling frequency. 2. The sampling clock automatic adjustment circuit according to claim 1, wherein the output of the delay circuit is selected so as to be substantially zero. 3. A binary signal conversion circuit that outputs a logical 0 when an input video signal is below a certain amplitude level and a logical 1 when it is above a certain amplitude level, and the sampling is performed using a sampling clock as data and the binary signal as a clock. 0 signal sampling circuit for sampling 0 signal of clock and 1
A 1-signal sampling circuit for sampling a signal, and 0
A plurality of CPUs for inputting the output frequency of the signal sampling circuit and the output frequency of the one-signal sampling circuit and outputting a selector selection signal corresponding to the difference between the respective frequencies, an original clock signal oscillation circuit, and a plurality of original clock signals. The delay circuit for outputting the different phases and the output of the delay circuit for the CP
A selector that selects the output of U and outputs the sampling clock signal, and selects the output of the delay circuit so that the difference between the 0 signal sampling frequency and the 1 signal sampling frequency becomes substantially zero. The sampling clock automatic adjusting circuit according to claim 1. 4. A binary signal conversion circuit which outputs a logic 0 when an input video signal is below a certain amplitude level and a logic 1 when it is above a certain level, and the adjustment clock is data and the binary signal is a clock. The 0 signal sampling circuit for sampling the 0 signal of the clock, the 1 signal sampling circuit for sampling the 1 signal, the output of the 0 signal sampling circuit and the output of the 1 signal sampling circuit are input,
A CPU that outputs two types of selector selection signals corresponding to the respective frequency differences, an original clock signal oscillation circuit, a delay circuit that outputs the original clock signal in a plurality of different phases, and an output of the delay circuit. The selection value of the selector includes a first selector that selects one output of the CPU and outputs the adjustment clock signal, and a second selector that selects the other output of the CPU and outputs a sampling clock. When the difference between the 0-signal sampling frequency and the 1-signal sampling frequency is zero, the selected value is set as the selection value of the second selector, and the output frequency of the 0-signal sampling circuit and the 1-signal sampling signal are set. 2. The setting value of the second selector is not changed by the obtained result when the difference in the frequency of the output of the circuit randomly changes. Pump ring clock automatic adjustment circuit. 5. The sampling clock automatic adjusting circuit according to claim 1, wherein a voltage controlled oscillator is used as the clock signal generating means capable of controlling the phase and frequency.