JPH08222687A - Semic0nductor integrated circuit device - Google Patents

Abstract

PURPOSE: To elevate the packing densities in the horizontal and height direction by placing the other ends of straight leads and L-shaped leads on the same plane and covering the entire parts with resin, except the other ends. CONSTITUTION: The other ends 13b of straight leads 13 and those 14b of L- shaped leads 14 are respectively disposed with specified spacings on nearly the same plane, and the entire part, except these end parts, is covered with a seal part 15 using an insulative resin to protect bare chips 1 and 2, bump electrodes 11 and 12, one end parts 13a of the leads 13 and those 14a of the leads 14, etc., from outer environments. A package type semiconductor integrated circuit device 10 is composed of, including the chips 1 and 2, electrodes 11 and 12, straight and L-shaped leads 13 and 14 and seal part 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit for high density mounting which is mounted on electric / electronic products such as computers, various OA equipment, automobile control equipment and the like. Regarding the device.

[0002]

2. Description of the Related Art At present, a semiconductor integrated circuit device is packaged mainly in a plastic package (hereinafter referred to as PP), a ceramic package (hereinafter referred to as CP), and a T package.
CP (Tape Carrier Packge) is used (Kayama et al .: VLSI packaging technology (1); Nikkei BP, Inc .;
pp127-145). FIG. 4 is a partial cross-sectional view schematically showing a conventional PP type semiconductor integrated circuit device of this type, and reference numeral 1 in the drawing shows a bare chip as a semiconductor integrated circuit. The bare chip 1 is bonded onto the die pad 41 using a resin adhesive 41a or the like, and a plurality of leads 43 are arranged around the die pad 41. A plurality of aluminum (hereinafter, referred to as Al
Electrode 42 is formed, and the Al electrode 42 and the inner lead portion 43b of the lead 43 are connected to each other using a bonding wire 44 of Au. The whole of the lead 43 except the outer lead portion 43a side is covered with a mold 45 using a thermosetting resin or the like, and the bare chip 1, the Al electrode 42, the inner lead portion 43b, the bonding wire 44, etc. are covered by the mold 45 in the external environment. To be protected from. These bare chips 1,
The PP type semiconductor integrated circuit device 40 is configured to include the bonding wires 44, the leads 43, the mold 45, etc., and the height H _PP of the semiconductor integrated circuit device 40 is 115.
It is about 0 μm. In the semiconductor integrated circuit device 40 configured in this manner, signals, power, etc. are input from the predetermined outer lead portion 43a to the circuit in the bare chip 1 via the inner lead portion 43b, the bonding wire 44, and the Al electrode 42. The signal processed by the circuit in the bare chip 1 is output to the predetermined outer lead portion 43a via the reverse path. When the semiconductor integrated circuit device 40 having the above-described structure is mounted on a circuit board (not shown), the outer lead portion 4 is provided at a predetermined position on the circuit board.
Surface mounting is performed by adhering 3a by a reflow soldering method.

FIG. 5 is a partial sectional view schematically showing a conventional CP type semiconductor integrated circuit device.
Indicates a bare chip. The bare chip 1 has a cavity 51a formed in the ceramic package substrate 51.
It is adhered to the upper surface using a resin adhesive 51b or the like. A plurality of leads 53 formed into, for example, a hook shape are adhered to the periphery of the upper portion of the ceramics package substrate 51 using a resin adhesive 51b or the like.
The outer lead portion 53a side of 3 is guided to the outside of the ceramic package substrate 51. A plurality of Al electrodes 52 are formed around the upper surface of the bare chip 1,
The Al electrode 52 and the inner lead portion 53b of the lead 53 are connected to each other using an Al bonding wire 54. A metal or ceramic lid 55 is arranged above the ceramics package substrate 51 so as to cover the ceramics package substrate 51. The lid 55 and the ceramics package substrate 51 are sealed by a sealing portion 56 made of low-melting glass or the like.
Is sealed by the bare chip 1, the Al electrode 52,
The inner lead portion 53b, the bonding wire 54, etc. are protected from the external environment. These bare chip 1, ceramic package substrate 51, lid 5
5, including bonding wire 54, lead 53, etc.
A P-type semiconductor integrated circuit device 50 is configured,
The height H _CP of the semiconductor integrated circuit device 50 is 2000 to 250.
It is about 0 μm. CP5 configured in this way
When 0 is mounted on a circuit board (not shown), the outer lead portions 53a are surface-mounted by adhering the outer lead portions 53a to predetermined portions of the circuit board by a reflow soldering method.

FIG. 6 is a partial cross-sectional view schematically showing a conventional TCP type semiconductor integrated circuit device. In FIG. 6, reference numeral 1 shows a bare chip 1 as a semiconductor integrated circuit. A plurality of bump electrodes 61 having a substantially ball shape are formed around the upper surface of the bare chip 1, and the inner lead portions 62b of the tape carrier are bonded to the bump electrodes 61, respectively. In addition, the upper surface and the side surface of the bare chip 1, the bump electrode 61, and the inner lead portion 62b.
Is covered with a potting sealing portion 63 made of resin, and the outer lead portion 62a side of the lead 62 is guided to the outside of the potting sealing portion 63.
3, the bump electrode 61 and the like are protected from the external environment. These bare chips 1 and bump electrodes 6
1, including the lead 62, the potting seal 63, etc.
The CP type semiconductor integrated circuit device 60 is configured, and the height H _TCP of the semiconductor integrated circuit device 60 is 450 μm.
It has become a degree. When the semiconductor integrated circuit device 60 configured as described above is mounted on a circuit board (not shown), the outer lead portion 62a is surface-mounted by adhering the outer lead portion 62a to a predetermined portion of the circuit board by a reflow soldering method.

However, the above-mentioned PP type semiconductor integrated circuit device 40 and CP type semiconductor integrated circuit device 5 are used.
In each of the 0 and TCP type semiconductor integrated circuit devices 60, one bare chip 1 is arranged in a plane, and the size of the semiconductor integrated circuit devices 40, 50, 60 is larger than the size S _{BC of the} bare chip 1. There is a problem that S _PP , S _CP and S _TCP are likely to be large, and the mounting density of the bare chips 1 in the horizontal direction is reduced.

In order to address this problem and reduce the size of the package body by setting the space occupied by the inner lead portion 53b in the semiconductor integrated circuit device 50 shown in FIG. 5 to be small, the width of the lead is small and the space between the leads is small. QFP (F) (Fine Pitch Q) with a narrow pitch
uad Flat Package) has been developed (Internepcon Osaka '92 Seminar Text; Industrial Research Committee; pp 2-1
1).

Further, the semiconductor integrated circuit device 5 shown in FIG.
Outer lead portion 53a protruding horizontally at 0
To eliminate this, a PGA (Pin Grid Array) type in which a plurality of electrode pins are erected on the lower surface of the ceramic package substrate 51 instead of the lead 53 has been developed (Morimatsu: LSI design and manufacturing technology; Pp404-40
6). The electrode pin is connected to the Al electrode 52 via a through hole formed in the ceramic package substrate 51, a pad (not shown) formed on the ceramic package substrate 51, and a bonding wire 54. When the PGA type semiconductor integrated circuit device thus configured is mounted on a circuit board, it is mounted by inserting the electrode pin into a hole formed in the circuit board.

Although not shown, in order to increase the mounting density in the horizontal direction, a plurality of leads are collectively formed on one side of the package, and the package is mounted vertically with the leads facing downward. (Vertical Sur
face mount package) is being developed. (Kayama and others:
VLSI packaging technology (bottom); Nikkei BP Company; pp17
9-180).

In order to increase the packaging density in the horizontal direction, a type in which packages or bare chips are stacked in a space in the vertical direction has been developed. FIG. 7 shows the conventional T
FIG. 3 is a partial cross-sectional view schematically showing a CP stacking mounting method (Kayama et al .: VLSI packaging technology (bottom); Nikkei BP Co .; pp180-181), and 1 in the drawing shows a bare chip. A plurality of electrodes (not shown) are formed on the lower surfaces of the four bare chips 1, and the inner lead portions 71b to 74b of the leads 71 to 74 of the TAB (Tape Automated Bonding) tape are formed on the electrodes, respectively. Bonded. The bottom surface and the side surface of the bare chip 1 and the inner lead portions 71b to 74b are covered with a sealing portion 72 made of epoxy resin.
2 protects the inner lead portions 71b to 74b and the like from the external environment. The outer lead portions 71a to 74a of the leads 71 to 74 are guided to the outside of the sealing portion 72, and the lengths of the outer lead portions 71a to 74a are the same as those obtained when the semiconductor integrated circuit devices 70a to 70d are stacked. The lower portions of the lead portions 71a to 74a are set so as to be substantially flush with each other. The TCP type semiconductor integrated circuit devices 70a to 70d including the bare chip 1, the leads 71 to 74, the sealing portion 72 and the like.
Is configured. When mounting the semiconductor integrated circuit devices 70a to 70d configured in this way on the wiring board 5, first, the semiconductor integrated circuit devices 70a, 70b, ... Are stacked in order from the bottom, and the outer lead portion 71 is provided on each predetermined electrode 5a.
After mounting a, 72a, ..., These and each electrode 5a are connected by a predetermined method.

FIG. 8 is a cross-sectional view schematically showing a conventional bare chip stacking and mounting system (Japanese Patent Laid-Open No. Hei.
No. 38847), 6 in the figure indicates an insulating substrate. The insulating substrate 6 has a recess 6c formed therein. The upper surface of the recess 6c, the inside of the insulating substrate 6 following this, and the insulating substrate 6
Conductor patterns 6a and 6b are formed on the upper surface. The bare chip 1 is disposed in the recess 6c, and a plurality of bump electrodes 81 having a substantially ball shape are formed around the lower surface of the bare chip 1. The bump electrodes 81 are flip-chip mounted on the conductor pattern 6a. . The bare chip 2 is arranged above the bare chip 1, and a plurality of electrodes 82 are formed around the upper surface of the bare chip 2. A TAB tape lead 83 is provided on the electrode 82.
While one end of each of the
The other end of 3 is connected to the conductor pattern 6b by thermocompression bonding or the like. Bare chips 1 and 2, leads 83 and recess 6c
Is covered with a sealing portion 84 using a chip coat resin, and the sealing portion 84 protects the bare chips 1, 2 and the like from the external environment.

FIG. 9 is a sectional view schematically showing another conventional bare chip stacking type package type (Japanese Patent Laid-Open No. 3-198367), and 91 in the figure shows a ceramic package substrate. A plurality of electrodes 91a are formed on the upper surface of the ceramic package substrate 91, and a plurality of PGAs are formed on the lower surface of the ceramic package substrate 91.
System electrode pin 91b is formed.
b and the electrode 91a are connected to the wiring layer 91c and the through hole 91d.
Are respectively connected via. A cavity 91e is formed in the ceramic package substrate 91, the bare chip 1 is disposed in the cavity 91e, and the bare chip 1 is bonded to the upper surface of the cavity 91e by using an adhesive 92 or the like. A plurality of bump electrodes 93a having a substantially ball shape are formed around the upper surface of the bare chip 1, and the bump electrodes 93a are the leads 94 of the lead frame.
While being bonded to one end of the lead 94, the other end of the lead 94 is connected to a predetermined electrode 91a. Further, the bare chip 2 is disposed above the bare chip 1, and a plurality of bump electrodes 93b having a substantially ball shape are formed on the bottom surface of the bare chip 2 facing the bump electrodes 93a. The bump electrodes 93b are leads 94. Is bonded to one end of the. A substantially box-shaped frame body 96 is adhered to the outer periphery of the upper surface of the ceramic package substrate 91 via a metal frame 95. Has been done. Further, a lid body 97 is provided above the bare chip 2 and the frame body 96, and the lid body 97 and the frame body 96 are connected to each other using solder 99. Further, a sealing portion 98 made of an insulating resin is formed between the inner surface of the opening 96a of the frame body 96 and the lower surface of the lid body 97 and the upper surface of the bare chip 2. The frame body 96, the lid body 97, and the sealing portion. The bare chips 1, 2, the leads 94, the electrodes 91a, etc. are protected by 98 or the like from the external environment. A semiconductor integrated circuit device 90 is configured by including the bare chips 1 and 2, the ceramics package substrate 91, the electrode pins 91b, the frame body 96, the lid body 97, and the like. When the semiconductor integrated circuit device 90 configured as described above is mounted on a circuit board (not shown), it is mounted by inserting the electrode pins 91b into the holes formed in the circuit board.

[0012]

In the above semiconductor integrated circuit devices 40, 50 and 60, the mounting density in the horizontal direction is low as described above. In the semiconductor integrated circuit devices 40 and 50, the height H of the bare chip 1 is
The height of each package is H _PP compared to _BC (about 350 μm),
The H _CP increases, and the mounting density of the bare chips 1 in the height direction decreases. Further, in the semiconductor integrated circuit device 60, the entire bare chip 1 is not covered with the potting sealing portion 63, and there is a problem that sealing is insufficient.

Further, in the above QFP (F), the improvement of the mounting density in the horizontal direction is still insufficient. In the PGA type semiconductor integrated circuit device described above, the height of the entire package is increased by the electrode pins, the mounting density in the height direction is reduced, and the coupling structure of the electrode pins is weak in strength. When mounting on a circuit board, it is troublesome to insert the electrode pin into the hole of the circuit board. Further, the VSMP described above has a problem that the mounting density in the height direction is extremely low.

Further, in the above-mentioned TCP stack mounting type, the entire semiconductor integrated circuit devices 70a to 70d are not packaged, and the handling thereof is troublesome, and the entire bare chip 1 is sealed by the sealing portion 72. Is not covered by, and the sealing is insufficient. Further, when the wiring board 5 is mounted, it is difficult to adjust the length and angle of the outer lead portions 71a to 74a and to position the outer lead portions 71a to 74a with respect to the electrode 5a, which causes a problem of cost increase.

In the bare chip stacking and mounting system shown in FIG. 8, the entire packaging including the two bare chips 1 and 2 is not intended, and the handling of these is troublesome. Further, when mounted on the insulating substrate 6, it is difficult to adjust the length and angle of the lead 83, and it is difficult to accurately position the bump electrode 81 and the other end of the lead 83 on the conductor patterns 6a and 6b. Further, there is a problem that it is difficult to flip-chip mount the conductor pattern 6a and the bump electrode 81, and the cost is high.

The semiconductor integrated circuit device 90 shown in FIG.
In, the height of the entire semiconductor integrated circuit device 90 is increased by the electrode pin 91b, and the mounting density in the height direction is reduced. Further, there is a problem that the coupling structure of the electrode pin 91 is weak in strength and it is troublesome to insert the electrode pin 91b into the hole of the circuit board when the electrode pin 91 is mounted on the circuit board.

The present invention has been made in view of the above problems, and it is possible to increase the mounting density in the horizontal and height directions, to achieve overall packaging, to facilitate handling, and to provide a bare chip. Etc. can be reliably protected from the external environment, the bare chips and leads can be easily and accurately positioned during manufacturing, and they can be easily surface-mounted on the circuit board, which can reduce costs. An object is to provide a semiconductor integrated circuit device.

[0018]

To achieve the above object, in a semiconductor integrated circuit device according to the present invention, one end of a plurality of straight leads is connected to a predetermined position of one bare chip and the other bare chip is connected. One end of a plurality of L-shaped leads is connected to a predetermined location, these bare chips are bonded on the back surface, and the other ends of the straight type lead and the L-shaped lead are arranged on substantially the same plane. It is characterized in that the entire part except the other end side is covered with resin.

[0019]

According to the semiconductor integrated circuit device having the above structure, one end of a plurality of straight leads is connected to a predetermined position of one bare chip and one end of a plurality of L-shaped leads is connected to a predetermined position of the other bare chip. , The bare chips are adhered on the back surface, the other ends of the straight lead and the L-shaped lead are arranged on substantially the same plane, and the whole other than the other end is covered with resin. Therefore, since the two bare chips are stacked three-dimensionally and there is no electrode pin formed in the conventional PGA method, the mounting density in the horizontal and height directions can be increased at the same time. Further, since the two bare chips and the leads are integrally fixed and completely covered with the resin, the entire package can be achieved, and the handling can be facilitated. Thus, each bare chip and each lead can be reliably protected from the external environment. Further, when stacking and fixing the two bare chips to which one end of each lead is connected, by using a sprocket hole formed in each lead carrier tape, each bare chip can be easily and accurately It can be positioned. Further, since the other end of the straight lead and the other end of the L-shaped lead are arranged on substantially the same plane, when these are placed on a circuit board and connected by a reflow soldering method or the like, It can be easily surface-mounted on the circuit board. As a result, the manufacturing cost and the mounting cost can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings. Note that components having the same functions as those of the conventional example are denoted by the same reference numerals.
FIG. 1 is a cross-sectional view schematically showing an embodiment of a semiconductor integrated circuit device according to the present invention, in which 1 and 2 show bare chips as a semiconductor integrated circuit. The upper surface 1b of the bare chip 1 and the lower surface 2a of the bare chip 2 are bonded and fixed using an insulating adhesive 16 or the like, and a substantially ball shape is formed around the lower surface 1a of the bare chip 1 and the upper surface 2b of the bare chip 2. A plurality of bump electrodes 11 and 12 are formed respectively. One end 13a of a straight lead 13 forming a carrier tape (not shown) is bonded to the bump electrode 11, and one end of an L-shaped lead 14 forming a carrier tape (not shown) is formed on the bump electrode 12. The parts 14a are respectively bonded. On the other hand, the other end 13b of the straight lead 13
And the other end portion 14b of the L-shaped lead 14 are arranged on the substantially same plane with a predetermined interval. Further, the entire portion except the other end portions 13b and 14b is covered with a sealing portion 15 using an insulating resin, and the sealing portion 15 covers the bare chips 1 and 2, the bump electrodes 11 and 12, and the straight leads 13. One end 13a, one end 1 of the L-shaped lead 14
4a and the like are protected from the external environment. A package type semiconductor integrated circuit device 10 is configured including the bare chips 1 and 2, the bump electrodes 11 and 12, the straight leads 13, the L-shaped leads 14, and the sealing portion 15. The height H is 1000 μm. It has become a degree.

When the semiconductor integrated circuit device electrode 10 thus constructed is mounted on a circuit board (not shown), the lower surface of the other end 13b of the straight lead 13 and an L-shape are formed at predetermined positions on the circuit board. When the lower surface of the other end 14b of the lead 14 is adhered by a reflow soldering method or the like, it is surface-mounted. The semiconductor integrated circuit device pole 10 configured as described above
Then, from the straight lead 13 and the L-shaped lead 14 where the signal and power from the circuit board are predetermined, the bump electrode 1
Signals input to the circuits in the bare chips 1 and 2 via 1 and 12 or processed by the circuits in the bare chips 1 and 2 are output to the circuit board via the reverse paths.

Next, a method of manufacturing the semiconductor integrated circuit device 10 thus configured will be described with reference to FIGS. 2 and 3 are a plan view and a perspective view schematically showing the manufacturing process of the semiconductor integrated circuit device according to the embodiment.
(A) is a state where one bare chip is bonded to an L-shaped lead of a carrier tape, (b) is a state where the other bare chip is bonded to a straight lead of a carrier tape, (c) is a carrier tape of (b) (A) is a state in which the carrier tape is overlaid, (d) is a state in which two bare chips are covered by the sealing portion ((a)
(Upward and downward directions are opposite to the case of (c)),
In FIG. 3, the carrier tape is omitted. First, one end 13a of the straight lead 13 on the carrier tape 23 and the bump electrode 11 on the upper surface of the bare chip 1 (FIG. 1).
And are bonded (FIG. 2A and FIG. 3A). Also, one end 14a of the L-shaped lead 14 on the carrier tape 24 and the bump electrode 12 on the lower surface of the bare chip 2 (FIG. 1).
And are bonded (FIG. 2 (b), FIG. 3 (b)). Next, stack the carrier tape 24 on the carrier tape 24,
After positioning the pins 25 through two or more sprocket holes 23a, 24a formed in the carrier tapes 23, 24, an insulating adhesive 16 (FIG. 1) is injected between the facing surfaces of the bare chips 1, 2. These are adhered (FIG. 2 (c), FIG. 3 (c)). Next, insert this into a molding die (not shown) and inject an insulating resin,
The sealing portion 15 is formed around the bare chips 1 and 2, and the carrier tapes 23 and 24 are removed thereafter, whereby the semiconductor integrated circuit device 10 is manufactured.

As is apparent from the above description, in the semiconductor integrated circuit device 10 according to the embodiment, one end portion 1 of a plurality of straight leads 13 is provided at a predetermined position of one bare chip 1.
3a is connected, one end portion 14a of a plurality of L-shaped leads 14 is connected to a predetermined position of the other bare chip 2, these bare chips 1 and 2 are adhered on the back surfaces 1b and 2a, and the straight leads 13 and L The other ends 13b and 14b of the character-shaped lead 14 are arranged on substantially the same plane, and the entire part except the other ends 13b and 14b is covered with the sealing part 15 made of resin. Bare chips 1, 2
Since they are stacked three-dimensionally and there is no electrode pin formed in the conventional PGA method, the mounting density in the horizontal and height directions can be increased at the same time. Also 2
The individual bare chips 1 and 2 and the leads 13 and 14 are integrally fixed by the sealing portion 15 and completely covered, so that the entire packaging is achieved and the handling is facilitated. Each bare chip 1, 2 and each lead 1
It is possible to reliably protect the parts 3 and 14 from the external environment. Further, when the two bare chips 1 and 2 to which the one ends 13a and 14a of the leads 13 and 14 are connected are stacked and fixed, the carrier tapes 23 and 24 for the leads 13 and 14 are fixed.
By using the sprocket holes 23a and 24a formed in the above, the bare chips 1 and 2 can be positioned easily and accurately. Further, since the other end portion 13b of the straight lead 13 and the other end portion 14b of the L-shaped lead 14 are arranged on substantially the same plane, they are placed on the circuit board and connected by a reflow soldering method or the like. Then, the circuit board can be easily surface-mounted. As a result, the manufacturing cost and the mounting cost can be reduced.

Although the bare chips 1 and 2 are adhered by the insulating adhesive 16 in the above-described embodiment, the sealing portion 15 is filled instead of the insulating adhesive 16. May be. In this case,
Use a molding die with two or more pins erected,
After positioning these pins through the sprocket holes 23a and 24a formed in the carrier tapes 23 and 24 and then injecting an insulating resin, the bare chips 1, 2
Similar to the surrounding area, the sealing portion 15 is formed between the bare chips 1 and 2, and these are fixed.

Further, in the above-mentioned embodiment, the case where the other ends 13b and 14b of the leads 13 and 14 are linear has been described, but depending on the standard, forming such as bending to the other ends of the leads may be performed. It may be done.

[0026]

As described above in detail, in the semiconductor integrated circuit device according to the present invention, one end of a plurality of straight leads is connected to a predetermined location of one bare chip, and the other bare chip has a predetermined location. Are connected to one ends of a plurality of L-shaped leads, these bare chips are bonded to the back surface, and the other ends of the straight leads and the L-shaped leads are arranged on substantially the same plane, and the other ends thereof are arranged. Since the whole except the part side is covered with resin, the two bare chips can be stacked three-dimensionally and the conventional PGA can be stacked.
Since there is no electrode pin formed in the conventional method, the mounting density in the horizontal and height directions can be increased at the same time.
Further, since the two bare chips and the leads are integrally fixed and completely covered with the resin, the entire packaging is achieved, the handling is facilitated, and The bare chip and each lead can be reliably protected from the external environment. Further, when stacking and fixing the two bare chips to which one end of each lead is connected, by using the sprocket holes formed in the carrier tape for each lead, the bare chips can be positioned easily and accurately. can do. Further, since the other end of the straight lead and the other end of the L-shaped lead are arranged on substantially the same plane, when these are placed on a circuit board and connected by a reflow soldering method or the like, It can be easily surface-mounted on the circuit board. As a result, the manufacturing cost and the mounting cost can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a plan view schematically showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment, (a) is a carrier tape in which one bare chip is bonded to an L-shaped lead, and (b) is the other. A carrier tape in which a bare chip is bonded to a straight lead, (c) is a state in which the carrier tape in (a) is overlaid on the carrier tape in (b), and (d) is two bare chips by a sealing portion. It shows a covered state (vertical direction is opposite to that in the case of (a) to (c)).

FIG. 3 is a perspective view schematically showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment, (a) shows a state in which one bare chip is bonded to an L-shaped lead (1),
(B) is a state where the other bare chip is bonded to the straight lead (2), (c) is a state where one bare chip is overlaid on the other bare chip, and (d) is a state where two bare chips are sealed. State ((a) ~
The vertical direction is opposite to that in the case of (c)), and the carrier tape is omitted in both cases.

FIG. 4 is a partial cross-sectional view schematically showing a conventional plastic package type.

FIG. 5 is a partial sectional view schematically showing a conventional ceramic package type.

FIG. 6 is a partial sectional view schematically showing a conventional TCP type.

FIG. 7 is a partial cross-sectional view schematically showing a conventional TCP stacking and mounting system.

FIG. 8 is a sectional view schematically showing a conventional bare chip stacking and mounting system.

FIG. 9 is a sectional view schematically showing a conventional bare chip stacking package type package.

[Explanation of symbols]

 1, 2 Bare chip 1b Upper surface 2a Lower surface 10 Semiconductor integrated circuit device 13 Straight lead 14 L-shaped lead 13a, 14a One end 13b, 14b The other end 15 Sealing part

Claims (1)

[Claims] 1. One bare chip is connected to one end of a plurality of straight leads at a predetermined location, and one bare chip is connected to one end of a plurality of L-shaped leads at a predetermined location of the other bare chip. A semiconductor integrated structure characterized in that the other ends of the straight type lead and the L-shaped lead are adhered to each other and are substantially coplanar with each other, and the entire part except the other end side is covered with resin. Circuit device.