JPH08222579A - Field effect transistor - Google Patents

Abstract

PURPOSE: To suppress the drop of allowance in operation based on the temperature change of a field effect type transistor without incurring size up or increase of power consumption by compensating the temperature change of threshold voltage with a protective insulating film itself which compensates the said temperature change by the temperature change of film stress. CONSTITUTION: A GaAs layer 12, an AlGaAs layer 13, a GaAs layer 14, an Inlays layer 15, an n-type AlGaAs layer 16, and an n-type GaAs layer 17 are epitaxially grown in order on a semiinsulating GaAs substrate 11. Next, recess structure is made by etching the n-type GaAs layer, and WSi/Pt/Au is stacked, and this is patterned to form a gate electrode 18. Subsequently, it is covered with AuGe/Ni/Au, and is patterned and sintered to form an ohmic electrode 18. To compensate the dependency on temperature of threshold voltage, the whole is covered with an insulating film 20 inclusive of the gate part, selecting a silicon nitride-oxide film which has temperature coefficient of the film stress of 9×10<6> dyn/cm<2> . deg.C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor, and more particularly to a field-effect transistor in which the piezoelectricity of a substrate is utilized to minimize the fluctuation of the threshold voltage of the transistor due to temperature change. is there.

[0002]

2. Description of the Related Art At present, an L-type field-effect transistor using a III-V compound semiconductor such as GaAs is integrated.
Research and development related to SI is being actively conducted, and one of the main themes is low power consumption. To reduce the power consumption, lowering the power supply voltage is effective. However, when the power supply voltage is lowered, the margin of the threshold voltage that enables the circuit operation becomes small.

On the other hand, regardless of the power supply voltage, the threshold voltage of a field effect transistor changes depending on the temperature such as the height of the Schottky barrier between the gate metal and the substrate material and the carrier concentration in the semiconductor substrate. Therefore, it fluctuates depending on the temperature. Therefore, the temperature range in which the circuit can operate is limited. Further, the decrease in the margin due to the temperature change becomes more remarkable as the power supply voltage is lowered.

Therefore, in order to stably operate the LSI irrespective of the temperature change, it has been attempted to compensate the fluctuation of the threshold voltage due to the temperature change by some means. The first method is disclosed in JP-A-61
JP-A-160960, which discloses a substrate potential setting circuit capable of detecting a substrate temperature and compensating for a threshold voltage of a field effect transistor caused by the temperature. It is provided inside.

In the second method, as shown in Japanese Patent Laid-Open No. 1-137701, when a field effect transistor is formed on GaAs, a side gate is arranged near the field effect transistor and a side gate voltage is applied. Is controlled according to the ambient temperature to suppress the fluctuation of the threshold voltage due to the ambient temperature change. This temperature compensation method requires a temperature detection circuit for detecting the ambient temperature, and also needs to provide a side gate close to the transistor.

[0006]

The conventional example described in the above publication requires a temperature detection circuit, a compensation circuit, or a side gate, which makes the circuit complicated and increases the number of parts. Therefore, it becomes an obstacle to integration. Further, in these conventional examples, the power consumption increases due to the additional circuit, which goes against the tendency of low power consumption. Furthermore, in the example in which the side gate is provided, the operating speed also decreases. Therefore, an object of the present invention is to enable self-compensation for temperature fluctuations of the threshold voltage without increasing the number of parts, and to increase the size and power consumption of a field-effect transistor. It is to be able to suppress the decrease of the operational margin due to the temperature change.

[0007]

To achieve the above object, according to the present invention, there is provided a field effect transistor formed on a semiconductor substrate having piezoelectricity, wherein the field effect transistor comprises: There is provided a field-effect transistor characterized in that a protective insulating film for compensating the temperature fluctuation of the threshold voltage of the field-effect transistor by the temperature change of the film stress is formed.

[0008]

In the field effect transistor formed as described above, the fluctuation of the threshold voltage due to the temperature change can be corrected by the field effect transistor itself. Field effect transistors using piezoelectric substrate materials include:
For example, October 1984, I E E E
Transactions on Electrotron Devices, ED-31, No. 10 (PMAsbeck et al .; IE
EE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, N
O. 10, OCTOBER, 1984), it is known that the threshold voltage changes due to the piezo effect due to the passivation formed on the field effect transistor and the film stress of the interlayer insulating film. There is. Since the film stress changes depending on the temperature, the fluctuation of the threshold voltage due to the piezo effect follows the temperature change.

For example, in a field effect transistor in which the substrate material is GaAs, the gate length is 0.25 μm and the insulating film thickness is 1 μm between the film stress and the threshold voltage.
As m, the relationship shown in FIG. 1 is established. That is, the threshold voltage changes almost linearly with the change of the film stress. The temperature coefficient of the insulating film stress is -1.5 to 10 × 10 ⁶ dyn / c by changing the material and film quality with negative compressive stress and positive tensile stress.
It can be changed within the range of m ² · ° C. Since the stress of the insulating film changes linearly according to its own temperature coefficient, the piezo effect exerted by the insulating film eventually changes the threshold voltage in proportion to the temperature change. You will be able to On the other hand, the threshold voltage of the field effect transistor varies with a temperature coefficient of about -1 to -2 mV / ° C when the insulating film is not formed.

FIG. 2 is a diagram showing the relationship between the temperature and the change in threshold voltage in the above-mentioned field effect transistor. In FIG. 2, the horizontal axis represents temperature and the vertical axis represents the amount of change in threshold voltage. In the calculation of the amount of change in threshold voltage due to the piezo effect shown in FIG. 2, it is assumed that the gate length is 0.25 μm and the thickness of the insulating film is 1 μm. From FIG. 2, the temperature coefficient range of the threshold voltage fluctuation due to temperature change is -1 to -2 mV / ° C, and the temperature coefficient range of the threshold voltage fluctuation due to the piezo effect is about -0.2 to. It is 1.7 mV / ° C. Therefore, with the threshold voltage fluctuation caused by this piezo effect,
It can be seen that the temperature variation of the threshold voltage of the field effect transistor can be compensated.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 3 is a partially enlarged cross-sectional view of a field effect transistor according to an embodiment of the present invention. This embodiment relates to a transistor having a high electron mobility. This transistor is manufactured as follows.

Semi-insulating GaA having (100) plane as main surface
On the s substrate 11, by a molecular beam epitaxial (MBE) method, a buffer layer having a thickness of about 400 nm and an undoped GaAs layer 12 and a buffer layer having a thickness of about 200 nm are formed.
And an undoped AlGaAs layer 13, a buffer layer having a thickness of about 60 nm and an undoped GaAs layer 14, and a channel layer having a thickness of about 15 nm, undoped InGaAs.
The layer 15, the n-type AlGaAs layer 16 having a film thickness of about 30 nm and the impurity concentration of about 2 × 10 ¹⁸ cm ⁻³ to be the electron supply layer, the contact layer having a film thickness of about 600 nm to have an impurity concentration of about 4
The n-type GaAs17 of × 10 ¹⁸ cm ^-3, were sequentially epitaxially grown.

Next, the direction in which the drain current flows is [01
1] with n-type GaA using a photoresist as a mask.
The s layer 30 is etched to form a recess structure, WSi / Ti / Pt / Au is deposited by sputtering and vapor deposition, and this is patterned to form the gate electrode 18. Subsequently, AuGe / Ni / Au is deposited, and patterning and sintering are performed to form the ohmic electrode 19. As a result, the transistor structure before the formation of the insulating film (passivation film) is completed.

Here, as shown in FIG. 4, the temperature dependence of the threshold voltage before the formation of the insulating film is -1.5 mV / ° C.
Met. In order to compensate for the temperature dependence of the threshold voltage, an insulating film having a temperature coefficient of film stress of 9 × 10 ⁶ dyn / cm ² · ° C. is required (see FIG. 1). On the other hand, for the insulating film, materials (SiO 2, SiON, S
iN, AlN, etc., film forming method (sputtering method, thermal CV)
The temperature coefficient of the stress has been investigated in advance according to the film forming conditions (D method, plasma CVD method, etc.). here,
A silicon oxynitride film (SiON) formed by the plasma CVD method is selected as an insulating film capable of realizing a temperature coefficient of film stress of 9 × 10 ⁶ dyn / cm ² · ° C. And
The insulating film 20 covering the whole including the gate portion is controlled to have a film thickness of 1.0 under the control of film forming conditions capable of realizing the above temperature coefficient.
μm.

FIG. 4 shows the temperature dependence of the threshold value of the transistor after being covered with the insulating film 20 in comparison with the state before being covered with the insulating film. In FIG. 4, the horizontal axis represents temperature and the vertical axis represents the amount of change in threshold voltage. It can be seen from FIG. 4 that the temperature dependence of the threshold voltage that existed before the insulating film was formed was almost eliminated after the insulating film was formed. This is because the temperature dependence of the original threshold voltage was compensated by the temperature dependence of the threshold voltage caused by the piezoelectric effect due to the film stress of the insulating film.

In the above description, G is used as the substrate material.
AAs was used, but instead of this, SiGe, In
P, InAlAs, GaSb, InSb, GaInP,
Other semiconductor materials having piezoelectricity such as GaN may be used. Usually, in a field effect semiconductor device using a compound semiconductor, the threshold voltage (original transistor) has a negative temperature dependence. On the other hand, in the case of using a compound semiconductor substrate, when the (100) plane is selected as the substrate main surface and the direction of the drain current is the [011] direction, the compressive stress of the insulating film is negative and the tensile stress is positive, and the insulating film is There is a positive proportional relationship between the change in threshold voltage due to the piezo effect and the film pressure. Therefore, when the current direction is selected in this direction, the temperature coefficient of stress of the insulating film needs to be positive, with compressive stress being negative and tensile stress being positive.

On the other hand, (100)
When the direction of the drain current is [01-1] ("-1" means that 1 has an upper line) direction using the plane, the change in the threshold voltage due to the piezo effect of the insulating film There is a negative proportional relationship with the membrane pressure. Therefore, when selecting the current direction of the transistor in the [01-1] direction,
The temperature coefficient of stress of the insulating film needs to be negative, with compressive stress being negative and tensile stress being positive.

Further, in the above embodiment, the n-type AlGaAs layer 16 which is the electron supply layer is uniformly doped with impurities. However, instead of this method, δ doping (high impurity concentration in the layer) Forming a thin layer). In addition, channel doping may be performed. Also, Al, Ti / A as the gate electrode material
Other materials such as u that can form a Schottky junction may be used, and the ohmic electrode may be formed of AuMg, NiG, or the like.
Other ohmic electrode materials such as e may be used. Further, the ohmic electrode may be formed by a non-alloy contact method using Ti / Pt / Au or the like.

As the insulating film material, in addition to the above-mentioned materials, a material usually used as a passivation film can be appropriately used. Furthermore, you may make it form the composite film of those materials. When a composite film is used, a film having a temperature coefficient that is difficult to achieve with a single film can be realized. Note that the protective insulating film formed over the transistor can be formed over the entire surface of the wafer with the same material, or different materials can be used depending on the transistor. Further, the present invention can be applied not only to the field effect transistor having the MES structure but also to the insulated gate transistor.

[0020]

As described above, in the field effect transistor according to the present invention, the fluctuation of the threshold voltage due to the temperature change is compensated for by the piezo effect caused by the temperature change of the film stress, so that the environmental temperature change As a result, the threshold voltage does not fluctuate, and it is possible to secure a margin of circuit operation with respect to temperature changes. Further, in the field effect transistor according to the present invention, since the field effect transistor itself self-compensates for the threshold voltage fluctuation with respect to temperature, it is not necessary to provide an external temperature compensating circuit, which increases power consumption and reduces the number of parts. The above effects can be obtained without causing inconveniences such as an increase, a complicated circuit configuration, and a reduction in operating speed.

[Brief description of drawings]

FIG. 1 is a graph showing the relationship between the film stress of an insulating film formed on a field effect transistor and the amount of change in threshold voltage for explaining the operation of the present invention.

FIG. 2 is a graph showing the temperature dependence of the threshold voltage of the original field effect transistor and the temperature dependence of the threshold voltage based on the piezo effect due to the insulating film stress for explaining the operation of the present invention. .

FIG. 3 is a sectional view of a field effect transistor showing an embodiment of the present invention.

FIG. 4 is a graph showing the effect of one embodiment of the present invention.

[Explanation of symbols]

 11 semi-insulating GaAs substrate 12, 14 GaAs layer 13 AlGaAs layer 15 InGaAs layer 16 n-type AlGaAs layer 17 n-type GaAs layer 18 gate electrode 19 ohmic electrode 20 insulating film

Claims (4)

[Claims] 1. A field effect transistor formed on a semiconductor substrate having a piezoelectric property, wherein a film of temperature fluctuation of threshold voltage of the field effect transistor is formed on the field effect transistor. A field effect transistor characterized in that a protective insulating film is formed to compensate for changes in stress with temperature. 2. The protective insulating film is formed of one or more materials selected from silicon nitride oxide, silicon nitride, silicon oxide, and aluminum nitride. The field effect transistor described. 3. The main surface of the semiconductor substrate is a (100) surface, and the drain current of the field-effect transistor is formed so as to flow in a direction parallel to [011]. 2. The field effect transistor according to claim 1, wherein the dependency has a slope having a sign opposite to that of a temperature change of a threshold voltage of the field effect transistor, with the compressive stress being negative and the tensile stress being positive. 4. The main surface of the semiconductor substrate is a (100) surface, and the drain current flowing direction of the field effect transistor is [01-1] ("-1" has an upper line 1). Instead, the temperature dependence of the film stress of the insulating film has the same sign as the temperature change of the threshold voltage of the field-effect transistor, with compressive stress being negative and tensile stress being positive. The field effect transistor according to claim 1, wherein the field effect transistor has a slope of.