JPH07183492A - Two-dimensional electron gas field effect transistor - Google Patents
Two-dimensional electron gas field effect transistorInfo
- Publication number
- JPH07183492A JPH07183492A JP5325241A JP32524193A JPH07183492A JP H07183492 A JPH07183492 A JP H07183492A JP 5325241 A JP5325241 A JP 5325241A JP 32524193 A JP32524193 A JP 32524193A JP H07183492 A JPH07183492 A JP H07183492A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- semiconductor layer
- electrode
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005669 field effect Effects 0.000 title claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 150000001875 compounds Chemical class 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims description 7
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ヘテロ結合を利用した
２次元電子ガスを電流チャネルとして用いる２次元電子
ガス電界効果トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional electron gas field effect transistor using a two-dimensional electron gas utilizing a heterojunction as a current channel.
【０００２】[0002]
【従来の技術】化合物半導体を用いた半導体素子は、一
般にシリコン半導体を用いた素子より高速・高周波域で
動作することが可能であるため、次第にその利用が広が
っている。そして、化合物半導体を利用した代表的な素
子である２次元電子ガス電界効果トランジスタ（以下、
ＨＥＭＴ(High Electoron Mobility Transistor)と称す
る）は、高速動作や高周波領域での利用が可能となるこ
とから期待されている。2. Description of the Related Art In general, a semiconductor device using a compound semiconductor can be operated at a higher speed and a higher frequency than a device using a silicon semiconductor, and therefore its use is gradually expanding. Then, a two-dimensional electron gas field effect transistor (hereinafter referred to as a typical device using a compound semiconductor)
HEMT (High Electoron Mobility Transistor) is expected because it can be used in a high speed operation and a high frequency region.
【０００３】ＨＥＭＴは、シリコン半導体を用いた素子
と比較して、それ自体高速動作するものであるが、より
高速動作させるための工夫が行われている。ＦＥＴを高
速動作させるための最も確実な方法は、ソース、ドレイ
ン間のチャネル長を短くして電子の移動距離を短縮する
ことである。Although the HEMT operates at a higher speed as compared with an element using a silicon semiconductor, HEMT has been devised to operate at a higher speed. The most reliable method for operating the FET at a high speed is to shorten the channel length between the source and drain to shorten the movement distance of electrons.
【０００４】このためには、ソース、ドレイン間に位置
するゲート電極を小さくしなければならない。しかしな
がら、このゲート電極の大きさは、ゲート電極形成のた
めのリソグラフィー技術によって制限され、その限界以
下に小さくすることができない。また、ゲート電極の幅
を小さくするとゲート電極の寄生抵抗が増大して、高周
波動作での損失が大きくなるという問題点もある。For this purpose, the gate electrode located between the source and the drain must be made small. However, the size of the gate electrode is limited by the lithography technique for forming the gate electrode, and cannot be made smaller than the limit. Further, when the width of the gate electrode is reduced, the parasitic resistance of the gate electrode increases, which causes a problem that the loss in high frequency operation increases.
【０００５】[0005]
【発明が解決しようとする課題】そこで、本発明は、化
合物半導体による２ＤＥＧを利用した２次元電子ガス電
界効果トランジスタ（ＨＥＭＴ）において、ゲート電極
の幅に制限されることなく、より高速な動作が可能な２
次元電子ガス電界効果トランジスタを提供することであ
る。SUMMARY OF THE INVENTION Therefore, according to the present invention, a two-dimensional electron gas field effect transistor (HEMT) using a compound semiconductor 2DEG can operate at higher speed without being limited by the width of the gate electrode. Possible 2
A three-dimensional electron gas field effect transistor is provided.
【０００６】[0006]
【課題を解決するための手段】上記目的を解決するため
の本発明は、第１の化合物半導体層と、該第１の化合物
半導体層上に該第１の化合物半導体層と比較して電子供
与物質となる不純物濃度が高い第２の化合物半導体層が
形成され、該第２の化合物半導体層上にソース電極、ド
レイン電極およびゲート電極が設けられた２次元電子ガ
ス電界効果トランジスタにおいて、前記ソース電極およ
び前記ドレイン電極の間の前記第１の化合物半導体層と
前記第２の化合物半導体層の接合界面に段差を有するこ
とを特徴とする２次元電子ガス電界効果トランジスタで
ある。SUMMARY OF THE INVENTION The present invention for solving the above-described object is to provide a first compound semiconductor layer and an electron donating layer on the first compound semiconductor layer as compared with the first compound semiconductor layer. A two-dimensional electron gas field effect transistor in which a second compound semiconductor layer having a high impurity concentration as a substance is formed, and a source electrode, a drain electrode and a gate electrode are provided on the second compound semiconductor layer, And a two-dimensional electron gas field effect transistor having a step at a junction interface between the first compound semiconductor layer and the second compound semiconductor layer between the drain electrode.
【０００７】[0007]
【作用】上述のように構成された本発明は、第１の化合
物半導体層と、該第１の化合物半導体層と比較して不純
物濃度が高く電子供与層となる第２の化合物半導体層と
の界面で２ＤＥＧ層が形成され、この第２の化合物半導
体層上に設けられたソース、ドレイン間の第１の化合物
半導体層と第２の化合物半導体層との界面、すなわち２
ＤＥＧ層に段差を設けたことにより、従来（段差のない
場合）は図４に示すように、２ＤＥＧ層にそってポテン
シャル（図中の曲線）が形成され、２ＤＥＧ層のみの電
流密度が高くなって、２ＤＥＧ層部分を電流の流れ（図
中の矢印）とは逆に電子が流れていたものが、２ＤＥＧ
層内に段差を形成したことによって、図２に示すよう
に、段差のところでポテンシャル（図中の曲線）の分布
が変化し、段差から高くなった方では、２ＤＥＧ層のみ
ならず第２の化合物半導体層内にも電流密度が分布して
この部分の電流の流れ（図中の矢印）とは逆に、電子が
流れるようになる。According to the present invention constructed as described above, the first compound semiconductor layer and the second compound semiconductor layer which has a higher impurity concentration than the first compound semiconductor layer and serves as an electron donating layer. A 2DEG layer is formed at the interface, and the interface between the first compound semiconductor layer and the second compound semiconductor layer between the source and the drain provided on the second compound semiconductor layer, that is, 2
By providing a step in the DEG layer, in the conventional case (when there is no step), a potential (curve in the figure) is formed along the 2DEG layer as shown in FIG. 4, and the current density of only the 2DEG layer becomes high. In the 2DEG layer part, electrons flow opposite to the current flow (arrow in the figure).
By forming the step in the layer, as shown in FIG. 2, the distribution of the potential (curve in the figure) changes at the step, and when the step becomes higher than the step, not only the 2DEG layer but also the second compound The current density is also distributed in the semiconductor layer, and electrons flow in the opposite direction to the current flow (arrows in the figure) in this portion.
【０００８】ＨＥＭＴにおいては、ソースおよびドレイ
ン電極近傍の不純物濃度が高い第２の化合物半導体層内
を流れる電子は、ゲート電極によってその流れを制御さ
れにくく、チャネルとして働く部分は、２ＤＥＧ層内の
みである。このため、段差があることにより、チャネル
として働く部分は、段差の低い方の部分のみとなり、実
質的なチャネル長が短くなる。In the HEMT, the electrons flowing in the second compound semiconductor layer having a high impurity concentration in the vicinity of the source and drain electrodes are difficult to be controlled by the gate electrode, and the portion acting as the channel is only in the 2DEG layer. is there. For this reason, since there is a step, the portion that acts as a channel is only the lower step portion, and the substantial channel length is shortened.
【０００９】[0009]
【実施例】以下、添付した図面を参照して、本発明の一
実施例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.
【００１０】図１は、本実施例のＤ型（デプレッション
型）ＨＥＭＴの断面図である。このＤ型ＨＥＭＴは、第
１の化合物半導体層である基板そのもの、もしくは基板
上にエピタキシャル成長させた不純物濃度５×１０14ｃ
ｍ-3のｉ−ＧａＡｓ層１０上に、第２の化合物半導体層
である不純物濃度８×１０17ｃｍ-3、厚さ５０ｎｍのｎ
−ＡｌＧａＡｓ層１１が積層されており、ｎ−ＡｌＧａ
Ａｓ層１１の上に、ＡｕＧｅ／Ｎｉ（金とゲルマニウム
とニッケルの合金）製のソース電極１２およびドレイン
電極１３と、Ａｌ製のゲート電極１４が設けられ、さら
に、ソース電極１２およびドレイン電極１３の間に位置
するｉ−ＧａＡｓ層１０とｎ−ＡｌＧａＡｓ層１１の接
合界面に、約１０ｎｍの段差が設けられている。FIG. 1 is a sectional view of a D-type (depletion type) HEMT of this embodiment. This D-type HEMT has a substrate itself, which is the first compound semiconductor layer, or an impurity concentration of 5 × 10 14 c which is epitaxially grown on the substrate.
A second compound semiconductor layer having an impurity concentration of 8 × 10 17 cm −3 and a thickness of 50 nm is formed on the m −3 i-GaAs layer 10.
-AlGaAs layer 11 is laminated, and n-AlGa
A source electrode 12 and a drain electrode 13 made of AuGe / Ni (an alloy of gold, germanium, and nickel) and a gate electrode 14 made of Al are provided on the As layer 11, and the source electrode 12 and the drain electrode 13 are further provided. A step difference of about 10 nm is provided at the junction interface between the i-GaAs layer 10 and the n-AlGaAs layer 11 located between them.
【００１１】これにより、ｎ−ＡｌＧａＡｓ層１１が電
子供与層となって、このｉ−ＧａＡｓ層１０とｎ−Ａｌ
ＧａＡｓ層１１の接合界面に、段差のある２ＤＥＧ層２
０が形成される。As a result, the n-AlGaAs layer 11 becomes an electron donating layer, and the i-GaAs layer 10 and the n-Al layer are formed.
A 2DEG layer 2 having a step at the junction interface of the GaAs layer 11
0 is formed.
【００１２】図２は、本実施例によるＤ型ＨＥＭＴのド
レインに２Ｖの電圧を印加したとき（ソースおよびゲー
トは０Ｖである）の２ＤＥＧ層付近のポテンシャルの状
態と電流の向きおよび電流密度を示す図面である。この
図において、上から下に至る曲線がポテンシャルの等高
線を示すもので、矢印が電流の向きを示し、矢印の大き
さが電流密度を示す（矢印が太いほど電流密度が高
い）。FIG. 2 shows the state of the potential near the 2DEG layer, the direction of the current, and the current density when a voltage of 2 V is applied to the drain of the D-type HEMT according to this embodiment (the source and the gate are 0 V). It is a drawing. In this figure, the curve from the top to the bottom shows the contour lines of the potential, the arrow shows the direction of the current, and the size of the arrow shows the current density (the thicker the arrow, the higher the current density).
【００１３】この図から明らかなように、ポテンシャル
は段差部分で乱れ、そこを流れる電流が段差の高い方で
は、２ＤＥＧ層以外に電子供与層であるｎ−ＡｌＧａＡ
ｓ層１１内にも流れるようになり、一方、段差の低い方
では、ドレイン電極下近傍を除くと２ＤＥＧ層内のみに
電流が流れることがわかる。As is clear from this figure, the potential is disturbed at the step portion, and the current flowing therethrough has a high step portion. In addition to the 2DEG layer, the electron donating layer n-AlGaA is also present.
It can be seen that the current also flows in the s-layer 11, and on the other hand, in the one with a lower step, the current flows only in the 2DEG layer except in the vicinity under the drain electrode.
【００１４】ＨＥＭＴにおいては、前記作用中でも述べ
たように、ゲート電極に電圧を印加することにより制御
できるのは、２ＤＥＧ層内を流れる電流（電流とは逆向
きの電子の流れ）のみで、ゲートおよびソース電極近傍
の不純物濃度が高い第２の化合物半導体層内を流れる電
流は制御することができず、結果的にチャネルとして働
く部分は、２ＤＥＧ層内のみである。このため、段差が
あることによりチャネルとして働く部分は、段差の低い
方の部分のみとなって、実質的なチャネル長が短くな
り、その動作が速くなる。たとえばソース電極とドレイ
ン電極のほぼ中間地点に段差を形成した場合には、その
チャネル長は、段差のない場合（従来）のソース・ドレ
イン間距離の約半分となって、その動作速度は、遮断周
波数ｆＴで比較して約１．８倍向上する。In the HEMT, as described in the above operation, by applying a voltage to the gate electrode, it is possible to control only the current flowing in the 2DEG layer (the flow of electrons in the opposite direction to the current). The current flowing in the second compound semiconductor layer having a high impurity concentration in the vicinity of the source electrode cannot be controlled, and as a result, the portion acting as a channel is only in the 2DEG layer. Therefore, due to the step, the portion acting as a channel is only the lower step portion, and the substantial channel length is shortened, and the operation becomes faster. For example, if a step is formed at approximately the midpoint between the source electrode and the drain electrode, the channel length will be about half the distance between the source and drain when there is no step (conventional), and the operating speed will be cut off. It is improved by about 1.8 times as compared with the frequency f T.
【００１５】次に、図３は、本実施例によるＤ型ＨＥＭ
Ｔのソースに２Ｖの電圧を印加したとき（ドレインおよ
びゲートは０Ｖである）の２ＤＥＧ層付近のポテンシャ
ルの状態と電流の向きおよび電流密度を示す図面であ
る。この図において、ポテンシャルの状態および電流の
向きならびに電流密度は、前記図２と同様に表示されて
いる。Next, FIG. 3 shows a D-type HEM according to this embodiment.
It is a figure which shows the state of the potential of 2DEG layer vicinity, the direction of current, and current density when a voltage of 2V is applied to the source of T (the drain and the gate are 0V). In this figure, the state of the potential, the direction of the current, and the current density are displayed as in FIG.
【００１６】この図から明らかなように、ソース側に電
圧を印加したときもポテンシャルは、段差部分で乱れ、
そこを流れる電流が段差の高い方では、２ＤＥＧ層以外
にｎ−ＡｌＧａＡｓ層１１内にも流れるようになり、一
方、段差の低い方では、ドレイン電極下近傍を除くと２
ＤＥＧ層内のみに電流が流れることがわかる。As is apparent from this figure, the potential is disturbed at the step portion even when a voltage is applied to the source side,
The current flowing therethrough has a higher step, and therefore flows into the n-AlGaAs layer 11 as well as the 2DEG layer. On the other hand, the lower step has a current of 2 except the area under the drain electrode.
It can be seen that the current flows only in the DEG layer.
【００１７】これにより前記ドレインに電圧を印加した
ときと同様に、段差があることによりチャネルとして働
く部分は、段差の低い方の部分のみとなって、実質的な
チャネル長が短くなるので、その動作が速くなる。これ
は前記同様に、たとえばソース電極とドレイン電極のほ
ぼ中間地点に段差を形成した場合には、そのチャネル長
は、段差のない場合（従来）のソース・ドレイン間距離
の約半分となって、その動作速度は、遮断周波数ｆＴで
比較して約１．８倍向上する。As a result, similarly to the case where a voltage is applied to the drain, the portion that acts as a channel due to the step difference is only the lower step portion, and the substantial channel length is shortened. It works faster. This is similar to the above, for example, when a step is formed at approximately the midpoint between the source electrode and the drain electrode, the channel length becomes about half the distance between the source and drain when there is no step (conventional), Its operating speed is improved by about 1.8 times compared with the cutoff frequency f T.
【００１８】ここで、本実施例と従来の段差のないＨＥ
ＭＴを比較するために、従来の段差のないＨＥＭＴの２
ＤＥＧ層付近のポテンシャルの状態と電流の向きおよび
電流密度を図４に示す。なお、印加した電圧はドレイン
に２Ｖ（ソースおよびゲートは０Ｖ）であり、この図に
おいて、ポテンシャルの状態および電流の向きならびに
電流密度は、前記図２と同様に表示されている。Here, HE having no step difference between the present embodiment and the conventional HE
In order to compare MT, the conventional HEMT without step 2
FIG. 4 shows the state of the potential near the DEG layer, the direction of the current, and the current density. The applied voltage is 2 V at the drain (0 V at the source and the gate), and in this figure, the state of the potential, the direction of the current, and the current density are displayed as in FIG.
【００１９】この図からわかるように、段差のない場合
には、ポテンシャルは２ＤＥＧ層にそって形成されてお
り、流れる電流は、ドレイン電極からソース電極に至る
部分全てに渡って２ＤＥＧ層内のみである。すなわち、
チャネル長としては、ソースドレイン間の長さとなる。As can be seen from this figure, when there is no step, the potential is formed along the 2DEG layer, and the flowing current is only in the 2DEG layer over the entire portion from the drain electrode to the source electrode. is there. That is,
The channel length is the length between the source and drain.
【００２０】以上説明した本実施例において、２ＤＥＧ
層内に段差を形成するには、たとえば、第１の化合物半
導体層であるｉ−ＧａＡｓ層１０に、まず、フォトリソ
グラフィーおよびエッチングによって、段差から低い方
を形成し、その上に、第２の化合物半導体層であるｎ−
ＡｌＧａＡｓ層１１をエピタキシャル成長させることに
よって、その界面、すなわち２ＤＥＧ層に、段差が形成
される。In this embodiment described above, 2DEG
To form a step in the layer, for example, the i-GaAs layer 10 that is the first compound semiconductor layer is first formed by photolithography and etching to form a lower portion from the step, and then the second step is formed. N- which is a compound semiconductor layer
By epitaxially growing the AlGaAs layer 11, a step is formed at the interface, that is, the 2DEG layer.
【００２１】なお、本実施例は、あくまでも本発明を適
応した一実施例であり、Ｄ型のものであるが、Ｅ型（エ
ンハンスメント型）のものについても同様に実施するこ
とが可能であり、また、その大きさや各層の厚さおよび
段差の程度に付いては、これに限定されるものではな
く、そのＨＥＭＴとして必要な特性により適宜調整され
得るものでり、たとえば段差の程度については、１０〜
５０ｎｍ程度とすることが可能で、下限１０ｎｍは、現
在のエッチングによる段差形成の程度によるものであ
り、一方、上限５０ｎｍを越えると、エピタキシャル成
長時に結晶欠陥が増大するために、これ以上大きな段差
をとることは好ましくないためである。Although the present embodiment is merely an embodiment to which the present invention is applied and is of D type, it can be similarly applied to E type (enhancement type). Further, the size, the thickness of each layer, and the degree of the step are not limited to this, and can be appropriately adjusted depending on the characteristics required for the HEMT. For example, the degree of the step is 10 ~
The lower limit of 10 nm is due to the degree of step formation by the current etching. On the other hand, when the upper limit of 50 nm is exceeded, crystal defects increase during epitaxial growth, and thus a larger step is taken. This is not preferable.
【００２２】[0022]
【発明の効果】以上説明したように、本発明の２ＤＥＧ
を利用した電界効果トランジスタ（ＨＥＭＴ）は、リソ
グラフィー技術による限界の最小線幅に律則されずに、
実効的なチャネル長を短くすることができ、素子の動作
をより高速化することができる。また、この高速化に伴
なう寄生抵抗の増大も起きない。As described above, the 2DEG of the present invention
The field effect transistor (HEMT) utilizing the is not restricted by the minimum line width of the lithography technology,
The effective channel length can be shortened, and the operation speed of the device can be further increased. In addition, the parasitic resistance does not increase as the speed increases.
【図１】 本発明による一実施例のＨＥＭＴの断面図で
ある。FIG. 1 is a cross-sectional view of an HEMT according to an embodiment of the present invention.
【図２】 この実施例においてドレインに２Ｖ印加した
ときの２ＤＥＧ層付近のポテンシャルの状態、電流の流
れを説明するための図面である。FIG. 2 is a diagram for explaining a potential state and a current flow near a 2DEG layer when 2 V is applied to the drain in this example.
【図３】 この実施例においてソースに２Ｖ印加したと
きの２ＤＥＧ層付近のポテンシャルの状態、電流の流れ
を説明するための図面である。FIG. 3 is a drawing for explaining a potential state and a current flow near the 2DEG layer when 2 V is applied to the source in this example.
【図４】 従来のＨＥＭＴにおいてドレインに２Ｖ印加
したときの２ＤＥＧ層付近のポテンシャルの状態、電流
の流れを説明するための図面である。FIG. 4 is a diagram for explaining a potential state and a current flow near a 2DEG layer when 2 V is applied to a drain in a conventional HEMT.
【符号の説明】 １０…ｉ−ＧａＡｓ層、 １１…ｎ−
ＡｌＧａＡｓ層、１２…ソース電極、
１３…ドレイン電極、１４…ゲート電極、
２０…２ＤＥＧ層。[Explanation of Codes] 10 ... i-GaAs layer, 11 ... n-
AlGaAs layer, 12 ... Source electrode,
13 ... Drain electrode, 14 ... Gate electrode,
20 ... 2 DEG layers.
Claims (1)
物半導体層上に該第１の化合物半導体層と比較して電子
供与物質となる不純物濃度が高い第２の化合物半導体層
が形成され、該第２の化合物半導体層上にソース電極、
ドレイン電極およびゲート電極が設けられた２次元電子
ガス電界効果トランジスタにおいて、 前記ソース電極および前記ドレイン電極の間の前記第１
の化合物半導体層と前記第２の化合物半導体層の接合界
面に段差を有することを特徴とする２次元電子ガス電界
効果トランジスタ。1. A first compound semiconductor layer, and a second compound semiconductor layer having a higher concentration of impurities serving as an electron donor than the first compound semiconductor layer as compared to the first compound semiconductor layer are formed. A source electrode on the second compound semiconductor layer,
A two-dimensional electron gas field effect transistor provided with a drain electrode and a gate electrode, wherein the first electrode between the source electrode and the drain electrode is provided.
A two-dimensional electron gas field effect transistor having a step at a junction interface between the compound semiconductor layer and the second compound semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5325241A JPH07183492A (en) | 1993-12-22 | 1993-12-22 | Two-dimensional electron gas field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5325241A JPH07183492A (en) | 1993-12-22 | 1993-12-22 | Two-dimensional electron gas field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07183492A true JPH07183492A (en) | 1995-07-21 |
Family
ID=18174610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5325241A Withdrawn JPH07183492A (en) | 1993-12-22 | 1993-12-22 | Two-dimensional electron gas field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07183492A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008210836A (en) * | 2007-02-23 | 2008-09-11 | Sanken Electric Co Ltd | Field effect semiconductor device and its fabrication process |
| US9685549B2 (en) | 2011-07-12 | 2017-06-20 | Panasonic Intellectual Property Management Co., Ltd. | Nitride semiconductor device and method for manufacturing same |
-
1993
- 1993-12-22 JP JP5325241A patent/JPH07183492A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008210836A (en) * | 2007-02-23 | 2008-09-11 | Sanken Electric Co Ltd | Field effect semiconductor device and its fabrication process |
| US9685549B2 (en) | 2011-07-12 | 2017-06-20 | Panasonic Intellectual Property Management Co., Ltd. | Nitride semiconductor device and method for manufacturing same |
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