JPH08222578A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE: To avoid the drop of withstand voltage caused by the accumulation of positive holes, by introducing a p-type impurity semiconductor layer under an n-type conductive channel, and providing a p-type impurity semiconductor layer in high concentration in contact with this p-type impurity semiconductor layer, and further, providing an ohmic electrode in contact with this. CONSTITUTION: An undoped InAlAs layer 2, a p-type doped InAlAs layer 3, an undoped InAlAs layer 4, an undoped InGaAs layer 5, an undoped InAlAs layer 6, a p-type doped InAlAs layer 7, an undoped InAlAs layer 8, an n-type doped InAlAs layer 9, and an n-type doped InGaAs layer 10 are stacked in order on a semiinsulating substrate 1 so as to make a semiconductor multilayer structure. A p-type dope region 14 in high concentration doped with p-type impurities in high concentration of about 1×10<20> cm<-3> is made by Zn diffusion or the like in such thickness that it reaches the InAlAs layer 3, piercing each layer 4-10 from the surface, at one part of this semiconductor multilayer structure, and further an ohmic electrode 15 is made on this p-type dope region 14 in high concentration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor made of a compound semiconductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing an example of the structure of a conventional field effect transistor made of a compound semiconductor.
In FIG. 9, this field-effect transistor has an undoped InAlAs layer 82 with a thickness of 2000 Å, an undoped InGaAs layer 83 with a thickness of 150 Å, and an undoped film with a thickness of 150 Å on a semi-insulating semiconductor substrate 81 formed of InP. Two
0Å InAlAs layer 84 and Si of 1 × 10 ¹⁹ cm ⁻³
InAlAs layer 85 with a film thickness of 50 Å made into n-type by doping
And an undoped InAlAs layer 86 with a film thickness of 150Å
And an InAlAs layer 87 having a film thickness of 150 Å made into n-type by doping 1 × 10 ¹⁹ cm ^{−3 of} Si, and 1 × 10 ¹⁹ c of Si.
InGaAs with a film thickness of 150 Å that was n-type doped with m ^-3
The layers 88 are sequentially stacked to form a semiconductor multilayer structure.

Further, in this semiconductor multilayer structure, a part of the semiconductor multilayer structure is at least InAlAs from the surface.
The window-shaped gate region 9 is removed to a depth reaching the layer 86.
3 is formed, and a gate Schottky electrode (hereinafter referred to as a gate electrode) 89 is formed on the bottom surface of the gate region 93.
And a source ohmic electrode (hereinafter, referred to as source electrode) 90 and a drain ohmic electrode (hereinafter, referred to as drain electrode) 91 are formed on both sides of the InGaAs layer 88 with the gate electrode 89 interposed therebetween. .

In order to operate the field effect transistor having such a structure, the voltage applied to the gate electrode 89 is changed to change the concentration of electrons immediately below the gate electrode 89, so that the source electrode 90 changes to the drain electrode. The flow rate of electrons flowing to 91, that is, the drain current is changed.

[0005]

However, the field effect transistor having such a structure has the following problems. (1) When the drain voltage is increased, a phenomenon called so-called kink occurs in which the drain current rapidly increases near a certain voltage. FIG. 10 is a cross-sectional view of a field effect transistor for explaining the kink manifestation mechanism. First, as shown in FIG. 10A, a depletion layer 95 spreads on the surface of the undoped InAlAs layer 86 below the gate region 93, and the thickness of the depletion layer 95 can be changed by the voltage of the gate electrode 89.

Here, the source electrode 9 is formed on the drain electrode 91.
When a positive voltage (hereinafter referred to as a drain voltage) with respect to 0 is applied, electrons are emitted from the source electrode 90 side to the drain electrode 9
However, since the n-type doped InGaAs layer 88 and the n-type doped InAlAs layer 87 are removed under the gate region 93, the channel resistance 97 is formed immediately below the gate. Areas 92 on both sides
A source resistor 96 and a drain resistor 98 are located immediately below the source resistor 96 to limit the flow of electrons.

Here, as the drain voltage is increased, the accelerated electron 99 has a high energy as shown in FIG. 10B, and the undoped InGaA
Collide with the valence electrons of semiconductor atoms in the s layer 83 to cause free electrons 1
00 and hole 101 are generated. The free electrons 100 generated in this way are transferred to the drain electrode 9
1 goes out of the transistor, but the holes 101 are undoped InGa because the surroundings are n-type or semi-insulating.
It remains in the As layer 83, particularly on the source electrode side below the gate electrode, and eventually recombines with electrons and disappears.

However, when the drain voltage is further increased, the frequency of generation of electron-hole pairs exceeds the frequency of recombination and disappearance of holes with electrons, and as shown in FIG. 10C, undoped InGaAs. Accumulation of holes 101 occurs in layer 83. When the holes 101 are accumulated in this manner, the number of electrons in the channel increases due to the decrease in the electrostatic potential of the channel, the source resistance 96 decreases, and the threshold voltage also decreases. A kink occurs.

(2) When a kink occurs, the drain breakdown voltage decreases. This is due to the accumulation of holes described in (1) above.
The drain current increases, but as a result, the number of holes generated by impact ionization increases, and the accumulation of holes is further accelerated. By repeating this, the drain current increases rapidly,
It destroys the field effect transistor.

Therefore, the present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is a field effect transistor capable of avoiding a kink and a decrease in breakdown voltage due to accumulation of holes, and a method of manufacturing the same. To provide.

[0011]

In order to achieve such an object, a field effect transistor according to the present invention includes a p-type impurity semiconductor layer between a semi-insulating substrate and an n-type conductive channel, and a compound semiconductor. A high-concentration p-type impurity semiconductor region is provided in a part of the layer in contact with the p-type impurity semiconductor layer, and an ohmic electrode in contact with the high-concentration p-type impurity semiconductor region is provided.

Further, in the method for manufacturing a field effect transistor according to the present invention, a step of forming a compound semiconductor layer having an n-type conductive channel layer on a semi-insulating substrate and a refractory metal thin film formed on the entire surface of the compound semiconductor layer. And a step of etching a region of the refractory metal thin film to be a high-concentration p-type impurity region, and a high-concentration p-type impurity is introduced into the compound semiconductor layer by using the refractory metal thin film as a mask. A step of forming a region, a step of processing the refractory metal thin film into an electrode pattern of a source electrode and a drain electrode,
And forming a ohmic electrode, a source electrode, a drain electrode, and a gate electrode on the high-concentration p-type impurity region, the source electrode pattern, the drain electrode pattern, and the n-type conductive channel layer, respectively.

[0013]

In the present invention, the p-type impurity semiconductor layer is introduced under the n-type conductive channel, and the high-concentration p-type impurity semiconductor region is provided in contact with the p-type impurity semiconductor layer. By providing an ohmic electrode in contact with the semi-insulating substrate, holes generated in the n-type conductive channel layer are extracted to the semi-insulating substrate side, and the high-concentration p-type impurity semiconductor region is passed through the ohmic electrode to the outside of the semi-insulating substrate. To take out efficiently.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a structure according to an embodiment of a field effect transistor according to the present invention. FIG. 1 (a) is a plan view seen from above, and FIG. 1 (b) is FIG. ) A-
It is sectional drawing of the A'line. In FIG. 1, a semi-insulating substrate 1
On top, an undoped InAlAs layer 2, p-type doped In
AlAs layer 3, undoped InAlAs layer 4, undoped InGaAs layer 5, undoped InAlAs layer 6, n
Type-doped InAlAs layer 7, undoped InAlAs layer 8, n-type doped InAlAs layer 9 and n-type doped In
A semiconductor multilayer structure is formed by sequentially stacking the GaAs layers 10.

Further, on the semiconductor multilayer structure, a part of the semiconductor multilayer structure is at least InAlA from the surface.
A window-shaped gate region is formed by removing to a depth reaching the s layer 8, and a gate Schottky electrode (hereinafter referred to as a gate electrode) 11 is formed on the bottom surface of this gate region. Furthermore, the gate electrode 1 on the InGaAs layer 10
A source ohmic electrode (hereinafter, referred to as a source electrode) 12 and a drain ohmic electrode (hereinafter, referred to as a drain electrode) 13 are formed at positions on both sides sandwiching 1. In addition, a part of this semiconductor multilayer structure penetrates each of these layers 4 to 10 from the surface and reaches a depth of reaching the InAlAs layer 3 by a high concentration of about 1 × 10 ²⁰ cm ⁻³ of p-type impurities due to Zn diffusion or the like. Heavily doped p-type doped region 1
4 is formed, and an ohmic electrode 15 is formed on the high concentration p-type doped region 14.

In order to operate the field effect transistor having the above-described structure, the voltage applied to the gate electrode 11 is changed to change the electron concentration immediately below the gate electrode 11, and the source electrode 12 to the drain electrode 13 are changed. Changes the drain current flowing to. At the same time, the ohmic electrode 15 connected to the high-concentration p-type doped region 14 can be grounded, and the accumulated holes can be emitted to the outside of the field effect transistor.

According to this structure, p-type doped In
By providing the AlAs layer 3, as shown in FIG. 2, the electrostatic potential A for electrons is larger on the semi-insulating substrate 1 side and smaller on the gate electrode 11 side than the electrostatic potential B in the conventional configuration. As a result, the holes 101 accumulated in the undoped InGaAs layer 5 where the conductive channel exists move to the p-type doped InAlAs layer 3 having a lower potential for holes. Further, the ohmic electrode 1 in contact with the high-concentration p-type doped region 14
P-doped InA by applying a negative voltage to
The holes transferred into the 1As layer 3 are highly concentrated p-type doped regions 1
It is possible to prevent the accumulation of holes by being discharged from the ohmic electrode 15 to the outside of the field effect transistor through the electrode 4.
Therefore, it is possible to suppress kinks and prevent a decrease in withstand voltage.

FIG. 3 is a diagram showing the drain current-drain voltage characteristics of the field effect transistor thus constructed. As shown by the dotted line in the figure, even with a threshold value in which a kink occurs in the drain current-drain voltage characteristic in the past, good characteristics without kink can be obtained as shown by the solid line in the figure. Further, it is possible to obtain a higher breakdown voltage than the conventional field effect transistor.

FIGS. 4 and 5 are views including a cross section and a partial plane in each step for explaining the embodiment of the method for manufacturing the field effect transistor described in FIG. In these figures, first, as shown in FIG. 4A, a semiconductor multilayer structure 32 is formed on a semi-insulating substrate 31, and then, for example, WS is used.
A refractory metal thin film 33 such as iN is deposited. here,
As shown in FIG. 1, the semiconductor multi-layer structure 32 is an undoped InAlAs layer 2 having a film thickness of 2000 Å 2 and a Be layer of 1 × 10.
¹⁸ cm ^-3 doped p-type InAl with a thickness of 100 Å
As layer 3, undoped InAlAs layer with a thickness of 50Å 4, undoped InGaAs layer with a thickness of 150Å 5, undoped InAlAs layer 6 with a thickness of 20Å Si 1 ×
InA with a film thickness of 50 Å to be n-type doped with 10 ¹⁹ cm ^-3
lAs layer 7, undoped InAlAs with a thickness of 150Å
The layer 8, the InAlAs layer 9 having a film thickness of 150 Å made into n-type by doping 1 × 10 ¹⁹ cm ^{−3 of} Si and 1 × 10 ^{19 of} Si
cm ^-3 doped n-type InGaA with a film thickness of 150Å
The s layer 10 is formed by laminating in that order by, for example, the MBE method.

Next, as shown in FIG. 4B, the refractory metal thin film 33 deposited on the semiconductor multilayer structure 32 is formed on the portion corresponding to the high-concentration p-type doped region 14 by, for example, the reactive ion etching method. The window 34 is opened. Next in FIG.
As shown in (c), the refractory metal thin film 33 having the window 34 formed therein is used as a mask, for example, about 1 × by Zn diffusion or the like.
A high-concentration p-type impurity of 10 ²⁰ cm ⁻³ is doped to form a high-concentration p-type doped region 35. Next, as shown in FIG. 4 (d), the refractory metal thin film 33 is removed by reactive ion etching or the like except a necessary portion, and the source electrode pattern 33S and the drain electrode pattern 33D are removed.
To form. Next, as shown in a sectional view of FIG. 4E and a plan view of FIG. 4F, element isolation is performed by, for example, wet etching.

Next, as shown in FIG. 4G, for example, Ti / is formed on the semi-insulating substrate 31 on which the semiconductor multilayer structure 32 is formed.
Not shown by contacting the source electrode pattern 33S and the drain electrode pattern 33D with a high electron conductive metal such as Pt / Au by vapor deposition or the like and contacting the source electrode 36, the drain electrode 37 and the high concentration p-type doped region 35, respectively. Form an ohmic electrode. Next, a gate electrode 39 is formed between the source electrode pattern 33S and the drain electrode pattern 33D as shown in the sectional view of FIG. 4H and the plan view of FIG. At this time, a part of the semiconductor multi-layer structure 32 is at least In from the surface from the surface.
A window-shaped gate region is formed by removing to a depth reaching the AlAs layer 8, and a gate electrode 39 is formed on the bottom surface of the gate region by using, for example, a high electron conductive metal such as Ti / Pt / Au. It is formed by In addition,
In FIG. 4 (i), 38 indicates an ohmic electrode in contact with the high concentration p-type doped region 35 formed in the previous step (shown in FIG. 4 (g)).

(Embodiment 2) FIGS. 5A and 5B are views showing the structure of a field effect transistor according to another embodiment of the present invention. FIG. 5A is a plan view seen from above, and FIG. FIG. 6 is a cross-sectional view taken along the line AA ′ of FIG. 5A, the same parts as those in FIG. 5 is different from FIG. 1 in that the high-concentration p-type doped region 14 is formed and electrically connected under the source electrode 12 without separately providing an electrode in contact with the high-concentration p-type doped region 14. ing. According to such a configuration, holes can be easily recombined with the electrons supplied from the source electrode 12, and a hole extraction effect can be expected.

6A to 6C are cross-sectional views in each step showing a method of manufacturing the field effect transistor shown in FIG. Since the manufacturing process shown in these figures is almost the same as the manufacturing method of FIG. 4 described above, the description thereof will be omitted.

(Third Embodiment) In the second embodiment described above, the case where the high-concentration p-type doped region 14 is provided only under the source electrode 12 has been described.
It may be provided only under 3, or under both the source electrode 12 and the drain electrode 13. here,
When the high-concentration p-type doped region 14 is provided only under the drain electrode 13, holes are injected contrary to the second embodiment, so that holes are always accumulated in the channel. Therefore, although improvement in withstand voltage cannot be expected, generation of kinks can be suppressed.

Further, when the high-concentration p-type doped region 14 is provided both below the source electrode 12 and below the drain electrode 13, there is an intermediate effect between the both. That is, it is possible to expect suppression of kinks and some improvement in breakdown voltage, and a source / drain symmetric structure is obtained, which is advantageous in designing an integrated circuit pattern.

In order to operate the field effect transistor having such a structure, the voltage applied to the gate electrode 11 is changed to change the concentration of electrons just below the gate electrode 11, and the source electrode 12 to the drain electrode 13 are changed. Changes the drain current flowing to. The accumulated holes can be released from the p-type doped InAlAs layer 3 through the high-concentration p-type doped region 14 to the outside of the field effect transistor by diffusion.

(Embodiment 4) In the fourth embodiment of the present invention, the InAlAs layer 3 having a film thickness of 100 Å which is made into p-type by doping Be with 1 × 10 ¹⁸ cm ^-3 in FIG. Is a field effect transistor having a structure in which the InAlAs layer 4 is removed. According to such a configuration,
Although the effect of releasing the accumulated holes is slightly reduced as compared with the third embodiment, the high concentration p-type doped region 14 can suppress the hole accumulation.

(Fifth Embodiment) In the fifth embodiment of the present invention, the InAlAs layer 3 having a film thickness of 100 Å which is made into p-type by doping Be with 1 × 10 ¹⁸ cm ^-3 in FIG. Is a field effect transistor having a structure in which the InAlAs layer 4 is removed. According to such a configuration,
Although the effect of releasing the accumulated holes is slightly lower than that in the second embodiment, the high concentration p-type doped region 14 can suppress the hole accumulation.

(Embodiment 6) FIG. 7 is a sectional view showing the structure of a field effect transistor according to another embodiment of the present invention. In FIG. 7, 41 is a semi-insulating substrate such as GaAs, 42 is a p-type doped layer doped with Be at 1 × 10 ¹⁷ cm ⁻³ , and 43 is Si at 1 × 10 ¹⁸ cm ^{−3, for example.}
It is a doped n-type conductive channel, and this n-type conductive channel 43 is in contact with the gate electrode 45. Further, 44 is an n ⁺ layer doped with Si at 5 × 10 ¹⁸ cm ⁻³ , and the n ⁺ layer 44 is in contact with the source electrode 46 and the drain electrode 47. Further, under the source electrode 46, for example, Zn
^Heavily doped p-type region 4 doped with 1 × 10 ²⁰ cm ⁻³
8 is formed to a depth reaching the p-type doped layer 42.

FIG. 8 is a cross-sectional view in each step for explaining the method of manufacturing the field effect transistor shown in FIG. In these figures, first, as shown in FIG. 8A, p is formed on the surface of the semi-insulating substrate 51 by, for example, ion implantation.
A p-type doped layer 52 is formed by doping a type impurity. Next, as shown in FIG. 8B, n-type impurities are doped on the p-type doped layer 52 by, for example, ion implantation to form an n-type conductive channel 53. Next, as shown in FIG. 8C, a refractory metal thin film 54 such as WSiN is formed on the n-type conductive channel 53. Next, as shown in FIG. 8D, an opening 55 is formed in the high melting point metal thin film 54 at a portion corresponding to the high-concentration p-type doped region 48 by, for example, reactive ion etching.

Next, as shown in FIG.
Using the refractory metal thin film 54 formed with
Dope a high-concentration p-type impurity by diffusion of n, etc.,
A high-concentration p-type doped region 56 is formed. Then, unnecessary portions of the refractory metal thin film 54 are removed by, for example, reactive ion etching to form a gate electrode 57 as shown in FIG. Then the n-type impurity doped due to an ion implantation as shown in FIG. 8 (g), to form an n ⁺ layer 58 by heat treating further at about 800 ° C.. Next, as shown in FIG.
Source electrode 59 using, for example, vapor deposition using
And the drain electrode 60 is formed.

In order to operate the field effect transistor thus constructed, the gate electrode 45 is changed by changing the voltage applied to the gate electrode 45 in FIG.
The concentration of electrons immediately below is changed to change the drain current flowing from the source electrode 46 to the drain electrode 47. The accumulated holes diffuse the p-type doped layer 42.
Can be emitted to the outside of the field effect transistor through the heavily-doped p-type doped region 48.

(Embodiment 7) A seventh embodiment of the present invention is a field effect transistor having a structure in which the p-type doped layer 42 is removed from the structure of the embodiment 6 (FIG. 7). With this structure, the effect of releasing the accumulated holes is slightly lower than that of the sixth embodiment, but the high-concentration p-type doped region 4 is used.
By 8, the accumulation of holes can be suppressed.

[0034]

As described above, according to the field effect transistor of the present invention, it is possible to obtain good characteristics without a kink even at the threshold value in which a kink occurs in the drain current-drain voltage characteristics. Further, a field effect transistor having a higher breakdown voltage than that of the conventional field effect transistor can be obtained. Therefore, it can be applied to various high-speed, high-frequency, low-noise integrated circuits.

[Brief description of drawings]

FIG. 1A is a plan view illustrating a configuration of an embodiment of a field effect transistor according to the present invention, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 2 is a diagram showing a band structure of a field effect transistor according to the present invention.

FIG. 3 is a diagram showing drain current-drain voltage characteristics of the field effect transistor according to the present invention.

FIG. 4 is a cross-sectional view for explaining one embodiment of the method for manufacturing the field effect transistor shown in FIG.

5A is a plan view for explaining the configuration of a field effect transistor according to another embodiment of the present invention, and FIG. 5B is a sectional view taken along line AA ′ in FIG.

6A and 6B are cross-sectional views for explaining one example of a method for manufacturing the field effect transistor shown in FIG.

FIG. 7 is a cross-sectional view illustrating the configuration of another embodiment of the field effect transistor according to the present invention.

FIG. 8 is a cross-sectional view for describing an example of a method for manufacturing the field effect transistor shown in FIG.

FIG. 9 is a cross-sectional view illustrating the configuration of a conventional field effect transistor.

FIG. 10 is a cross-sectional view for explaining a kink occurrence phenomenon in the field effect transistor shown in FIG.

[Explanation of symbols]

1 ... Semi-insulating substrate, 2 ... Undoped InAlAs layer, 3
... p-type doped InAlAs layer, 4 ... undoped InAl
As layer, 5 ... Undoped InGaAs layer, 6 ... Undoped InAlAs layer, 7 ... N-type doped InAlAs layer, 8
... undoped InAlAs layer, 9 ... n-type doped InAl
As layer, 10 ... N-type doped InGaAs layer, 11 ... Gate electrode, 12 ... Source electrode, 13 ... Drain electrode, 14
... High-concentration p-type doped region, 15 ... Ohmic electrode, 31
... Semi-insulating substrate, 32 ... Semiconductor multilayer structure, 33 ... Refractory metal thin film, 33S ... Source electrode pattern, 33D ... Drain electrode pattern, 34 ... Window, 35 ... High concentration p-type doped region, 36 ... Source electrode, 37 ... Drain electrode, 38 ...
Ohmic electrode, 39 ... Gate electrode, 41 ... Semi-insulating substrate, 42 ... P-type doped layer, 43 ... N-type conductive channel, 4
4 ... N ⁺ layer, 45 ... Gate electrode, 46 ... Source electrode, 4
7 ... Drain electrode, 48 ... High concentration p-type doped region, 51
... semi-insulating substrate, 52 ... p-type doped layer, 53 ... n-type conductive channel, 54 ... refractory metal thin film, 55 ... opening, 56 ...
High concentration p-type doped region, 57 ... Gate electrode, 58 ... N ⁺
Layer, 59 ... Source electrode, 60 ... Drain electrode.

Claims (5)

[Claims] 1. A field effect transistor in which a compound semiconductor layer having an n-type conductive channel is formed on a semi-insulating substrate, and a gate electrode, a source electrode, and a drain electrode are provided on the n-type conductive channel, A p-type impurity semiconductor layer is included between the semi-insulating substrate and the n-type conductive channel, and a high-concentration p-type impurity semiconductor region is provided in a part of the compound semiconductor layer in contact with the p-type impurity semiconductor layer. A field effect transistor comprising an ohmic electrode in contact with the high-concentration p-type impurity semiconductor region. 2. A field effect transistor in which a compound semiconductor layer having an n-type conductive channel is formed on a semi-insulating substrate, and a gate electrode, a source electrode and a drain electrode are provided on the n-type conductive channel, A p-type impurity semiconductor layer is included between a semi-insulating substrate and the n-type conductive channel, and the p-type impurity semiconductor layer is formed on a part of the compound semiconductor layer under at least one of the source electrode and the drain electrode. A field-effect transistor having a high-concentration p-type impurity semiconductor region in contact with. 3. A field effect transistor in which a compound semiconductor layer having an n-type conductive channel is formed on a semi-insulating substrate, and a gate electrode, a source electrode and a drain electrode are provided on the n-type conductive channel, A field effect transistor comprising a high concentration p-type impurity semiconductor region in a part of a compound semiconductor layer, and an ohmic electrode in contact with the high concentration p-type impurity semiconductor region. 4. A field effect transistor in which a compound semiconductor layer having an n-type conductive channel is formed on a semi-insulating substrate, and a gate electrode, a source electrode and a drain electrode are provided on the n-type conductive channel, A high-concentration p-type impurity semiconductor region is provided in a part of the compound semiconductor layer below at least one of a source electrode and a drain electrode. 5. A step of forming a compound semiconductor layer having an n-type conductive channel layer on a semi-insulating substrate, a step of forming a refractory metal thin film on the entire surface of the compound semiconductor layer, and a step of forming the refractory metal thin film. Etching a region to be a high-concentration p-type impurity region; forming a high-concentration p-type impurity region by introducing a p-type impurity into the compound semiconductor layer using the refractory metal thin film as a mask; A step of processing a refractory metal thin film into electrode patterns of a source electrode and a drain electrode, and an ohmic electrode, a source electrode, and a source electrode on the high-concentration p-type impurity region, the source electrode pattern, the drain electrode pattern, and the n-type conductive channel layer, respectively. A step of forming a drain electrode and a gate electrode, and a method for manufacturing a field effect transistor.