JPH08213570A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To reduce the area of a MOS transistor which occupies the surface of a semiconductor substrate by forming switching elements and capacitor elements vertically in a groove formed into the substrate so that the current paths of the switching elements are formed at only one side face of the groove. CONSTITUTION: On the surface of a semiconductor substrate is formed an impurity diffused layer 1a of the opposite conductivity to that of the substrate. On the bottom face of a groove region b is formed an impurity diffused layer 1a of the opposite conductivity to that of the substrate. On this layer 1b is formed a first conductive layer 2 through an insulation film. A stepped part between the layers 1a and 2b forms a channel region 5. The conductive layer 2 is used as a gate electrode to form a switching element. The current path of the switching element is formed on only the side face of the groove region b. A second conductive layer 3 is formed inside a groove region c through an insulation film. The side face of the region c and bottom face of the substrate are used as opposed electrodes to form a parallel plate type capacitor element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the structure of a semiconductor memory device including one switching element (MOS transistor) and one capacitance element.

[0002]

2. Description of the Related Art Currently, a dynamic RAM (DRA
One MO is used as a memory cell of a memory device called M).
What is composed of an S transistor and one capacitive element is used.

As a memory cell structure satisfying recent demands for large scale and miniaturization, there has been proposed one in which a capacitor is formed in a groove provided on a semiconductor substrate. As a conventional example, an example thereof is shown in FIG.

FIG. 5 (a) is a plan view showing the parallel arrangement of two memory cells, and FIG. 5 (b) is a sectional view taken along the line AA 'in FIG. 5 (a). The source and drain of the MOS transistor are formed on the surface portion of the semiconductor substrate of the first conductivity type by the impurity diffusion layers 1a and 1c of the opposite conductivity type. A first conductive layer 2 which doubles as the gate electrode of the MOS transistor and the wiring of the word line is formed between the impurity diffusion layers 1a and 1c. A groove 10 is provided adjacent to the impurity diffusion layer 1c, and a second conductive layer 3 which also functions as one electrode of the capacitor and a bit line wiring is formed on the surface of the groove 10 via an oxide film. Reference numeral 5 is a channel region (current path) of the MOS transistor, 6 is a thick insulating layer for separating wirings or elements, and 7 is an impurity diffusion layer of the same conductivity type as the semiconductor substrate for element isolation.

In this conventional example, the capacitive element is shown in FIG.
As shown in (b), the conductive layer 3 inside the groove region d, the oxide film below the conductive layer 3 and the semiconductor substrate are formed as parallel plate capacitors on the side and bottom surfaces of the groove. The area of the element region occupied on the surface of the semiconductor substrate of the capacitive element thus configured is much smaller than that of the case where the capacitive element having the same capacitance value is formed on the surface of the planar semiconductor substrate.

[0006]

In the conventional memory cell described above, only the capacitance element has reduced the area occupied on the surface of the semiconductor substrate. For the MOS transistor, see FIG.
As shown in (b), the length y of the gate channel region 5 is
X / 2 in the impurity diffusion layer 1a which becomes the data input / output portion
(Because the impurity diffusion layer 1a is shared with the MOS transistor of the adjacent memory cell), Z is the impurity diffusion layer 1c connected to one end of the capacitive element, which is (x / 2) + y + z in total.
Is needed. The conventional memory cell structure shown in FIG. 5 has a drawback that the MOS transistor region cannot be reduced due to this length, and there is a limit to the reduction of the area occupied by the memory cell region on the surface of the semiconductor substrate.

[0007]

A semiconductor memory device according to the present invention is a semiconductor memory device in which a switching element and a capacitive element are connected to each other, and the switching element and the capacitive element are perpendicular to a groove provided on a semiconductor substrate. And a current path of the switching element is formed only on one side surface of the groove. Specifically, the groove is composed of a protrusion and a deep groove formed at a predetermined distance in the direction of one side surface of the protrusion, the semiconductor substrate of one conductivity type having the groove, and the surface of the semiconductor substrate. And an insulating layer formed on the surface in the deep groove, a surface of the semiconductor substrate that is the protrusion and a surface of the semiconductor substrate between the protrusion and the deep groove, the first conductivity type opposite to the semiconductor substrate. And the second impurity diffusion layer, the first conductive layer formed on the insulating layer above the second impurity diffusion layer, and the insulating layer in the deep groove so as to fill the deep groove. A second conductive layer, the first
Element, a switching element formed by one side surface of the first and second impurity regions, and the protrusion, and a capacitive element formed by the second conductive layer, an insulating layer on the surface in the deep groove, and the semiconductor substrate. A semiconductor memory device formed by
The current path of the switching element is formed only on one side surface of the protrusion.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. FIG. 1 (a) is a plan view, FIG. 1 (b) is a sectional view taken along the line A--A 'of FIG. Figure (c) shows B in Figure (a).
It is a -B 'sectional view. The semiconductor substrate has a groove region b and a groove region c. An impurity diffusion layer 1a having a conductivity type opposite to that of the semiconductor substrate is provided on the surface of the semiconductor substrate, and an impurity diffusion layer 1b having a conductivity type opposite to that of the semiconductor substrate is also provided at the bottom of the groove region b. A first conductive layer 2 is formed on the impurity diffusion layer 1b via an insulating film, and the first conductive layer 2 is formed of a thin insulating film on both the semiconductor substrate at the step between the impurity diffusion layers 1a and 1b. Through. In the impurity diffusion layers 1a and 1b, the surface of the semiconductor substrate in the step portion between them serves as the channel region 5, and the first conductive layer 2 serves as the gate electrode.
It constitutes an S-transistor. The second conductive layer 3 is formed inside the groove region c via an insulating film, and constitutes a parallel plate type capacitive element using the semiconductor substrate corresponding to the side surface and the bottom surface of the groove region c as the counter electrode. The wiring layer 4 is the second conductive layer 3
The wiring layer 4 ′ is a word line that is wired to the first conductive layer 2 and is a wiring that applies a fixed potential to the first conductive layer 2. Reference numeral 6 is a thick insulating layer for separating elements or wirings, and 7 is an impurity diffusion layer of the same conductivity type as the semiconductor substrate for element separation. a is a region for separating elements (between memory cells). According to such a memory cell structure, the channel area 5 (length y) of the MOS transistor is on the side surface of the groove and is perpendicular to the surface of the semiconductor substrate, so that the area on the plane is not required. Therefore, when viewed from the surface of the semiconductor substrate, the length is x / 2 (because it is shared with the adjacent memory cell) for the impurity diffusion layer 1a which is the input / output portion of data, and it is on the bottom surface of the groove region b. The MOS transistor only needs a total length of (x / z) + z including the length z for the impurity diffusion layer 1b connected to one end of the capacitive element, which is longer than the conventional example. The MOS transistor region is reduced by the y portion.

2A to 2E are views showing the manufacturing method of the first embodiment in the order of steps. First, as shown in FIG. 2A, a photoresist 11 is formed to form an element forming region, and a first groove region a is formed by etching. After that, an impurity diffusion layer 7 having the same conductivity type as the substrate is selectively formed on the bottom surface of the groove region a for element isolation. After removing the photoresist 11, the insulating layer 6 is selectively formed in the groove region a. Next, as shown in FIG. 2B, a photoresist 11 is selectively formed on the insulating layer 6 of the semiconductor substrate,
A groove region b'which is shallower than the groove region a which will be a groove region b for forming a MOS transistor later is formed. At that time, the insulating layer 6
By utilizing the difference in etching rate between the semiconductor substrate and the semiconductor substrate, the insulating layer 6 on the groove region a is not etched. After removing the photoresist 11, next, as shown in FIG.
Impurity diffusion layers 1a and 1b of the opposite conductivity type to the semiconductor substrate forming the source and drain of the MOS transistor are formed on the semiconductor substrate surface and the bottom surface of the groove region b '. afterwards,
A thin film made of the insulating layer 6 is formed in the groove region b'and the groove region b '
Then, the first conductive layer 2 is selectively formed. Then, FIG.
As shown in (d), a groove region c for forming a capacitive element
To form. In this step, the photoresist 11 is formed so as to cover a part of the groove region b ′ and the surface of the semiconductor substrate, and the first conductive layer 2, the thin insulating layer 6, the impurity diffusion layer 1b, and the semiconductor substrate are etched. . At this time, the insulating layer 6 in the groove region a is left by utilizing the difference in etching rate. Since the insulating layer on the groove region b'is sufficiently thinner than the insulating layer on the groove region a, the insulating layer 6 on the groove region a is hardly affected. Then, as shown in FIG. 2E, a thin insulating layer 6 is formed inside the groove region c.
Is formed, the second conductive layer 3 is selectively formed inside the groove region c, and the whole is covered with the insulating layer 6. After that, contact holes are formed in the insulating layer 6 to connect the conductive layers 2 and 3 formed in the adjacent element regions, which are separated by the groove regions a, and the conductive layers 4 and 4 ′ serving as contact wiring are formed later. Formed to obtain the memory cell shown in FIG.

FIG. 3 shows the second embodiment of the present invention.
The figure (a) is a top view, the figure (b) is A- of the figure (a).
A sectional view taken along line A ', and FIG. 7C is a sectional view taken along line BB' in FIG. The symbols in the figures are the same as the symbols used in FIGS. 1, 2 and 5.

In the second embodiment, the upper surface of the insulating layer 6 in the groove area a, which becomes a portion to be the wiring, is located at a position which is as shallow as the bottom surface of the groove area b, so that the conductive layers 2 and 3 are formed. The wiring can be formed as it is, and there is an advantage that the conductive layers 4 and 4'in FIG. 1 are not necessary.

FIGS. 4A to 4E are views showing a manufacturing method of the second embodiment and correspond to FIGS. 2A to 2E. 4 is different from FIG. 2 in the step shown in FIG. 2B. When the groove region b'is formed, the insulating layer 6 on the groove region a is moved to a position almost equal to or slightly shallower than the bottom surface of the groove region b '. It's about etching. After that, wiring is formed in a self-aligned manner in the process of forming the conductive layers 2 and 3.

[0014]

As described above, in the semiconductor memory device according to the present invention, since the channel region of the MOS transistor is formed on one side surface of the groove region perpendicular to the semiconductor substrate, the area of the MOS transistor region on the surface of the semiconductor substrate is reduced. There is an effect that can be done. In addition, in the second embodiment, since the wiring is entirely formed in the groove region, it is effective in flattening the surface. The transistor in the DRAM cell can be regarded as a switch element that connects the bit line and the capacitor. Therefore, since a high driving capability is not always required, it is sufficient to form the channel region on one side surface of the groove region as described above.

[Brief description of drawings]

FIG. 1 is a first embodiment.

FIG. 2 is a cross-sectional view showing a manufacturing process of the first embodiment.

FIG. 3 is a second embodiment

FIG. 4 is a cross-sectional view showing a manufacturing process of the second embodiment.

FIG. 5: Conventional memory cell

[Explanation of symbols] 1a, 1b, 1c Impurity diffusion layer of opposite conductivity type to substrate 2 First conductive layer 3 Second conductive layer 4, 4'Wiring layer 5 MOS transistor channel region 6 Insulating layer 7 Same as substrate Conductive impurity diffusion layer 11 Photoresist a, b, b ', c, d Groove region

Claims (2)

[Claims] 1. A semiconductor memory device comprising a switching element and a capacitive element connected to each other, wherein the switching element and the capacitive element are vertically formed in a groove provided on a semiconductor substrate, and a current of the switching element is formed. A semiconductor memory device, wherein a path is formed only on one side surface of the groove. 2. A semiconductor substrate of one conductivity type having a protrusion and a groove formed at a predetermined distance in one side surface direction of the protrusion, and formed on the surface of the semiconductor substrate and the surface inside the groove. Formed on the surface of the semiconductor substrate that is the protruding portion and between the protruding portion and the groove, and the insulating layer that is formed on the surface of the semiconductor substrate.
Of the impurity diffusion layer, the first conductive layer formed on the insulating layer above the second impurity diffusion layer, and the second conductive layer formed on the insulating layer in the groove so as to fill the groove. A switching element constituted by one side surface of the first conductive layer, the first and second impurity regions, and the protrusion, a second conductive layer, and a surface in the groove. A semiconductor memory device formed by a capacitive element including an insulating layer and the semiconductor substrate, wherein a current path of the switching element is formed only on one side surface of the protrusion. Storage device.