JPH08212705A - Synchronizing circuit - Google Patents

Abstract

PURPOSE: To perform pulling into synchronization qcuickly even if the amount of bit slip is large. CONSTITUTION: At first, it is assumed that synchronization detection is performed on the side of a detection protecting part 22. When a bit slip occurs, the synchronization pattern is not detected within an estimating range. The synchronization pattern is interpolated by a judging circuit 14, and the detecting state becomes 'L'. On the other hand, the synchronization pattern is inputted to the side of a detection protecting part 32 from an AND gate 12, and the pulling into synchronization in performed. When the synchronization pattern enters the estimating range, the entrance is detected with the judging circuit 24, and the synchronization signal output is obtained. The detecting state becomes 'H', and a conciliating circuit 34 is switched to the side of the detection protecting part 32. Therefore, the output synchronization signal of the detection protecting part 32 is outputted from an output terminal TC in place of the detection protecting part 22 hereinafter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit which detects a synchronizing signal in a digital signal reproducing system, protects the missing signal, and appropriately eliminates unnecessary signals.

[0002]

2. Description of the Related Art In a digital signal reproducing system, for example, a digitally recorded disk or tape reproducing device, or a receiving side device of a digital transmission line, a synchronous signal is used for detecting or protecting a synchronizing signal for reproducing the digital signal. A circuit is used. As such a synchronizing circuit, for example, there is one disclosed in Japanese Patent Publication No. 5-74147, but it is necessary to satisfy the following requirements as much as possible.

(1) Elimination of pseudo signal pattern: When the sync signal pattern is detected in a pseudo manner even though it is not the position (timing) of the sync signal, it is desired to eliminate the pseudo pattern. (2) Interpolation of missing sync signal: When the sync signal pattern is not detected at the position where the sync signal originally exists, we want to interpolate and protect the sync signal pattern.

FIG. 5 shows an example of a conventional synchronizing circuit. Further, FIG. 6 shows a timing chart of the same circuit. The input terminal TA is supplied with reproduction data of a digital signal including, for example, a synchronization pattern, and
The detection pattern shown in (A) is the synchronization pattern detection circuit 10.
It is output from 0. In the sync pattern detection circuit 100,
All the synchronization signal patterns in the input signal are detected regardless of the timing and are supplied to the determination circuit 102.
In the initial state, the detection result of the synchronization pattern detection circuit 100 is output as it is from the output terminal TC via the determination circuit 102 and becomes a reset signal of the counter 104.

A reproduction clock pulse is input to the other input terminal TB and is supplied to the counter 104. The counter 104 counts the reproduced clock pulses under the control of the reset signal input from the determination circuit 102. In the prediction range generation circuit 106,
From the count value of the counter 104, a range where the sync signal is predicted to exist, that is, a prediction range is generated as shown in FIG. 6B and is supplied to the determination circuit 102. The predicted position generation circuit 108 generates a position where the synchronization signal is predicted to exist from the count value of the counter 104, that is, a predicted position, as shown in FIG. 6C, and supplies it to the determination circuit 102.

The judgment circuit 102 makes the following judgment from the input detection signal, prediction range, and prediction position. (1) If the sync pattern is detected within the prediction range, the detected sync pattern is output from the output terminal TC as it is. For example, the portion of arrow FA in FIG. 6 corresponds. (2) If no sync pattern is detected within the prediction range,
The synchronization pattern is interpolated at the predicted position and output as an interpolated synchronization signal. The portion indicated by arrow FB in FIG. 6 corresponds to this. (3) The sync pattern detected outside the prediction range is judged to be a pseudo sync signal and is excluded and not output. The portion indicated by arrow FC in FIG. 6 corresponds to this. (4) If no sync pattern is detected outside the prediction range,
do nothing. The portion of arrow FA of FIG. 6 corresponds.

The synchronizing signal output from the judging circuit 102 is also supplied to the counter 104 and serves as its reset signal. FIG. 6D shows the synchronization signal sequence obtained as described above, and FIG. 6E shows the counter 104.
Behavior is shown. The operation of the synchronization circuit as described above is an operation after the transition from the initial pull-in state based on a determination criterion such that the synchronization pattern is periodically detected a plurality of times. If it is determined that the synchronization pattern is not detected within the prediction range for a plurality of times, the initial pull-in state is entered again.

[0008]

By the way, at the time of reproducing digital data, a situation may occur in which the interval of the synchronization pattern is changed from that at the time of recording due to so-called bit slip, that is, some disturbance. The wider the prediction range of the synchronization pattern, the larger the bit slip that can be handled. However, if it is too wide, there is a trade-off relationship that the effect of eliminating the pseudo sync pattern deteriorates.

In the background art described above, inconvenience occurs when a bit slip having a size exceeding such a prediction range occurs. FIG. 7 shows a timing chart in such a case. As shown in FIG.
A bit slip that exceeds the prediction range in FIG. In such a case, since the detection pattern deviates from the prediction range of FIG. 7B after time T2, all the detection patterns at this time are judged as pseudo synchronization patterns and are eliminated.

Therefore, the final sync signal output is time T
1 The prediction position based on the sync pattern detected before 1 is erroneously interpolated. The synchronization signal in the portion indicated by the arrow FD in FIG. 7D is erroneously interpolated. Such a state continues until a transition is made to the pull-in state again, during which the correct synchronization signal cannot be output. For this reason, all the data blocks corresponding to the synchronizing signal during that time become errors, and the influence on the reproducing operation becomes very large.

The present invention focuses on the above points,
It is an object of the present invention to provide a synchronizing circuit that can quickly perform synchronization pull-in to a slipped position even if the bit slip amount is large.

Another object of the present invention is to provide a synchronizing circuit which can reduce the load on the circuit and can quickly pull in the synchronized position even when the bit slip amount is large.

[0013]

In order to achieve the above-mentioned object, the present invention provides a plurality of synchronization protection means for performing synchronization signal detection, synchronization signal interpolation, and synchronization pull-in, among which synchronization pull-in is performed. The output of the synchronization protection means is prioritized. According to the present invention, all synchronization patterns that are not within the prediction range are regarded as pseudo synchronization signals and are not eliminated. When the sync pull-in is performed on one of them satisfying the periodicity, it is output as a sync signal. As a result, even if the bit slip amount is large, it is possible to quickly perform the synchronization pull-in to the slipped position.

According to another aspect of the invention, the periodic state of the synchronization pattern after the bit slip is detected, and if the periodic state is good as a result, synchronization pull-in is performed.

The main aspects of the present invention are as follows. (1) A synchronization pattern detection circuit that receives a digital input signal containing a synchronization signal for each fixed-length block and detects a synchronization pattern, a counter that is synchronously controlled based on the synchronization signal position reference, and a counter that calculates a clock pulse, and this counter The predicted position and the prediction range of the synchronization signal are set from the values, and if the output of the synchronization pattern detection circuit is within the prediction range, it is output as it is, and if it is outside the prediction range, it is excluded, and within the prediction range, the synchronization pattern detection circuit If the output from the above is not obtained, a circuit for monitoring the periodicity of the detected synchronization pattern excluded by the above judgment logic is separately provided for the synchronization protection circuit that has a judgment logic that performs interpolation output at the predicted position. For the output of the sync pattern detector that is judged to have been filled with the periodicity among the excluded sync patterns, A synchronous circuit characterized by adding stages.

(2) With respect to the synchronization protection circuit, the second counter and the second determination logic separately monitor the periodicity of the detected synchronization pattern eliminated by the determination logic, and detect the eliminated synchronization pattern. A synchronizing circuit characterized by further adding circuit means for making the output of the synchronizing pattern detector, which is judged to have been filled with the periodicity, effective.

(3) The synchronization protection circuit is provided with a register for storing the counter value at the position of the detected synchronization pattern excluded by the judgment logic, and the register value at the time of the exclusion at the position of the excluded synchronization pattern. And a counter value are used to monitor the periodicity, and the synchronization pattern detector output that is judged to have satisfied the periodicity among the eliminated synchronization patterns is further validated by circuit means. A synchronous circuit characterized by being added.

The above and other objects, features and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS While there may be many embodiments of the present invention, a suitable number of embodiments will now be shown and described in detail. It should be noted that the same reference numerals are used for the components corresponding to the background art.

<Embodiment 1> First, Embodiment 1 will be described with reference to FIGS. FIG. 1 shows the configuration of the first embodiment. This embodiment basically has a configuration including two systems of the circuit of the background art. The input terminal TA is connected to the synchronization pattern detection circuit 100, and its output side has two-input AND gates 10 and 12.
Is connected to the input side of. The output side of the AND gate 10 has a judgment circuit 14, a counter 16, and a predicted position generation circuit 1.
8. Connected to the detection protection unit 22 including the prediction range generation circuit 20. The output side of the AND gate 12 is the decision circuit 2
4, the counter 26, the predicted position generation circuit 28, and the prediction range generation circuit 30 are connected to the detection protection unit 32.

The output sides of the judgment circuits 14 and 24 are connected to an arbitration circuit 34 which selects the outputs of the detection protection sections 22 and 32 in accordance with the respective detection states. This arbitration circuit 34
The output side of is connected to the selector 36 for selecting the output of the prediction range generating circuit on the side selected by the arbitration circuit 34 and the output terminal TC. Prediction range generation circuit 20
The output side of is connected to the selector 36 as it is, and the output side of the prediction range generation circuit 30 is connected to the selector 36 via the inverter 38.

The output side of the selector 36 is the AND gate 1
They are connected to the input side of 0 and 12, respectively. Among them, the AND gate 12 side has an inverting input, whereby the output of the synchronization pattern detection circuit 100 is masked according to the output of the selector 36.

Next, the basic operation of each part will be described. First, it is assumed that the arbitration circuit 34 selects the synchronization signal output of the detection protection unit 22. At this time, in the selector 36, the prediction range generation circuit 20 side on the detection protection unit 22 side is selected. Therefore, of the outputs of the sync signal detection circuit 100, the sync pattern masked by the output of the prediction range generation circuit 20 is input to the detection protection unit 22. The synchronization patterns detected at other positions are input to the detection protection unit 32.

On the contrary, if the arbitration circuit 34 selects the synchronization signal output of the detection protection section 32, the selector 3
6, the prediction range generation circuit 30 side on the detection protection unit 32 side is selected, and this is output to the AND gates 10 and 12 after being inverted by the inverter 38. Therefore, the detection protection unit 32 includes the synchronization pattern detection circuit 100.
Of the outputs of the above, those masked by the output of the prediction range generation circuit 32 are input. The synchronization patterns detected at other positions are input to the detection protection unit 22. As described above, the detection synchronization pattern is distributed to either one of the detection protection units 22 and 32 complementarily by the action of the AND gates 10 and 12 and the selector 36.

Next, the operation of each of the detection protection sections 22 and 32 is basically the same as the background art. However, the judgment circuit 1
4 and 24 are configured to notify the arbitration circuit 34 of the respective detection states. For example, if a synchronization pattern is detected in the prediction range, a logical value of “H” is detected. If a synchronization pattern is not detected in the prediction range, a logical value of “L”, otherwise the detection state is set to hold. The signal shown is generated and output to the arbitration circuit 34.

Next, the arbitration circuit 34 receives these detection state signals, and outputs, for example, if the detection state of one of the detection protection units 22 and 32 is the logical value "H", that "H". Selects and outputs the synchronization signal of the detection protection unit on the operating side, otherwise, selects and outputs the synchronization signal of the detection protection unit on the currently selected side, and so on. A control signal for the selector 36 is also generated.

Next, the operation of the first embodiment will be described with reference to the timing chart of FIG. It should be noted that the prediction position on the detection protection unit 22 side is PA, the prediction range is WA, the detection state is DA, the synchronization signal output is SA, the prediction position on the detection protection unit 32 side is PB, the prediction range is WB, and the detection state is DB. , The synchronization signal output is SB. First, it is assumed that the detection protection unit 22 side is selected by the arbitration circuit 34 (FIG. 2,
After time Ta). Therefore, the detection synchronization pattern existing in the prediction range WA is input to the detection protection unit 22 side, and the WA
Detection synchronization patterns that are present in other than the above are input to the detection protection unit 32 side. In the illustrated example, the synchronization signal is well detected within the prediction range WA of the detection protection unit 22 until time Tb in the figure (see FIGS. 2A and 2B).

After that, a bit slip occurs and time Tc
Then, it is assumed that the synchronization pattern is not detected within the prediction range WA. Then, the determination circuit 14 interpolates the synchronization pattern at the time Tc (see FIG. 2D), and at the same time, the detection state DA becomes the logical value “L” (see FIG. 2E). The interpolation of the synchronization pattern is continued thereafter, and the synchronization signal SA is output (see FIG. 2D).

Next, at time Td, the synchronization pattern comes to exist outside the prediction range WA. Therefore, time Td
The synchronization pattern of is input to the detection protection unit 32 side via the AND gate 12. This synchronization pattern is the judgment circuit 2
4 (see FIG. 2 (H)), the counter 26
Is reset for the first time, and thereafter, the predicted position generation circuit 28 and the predicted range generation circuit 30 start operating (FIG. 2).
(See (F) and (G)).

Then, at time Tf, a sync pattern comes into the predicted range WB, which is detected by the judgment circuit 24 and becomes the output of the sync signal SB (FIG. 2 (H)).
Then, the detection state DB becomes “H” (see FIG. 2 (I)). When this is supplied to the arbitration circuit 34, the arbitration circuit 3
4 is switched to the detection protection unit 32 side. Therefore, after time Tf, the output synchronization signal SB of the determination circuit 24 is output from the output terminal TC instead of the determination circuit 14 (see FIG. 2 (J)).

After that, since the synchronization pattern is satisfactorily detected within the prediction range WB of the detection protection unit 32 (see FIG. 2).
(See (A) and (F)), and they are output from the output terminal TC. Hereinafter, the synchronization signals SA and SB of the detection protection units 22 and 32 are appropriately switched and output by the same procedure.

As described above, the operation of the first embodiment corresponds to that when one of the detection protectors is in the inertial operation for synchronization detection, the other detection protector is used to perform the synchronization pull-in operation. Therefore, even if the synchronization pattern timing (time position) is largely deviated due to the bit slip, it is possible to quickly lock at the deviated timing. In the example of FIG. 2, it is possible to recover from the synchronization signal at the position at time Tf.

<Second Embodiment> Next, a second embodiment will be described with reference to FIGS. 3 and 4. In the above-mentioned embodiment, the detection protection section is provided in two systems, but in this embodiment, two systems are provided.
It is intended to obtain the same effect as that of the first embodiment by simplifying the circuit configuration. The configuration is shown in FIG. 3, and the synchronization pattern detection circuit 100, the counter 104, the prediction range generation circuit 106, and the prediction position generation circuit 108 are the same as those of the background art.

However, the decision circuit 50 includes a register 52,
A comparator 54 is provided and performs a judgment operation different from that of the judgment circuit 102 in the background art as described below. (1) If the sync pattern is detected within the prediction range, the detected sync pattern is output from the output terminal TC as it is. (2) If no sync pattern is detected within the prediction range,
The synchronization pattern is interpolated at the predicted position and output as an interpolated synchronization signal.

(3A) If the counter value of the counter 104 at that time and the value of the register 52 are equal, the sync pattern detected outside the predicted range is output as it is as a sync signal. (3B) However, if the counter value of the counter 104 and the value of the register 52 are different, it is determined as a pseudo sync pattern, and this is excluded and not output. (4) If no sync pattern is detected outside the prediction range,
do nothing. As described above, (1), (2), and (4) are similar to the background art, but the operations of (3A) and (3B) are different, and the judgment for the synchronization pattern detected outside the prediction range is subdivided. Has been done.

The determination circuit 50 also generates and outputs control signals for setting and clearing the register 52 as follows. (1) When it is determined that the output of the synchronization pattern detection circuit 100 is obtained outside the prediction range, the set signal is output to the register 52. (2) When the output of the synchronization pattern detection circuit 100 is output as it is, a clear signal is output to the register 52. In addition to the above, the value of the register 52 is held.

The value of the counter 104 and the value of the register 52 are input to the comparator 54, and the comparator 54 compares them. Then, the coincidence detection result is supplied to the determination circuit 50.

Next, the operation of the second embodiment will be described with reference to the timing chart of FIG. Times Ta to Tb in the figure
As shown in, when the synchronization pattern is detected within the prediction range, it is apparently the same as the background art (see (A), (B), and (D) in the same figure). Here, if a bit slip occurs, no synchronization pattern is detected within the prediction range at time Tc. Therefore, the determination circuit 50 interpolates the synchronization pattern at the timing of the predicted position (see (C) and (D) in the figure).

Since a bit slip has occurred, the synchronization pattern is detected at the timing of time Td, which is outside the prediction range. Therefore, in the determination circuit 50, the count value of the counter 104 at that time is set in the register 52. In the illustrated example, as shown in FIG.
Has a count value of Ca. This is register 5
Set to 2.

Next, at time Te, since the synchronization pattern is not detected within the prediction range as at time Tc, the decision circuit 5
The synchronization pattern is interpolated by 0 ((A) in the figure,
(See (B) and (D)). Further, since the clear signal is not output from the judgment circuit 50, the value of the register 52 is held as it is. After that, at time Tf, the synchronization pattern is detected again outside the prediction range. Therefore, the decision circuit 50 refers to the output of the comparator 54 at that time.

By the way, in the comparator 54, the register 52
And the value of the counter 104 are compared. Since the value of the register 52 is the count value of the counter 104 at the time Td, it means that the two coincide with each other at the time Tf.
It means that the count value of the counter 104 at time Td matches the count value of the counter 104 at time Td. As shown in (E) of the figure, the counter 104 is reset by the synchronization signal output of the determination circuit 50,
Normally, the counting operation is repeated at the cycle of the synchronization signal. Therefore, the fact that the value of the counter 104 becomes equal at the times Td and Tf means that the interval between those times matches the cycle Wck of the synchronization signal. From this point of view, the register 52 and the comparison circuit 54 detect the periodic state of the synchronization signal after the bit slip.

Therefore, if the period of the synchronization pattern after the bit slip is the predetermined value Wck, the outputs of the comparators 54 match, the outputs become active, and the fact is input to the determination circuit 50. . In the judgment circuit 50, this time T
At the same time that the synchronization pattern at the time point of f is output as it is (see FIG. 3D), the counter 104 is reset. As a result, the counter 104, the prediction range generation circuit 106, and the prediction position generation circuit 108 come to operate with the time Tf as a reference (see (B), (C), and (E) in the same figure), and the synchronous pull-in operation is performed. Will be seen. The determination circuit 50 also clears the register 52 to prepare for the occurrence of the next bit slip.

If the counter value and the register value do not match at the time Tf, it can be determined that a further bit slip has occurred and the cycle of the synchronization pattern is disturbed. Therefore, the counter 104 counts at that time. The value is set again in the register 52 and is prepared for the next synchronization pattern detection. After that, the procedure described above is repeated to perform synchronization protection.

As described above, according to the second embodiment, the first embodiment
As described above, it is not necessary to add another set of detection protection units, and by using the register 52 and the comparator 54, an effect substantially similar to that of the first embodiment can be obtained, and the circuit load is significantly reduced. Also, it is advantageous in terms of cost.

<Other Embodiments> The present invention can be variously modified based on the above disclosure, and includes, for example, the following.

(1) In the first embodiment, two sets of detection protection units are used. However, if the number of detection protection units is further increased, more synchronization patterns located outside the prediction range of the currently selected detection protection unit are targeted. It is possible to independently perform the pull-in operation.

(2) Further, the first embodiment is characterized in that each detection protection section outputs the synchronization pattern detection state and the output is switched by the arbitration circuit according to the synchronization pattern detection state. The generating means and the output selecting means in the arbitration circuit are not limited to those in the above embodiment. For example, in each detection protection unit, "N within the prediction range
The synchronization pattern is detected consecutively. , "A sync pattern has not been detected M times consecutively within the prediction range." Is used to generate the priority of the detection state, and the arbitration circuit selects the output according to the priority. You may. In addition, in the first embodiment,
It can be considered that M = N = 1.

(3) Also in the second embodiment, by increasing the number of registers 52, it becomes possible to independently perform the pull-in operation targeting more synchronization patterns located outside the prediction range.

(4) Further, in the second embodiment, as a condition for outputting the synchronization signal detected outside the prediction range as a valid signal, only the perfect match between the counter value and the register value at that position is observed. . That is, the bit slip during that time is not recognized. However, the comparator in FIG. 3 is configured by a subtractor, and the judgment criterion (3A) of the judgment circuit 50,
(3B)

(3a) The synchronization pattern detected outside the prediction range is output as it is if the output of the subtractor is within the range of ± n (n is an arbitrary integer value set in advance). (3b) If the output of the subtractor is not within the range of ± n, the synchronization pattern detected outside the predicted range is determined to be a pseudo synchronization signal and is excluded and not output. If so, it is possible to provide a prediction range of ± n with respect to a synchronization signal detected outside the prediction range. That is, it is possible to cope with ± n bit slips.

(5) In the second embodiment, the synchronization pattern obtained outside the prediction range is immediately validated when the counter value and the register value at that time match. It is also possible to adopt a configuration in which it is enabled only when the matching of is confirmed. Furthermore, when outputting the synchronization pattern detected outside the prediction range as valid, a constraint condition such as "a synchronization pattern has not been obtained consecutively N times within the prediction range" may be added.

[0052]

As described above, the present invention has the following effects. (1) Multiple detection protection units are provided, and when one of the detection protection units is in inertial motion, the other detection protection unit is used to perform the pull-in operation. Even if it shifts, it is possible to promptly perform the synchronization pull-in at the shifted position.

(2) Since it is decided to monitor the synchronization state after the bit slip has occurred, the circuit load is reduced and
It is possible to quickly perform the synchronization pull-in to the position after the bit slip.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a configuration of a second embodiment.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a block diagram showing a configuration of background art.

FIG. 6 is a timing chart showing the operation of the background art.

FIG. 7 is a timing chart showing how a bit slip occurs.

[Explanation of symbols]

 10, 12 ... AND gates 14, 24, 50 ... Judgment circuit 16, 26, 104 ... Counter 18, 28, 108 ... Predicted position generation circuit 20, 30, 106 ... Predicted range generation circuit 22, 32 ... Detection protection unit 34 ... Arbitration circuit 36 ... Selector 38 ... Inverter 52 ... Register 54 ... Comparator 100 ... Synchronous pattern detection circuit Ca ... Count values T1, T2, T to aTf ... Time Wck ... Cycle

Claims (2)

[Claims] 1. A synchronization pattern detecting means for detecting a synchronization pattern from a digital signal; a plurality of synchronization protection means for detecting a synchronization signal from the synchronization pattern, interpolating the synchronization pattern, and pulling in synchronization when a bit slip occurs. Input control means for supplying the synchronization pattern to any one of the synchronization protection means with reference to the prediction range of each synchronization protection means; arbitration means for giving priority to the output of the synchronization protection unit in which synchronization is pulled in; The synchronization protection means is a counter that performs a counting operation in synchronization with detection of a synchronization signal;
Prediction position setting means for setting the prediction position of the synchronization pattern based on the count value of the counter; Prediction range setting means for setting the prediction range of the synchronization pattern based on the count value of the counter; Detecting the synchronization signal with reference to the prediction range And a determination circuit for interpolating the synchronization signal with reference to the predicted position; 2. A sync pattern detecting means for detecting a sync pattern from a digital signal; a counter for performing a counting operation in synchronization with the sync signal detection; a predictive position setting means for setting a predictive position of the sync pattern based on a count value of the counter. Prediction range setting means for setting the prediction range of the synchronization pattern based on the count value of the counter; Cycle state detection means for detecting the cycle state of the synchronization pattern detected outside the set prediction range; While detecting the sync signal, refer to the predicted position to interpolate the sync signal,
A synchronization circuit including a determination unit that refers to a cycle state to perform synchronization pull-in.