JPH08212698A - Data processing device - Google Patents

Abstract

PURPOSE: To obtain a CD-ROM signal processing circuit which can reduce the load on a sub-CPU. CONSTITUTION: A comparison processing circuit 4 compares successively a sector address A2 desired to start transferring output from a CD-ROM signal processing circuit 2 (sector address desired to finish transferring output) with a sector address A1 read out from a disk 59, judges whether both coincide with each other or not, and a control signal S2 (the inverse of S2) is generated conforming to the judged result. A transfer control circuit 75 being in an inactivated state or an activated state is activated when the control signal S2 (the inverse of S2) is inputted, and transfer to a main CPU 56 and a picture voice reproducing device 58 from the front of a sector outputted next of a decode core circuit 74 is started or stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device.

[0002]

2. Description of the Related Art CDs (Compact Disks) are widely used all over the world as media for providing high-quality music information.
In recent years, not only music information but also multimedia in which image information and audio information are mainly used has been promoted. Various CDs used in multimedia are collectively called a CD family. The CD family includes the CD-DA (CD-Digital Audio) family, which is a so-called music CD, and the CD-RO, which is a so-called data CD.
There are M (CD-Read Only Memory) families. C
The D-ROM family includes CD-IFMV (CD-Interac
tive Full Motion Video) or CD-IDV (CD-Inte
ractive Digital Video) etc. CD-IFMV
Has video CDs and karaoke CDs.

The information handled by multimedia is enormous and diverse, and it is necessary to process such information at high speed in order to put multimedia into practical use. In order to process information at high speed, data compression / decompression technology is essential. Compression of such data
As an extension technology, "MPEG (Moving Picture Expert Gro
up) ”method. This MPEG system is IS
O (International Organization for Standardizatio
n) / IEC (Intarnational Electrotechnical Commiss)
ion) MPEG committee (ISO / IEC JTC1 / SC29 / WG1
It is being standardized by 1). MPEG is composed of three parts. In Part 1, "MPEG System Part" (ISO / IEC IS 11172 Part1: Systems),
A multiplexing structure of video data and audio data and a synchronization method are specified. Part 2, "MPEG Video Part" (ISO / IEC IS
11172Part2: Video) specifies a high-efficiency coding method for video data and a video data format. Part 3, "MPEG Audio Part" (ISO / IE
CIS 11172 Part3: Audio) specifies a high-efficiency encoding method for audio data and an audio data format.

By using the MPEG system, a CD
-Video reproduction is possible even in the ROM family.
Karaoke CD is MP from CD-IFMV format
Only the part relating to the EG method is taken out and only the moving image is reproduced. In addition to video playback, video CDs
A menu playback function called PBC (Play Back Control) that enables a still image playback and a combined expression of still image playback and moving image playback is added. Therefore,
Video CD is compatible with CD-IFMV, CD-I
An FMV player can play a video CD format disc.

Data recording on a video CD is continuously performed in units of sectors, and the data is read by a video CD player at a constant speed of 75 sectors per second.

A sector is composed of a header, a subheader and a data field. The header and sub-header store the sector address, data format, form type, coding information, and the like. The data format is classified into a video sector, an audio sector, and a data sector depending on the type of data recorded in the sector. The application program is recorded in the data sector. The form indicates the presence or absence of an error correction code in the data field. The coding information indicates the coding format of the sector.

FIG. 2 shows a block circuit of a conventional video CD player 51. The video CD player 51 includes a disk drive device 52 and a CD signal processing circuit (CD-DSP;
CD-Digital Signal Processor) 53, CD-ROM signal processing circuit (CD-ROM-DSP) 54, sub CPU
55, a main CPU (host) 56, a user interface circuit 57, and an image / sound reproduction device 58.

The disk drive device 52 includes an optical pickup for reading data recorded on the video CD format disk 59, a rotary drive device for the disk 59, and the like. Then, the data recorded on the disk 59 is read from the disk drive device 52 at a constant speed of 75 sectors per second. The data (sector) read from the disc 59 is output to the CD signal processing circuit 53.

The CD signal processing circuit 53 performs signal processing (error correction, etc.) conforming to the CD format on the sectors read from the disk 59, and the CD-ROM signal processing circuit 54 processes the signal processed sectors. Output to.

The CD-ROM signal processing circuit 54 includes interface circuits 71 and 72, a register 73, a decode core circuit 74, and a transfer control circuit 75. The interface circuit 71 receives the sector output from the CD signal processing circuit 53, detects the sector address based on the sector header of the sector, and outputs the sector address to the register 73. Each time the interface circuit 71 outputs a new sector address, the register 73 discards the previously stored sector address and stores the new sector address.

The sector address stored in the register 73 is read by the sub CPU 55, and the sector address is read via the interface circuit 72.
55. The control signal S1 (or bar S1) output from the sub CPU 55 is transferred to the transfer control circuit 75 via the interface circuit 72.

The decode core circuit 74 sends a CD-R to the sector input via the interface circuit 71.
Signal processing based on OM format (error correction, etc.)
I do.

The transfer control circuit 75 controls the start and end of the transfer output of the sector from the CD-ROM signal processing circuit 54 to the main CPU 56 and the video / audio reproduction device 58. That is, the transfer control circuit 75 in the inactive state is
When the control signal (enable signal) S1 is input, it is activated, and the main CPU 56 and the video / audio reproduction device 5 are activated from the beginning of the sector output next from the decode core circuit 74.
Transfer to 8 is started. The active state of the transfer control circuit 75 continues until the control signal (disable signal) bar S1 is input. Then, the transfer control circuit 7 in the active state
5 is inactivated when the control signal bar S1 is input,
The transfer from the decode core circuit 74 to the main CPU 56 and the video / audio reproduction device 58 is stopped from the beginning of the next sector. In other words, once the control signal S1 is input, the transfer control circuit 75 causes the main CPU 56 and the video / audio reproduction unit to output each sector sequentially output from the decode core circuit 74 until the next control signal bar S1 is input. Sequential transfer to the device 58.

The image / sound reproduction device 58 includes a system decoder 81, an MPEG video decoder 82, an MPEG audio decoder 83, a video output processing circuit 84, and an audio D / A converter 85.

The system decoder 81 distinguishes the sectors according to the data format, and separates the MPEG video stream (video data data string) from the video sector and the MPEG audio stream (audio data data string) from the audio sector.

The video decoder 82 decodes the MPEG video stream according to the MPEG video part, and outputs the decoding result to the video output processing circuit 84. The audio decoder 83 decodes the MPEG audio stream in accordance with the MPEG audio part, and outputs the decoding result to the audio D / A converter 85.

The video output processing circuit 84 is a video D / A.
A converter and an NTSC (or PAL) encoder are provided, a video output is produced | generated from the decoding result of the video decoder 82, and the video output is output to the display provided externally.

The audio D / A converter 85 generates an audio output from the decoding result of the audio decoder 83, and outputs the audio output to an external audio reproducing device.

The user interface circuit 57 generates a control signal based on an instruction from a user who uses the video CD player 51. The main CPU 56 is a CD-R
The image / audio reproduction device 58 is controlled based on the control signal of the sector or the user interface circuit 57 output from the OM signal processing circuit 54.

The sub CPU 55 receives the CD signal processing circuit 53 based on the control signal from the user interface circuit 57.
And the CD-ROM signal processing circuit 54. Next, from the CD-ROM signal processing circuit 54 to the main CPU 5
6 and the control operation of the transfer output of the sector to the video / audio reproduction device 58 will be described.

The user uses the user interface circuit 57 to indicate to the sub CPU 55 which sector of the data recorded on the disk 59 the reproduction is to be started from (or which sector the reproduction is to be ended). Give instructions. For example, when a plurality of programs are recorded on the disc 59 and the user specifies a program to be reproduced, the user interface circuit 57 generates a control signal corresponding to the sector address of the first sector of the program. After that, the user interface circuit 57 generates a control signal corresponding to the sector address of the last sector of the program.

The sectors read from the disk 59 are
It is input to the CD-ROM signal processing circuit 54 via the CD signal processing circuit 53. The sector address of the sector is detected by the interface circuit 71, and the sector address is stored in the register 73. The sector address stored in the register 73 is read by the sub CPU 55, and the sector address is read by the interface circuit 72.
Is transferred to the sub CPU 55 via.

The sub CPU 55 controls the user interface circuit 57 (control signal corresponding to the sector address of the first or last sector of the program designated by the user) and the sector address of the sector read from the register 73 (disk. A control signal S1 (or bar S1) for controlling the transfer control circuit 75 is generated on the basis of the sector address of the sector read from 59).

That is, the sub CPU 55 compares the sector address at the beginning of the program (the sector address of the sector where the transfer output is to be started) with the sector address read from the disk 59, and determines that they match. ,
The control signal S1 is generated. The control signal S1 is transferred to the transfer control circuit 75 via the interface circuit 72. The transfer control circuit 75 is activated according to the control signal S1, and the main CPU 56 and the video / audio reproduction device 58 are activated from the beginning of the sector output next from the decode core circuit 74.
Transfer to.

After that, the sub CPU 55 compares the last sector address of the program (the sector address of the sector whose transfer output is to be ended) with the sector address read from the disk 59, and determines that they match. , Generate a control signal bar S1. The control signal bar S1 also
It is transferred to the transfer control circuit 75 via the interface circuit 72. The transfer control circuit 75 in the active state is inactivated according to the control signal bar S1, and the decode core circuit 74 is activated.
From the beginning of the sector output next from the main CPU 56
And the transfer to the image / audio reproduction device 58 is stopped.

As described above, the sub CPU 55 uses the CD-R
The sector address at which transfer output is to be started from the OM signal processing circuit 54 (or the sector address at which transfer output is to be ended) is sequentially compared with the sector address read from the disk 59 to determine whether they match. ,
Control signal S1 (or bar S1) according to the determination result
Is generated to control the transfer control circuit 75. That is, the sub CPU 55 makes the above determination for each sector read from the disk 59, and controls the transfer control circuit 75 according to the determination result.

[0027]

The sub CPU 55 not only controls the transfer control circuit 75 but also controls other circuits (71 to 74, etc.) in the CD-ROM signal processing circuit 54 and C.
It is also necessary to control the D signal processing circuit 53. Therefore, as described above, the start and end operations of the sector transfer output from the CD-ROM signal processing circuit 54 are performed by the sub CPU.
Controlling 55 causes a great load on the sub CPU 55.

As a result, the operating speed of the sub CPU 55 decreases, and the operating speeds of the CD signal processing circuit 53 and the CD-ROM signal processing circuit 54 are adversely affected. If the functions of the video CD player 51 are expanded in the future, each circuit 53,
54 is required to operate at a higher speed than at present. Therefore, the decrease in the operation speed of the sub CPU 55 will prevent future expansion of the functions of the video CD player 51.

The present invention has been made to solve the above problems, and an object thereof is a data processing apparatus capable of reliably controlling the start and end of data transfer output to the outside. To provide.

[0030]

SUMMARY OF THE INVENTION The gist of the invention described in claim 1 is that the start and end of data transfer output to the outside can be controlled inside the device.

According to a second aspect of the present invention, when a set of data that is serially transferred and data to which an address is given for each set is input, an address for detecting the address of the data is input. The detection means and the active state and the inactive state are switched according to the control signal. When the active state, the input data is transferred to the outside and output, and when the inactive state, the input data is stopped from being output to the outside. Transfer control means, an address setting means for setting a data address for starting transfer output to the outside, and a data address for ending transfer output for the outside, a first address detected by the address detecting means, and an address And a comparison processing unit that compares the second address set by the setting unit and generates a control signal according to the comparison result. And the gist thereof.

According to a third aspect of the present invention, when a pack conforming to the MPEG format is input, a pack address detecting means for detecting a pack address based on the pack header, and an active state and an inactive state according to a control signal. Are switched, and the transfer control means for transferring and outputting the input pack to the outside in the active state and stopping the transfer output to the outside of the input pack in the inactive state, and for each input pack The pack address of the pack whose external transfer output is to be started and the pack address of the pack whose external transfer output is to be ended, and the first pack address detected by the pack address detecting means. And the second pack address set by the pack address setting means are compared, and control is performed according to the comparison result. As its gist that a comparison processing means for generating a degree.

According to a fourth aspect of the present invention, the sector address detecting means for detecting the sector address based on the sector header of the input sector, and the active state and the inactive state are switched in accordance with the control signal so that the active state is maintained. Transfer control means that sometimes transfers the input sector to the outside and outputs it when it is inactive, and transfer control means that stops the transfer output to the outside of the input sector and the transfer output to the outside for each input sector. Sector address setting means for setting the sector address of the sector to start and the sector address of the sector to end the transfer output to the outside, the first sector address detected by the sector address detecting means, and the sector address setting means And a comparison processing means for generating a control signal according to the comparison result. It is referred to as the gist thereof.

According to a fifth aspect of the invention, the sector address detecting means for detecting the sector address based on the sector header of the sector output from the CD signal processing circuit, and the active state and the inactive state are switched according to the control signal. The
In the active state, the sector output from the CD signal processing circuit is transferred and output to an external device, and in the inactive state, C
The transfer control means for stopping the transfer output of the sector output from the D signal processing circuit to the external device, the first register for storing the sector address output from the sector address detection means, and the CD signal processing circuit are output. For each sector, a sector address setting means for setting a sector address of a sector whose transfer output to the external device is to be started and a sector address of a sector whose transfer output to the external device is to be ended, and a sector address setting means are provided. The second register that stores the set sector address, the first sector address read from the first register, and the second sector address read from the second register are compared, and the comparison is performed. The gist of the present invention is to have a comparison processing means for generating a control signal according to the result.

According to a sixth aspect of the present invention, a CD signal processing circuit for performing signal processing conforming to the CD format on a sector read from a disc on which data is recorded in the CD format, and a CD signal processing circuit. The sector signal detecting means for receiving the sector output from the CD sector and detecting the sector address on the basis of the sector header of the sector, and the active state and the inactive state are switched according to the control signal. Transfer control means for transferring and outputting the output sector to an external device and stopping transfer output of the sector output from the CD signal processing circuit to the external device when inactive, and a new sector address from the sector address detecting means. Whenever is output, the sector address stored before is discarded and a new sector address is Address for each sector output from the CD signal processing circuit and the sector address of the sector for which the transfer output to the external device is to be started and the sector address for which the transfer output to the external device is to be ended. The sector address is set, and each time a new sector address is output from the sector address setting means that outputs each sector address and the sector address setting means, the sector address stored before that is discarded, A second register for storing a new sector address; a first sector address read from the first register;
The gist of the present invention is that the second sector address read from the register is compared with the second sector address, and a comparison processing unit that generates a control signal according to the comparison result is provided.

According to a seventh aspect of the present invention, in the data processing apparatus according to any one of the fourth to sixth aspects, in the comparison processing means, the value of the first sector address is the value of the second sector address. It is a gist to generate a control signal when it coincides with.

According to an eighth aspect of the present invention, in the data processing apparatus according to any one of the fourth to sixth aspects, in the comparison processing means, the value of the first sector address is the value of the second sector address. The gist of the invention is to generate a control signal when the value exceeds the limit.

According to a ninth aspect of the present invention, in the data processing device according to any one of the fourth to sixth aspects, the transfer control means, when activated, is a sector which is next output from the CD signal processing circuit. The gist of the invention is to start the transfer output to the outside from the beginning of the sector and to stop the transfer output to the outside from the beginning of the sector output next from the CD signal processing circuit when it becomes inactive.

The invention according to claim 10 is the invention according to claims 4 to 6.
In the data processing device according to any one of items 1 to 3, the transfer control means, when activated, starts the transfer output to the outside as it is, even if the sector output from the CD signal processing circuit is in the middle, and is inactive. In the state, the gist is to stop the transfer to the outside even if the sector output from the CD signal processing circuit is in the middle.

[0040]

According to the first aspect of the invention, the start and end of the data transfer output to the outside can be controlled inside the device.

According to the second aspect of the present invention, the transfer control means is controlled according to the control signal generated according to the comparison result of the first address and the second address by the comparison processing means, and the data is transferred to the outside. The start and end of transfer output are controlled.

According to the third aspect of the present invention, the transfer control means is controlled according to the control signal generated according to the comparison result of the first pack address and the second pack address by the comparison processing means, and the outside of the pack. Controls the start and end of transfer output to.

According to the invention described in any one of claims 4 to 6, the transfer control means according to the control signal generated according to the comparison result of the first sector address and the second sector address by the comparison processing means. Is controlled to control the start and end of the transfer output to the outside of the sector.

According to the invention described in claim 5 or claim 6, by providing the first and second registers,
The comparison processing of the comparison processing means can be reliably performed. According to the invention of claim 6, when the first and second registers store a new sector address, the sector address stored before that is discarded, so the first and second registers The operation of becomes reliable.

According to the invention described in claim 7, when the value of the first sector address matches the value of the second sector address, the transfer control means is switched between the active state and the inactive state.

According to the invention described in claim 8, when the value of the first sector address exceeds the value of the second sector address, the active state and the inactive state of the transfer control means are switched. Therefore, even if there is an error in the sector address read from the disk, if the correct sector address is read, the state of the transfer control means is surely switched.

According to the invention described in claim 9, the sectors transferred and output from the transfer control means are in sector units, and do not include sectors which are interrupted in the middle. According to the tenth aspect of the invention, the sectors transferred and output from the transfer control means include sectors that are interrupted in the middle.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below with reference to FIG. In the present embodiment, the same components as those in the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 shows a video CD player 1 of this embodiment.
The block circuit of is shown. The video CD player 1 includes a disc drive device 52, a CD signal processing circuit 53, and a CD-RO.
An M signal processing circuit 2, a sub CPU 55, a main CPU (host) 56, a user interface circuit 57, and an image / sound reproduction device 58 are provided.

The CD-ROM signal processing circuit 2 includes interface circuits 71 and 72, registers 73 and 3, a decode core circuit 74, a transfer control circuit 75, and a comparison processing circuit 4.

The sector address stored in the register 73 is read by the comparison processing circuit 4. Sub C
The sector address output from the PU 55 is transferred to the register 3 via the interface circuit 72. Each time a new sector address is transferred from the interface circuit 72, the register 3 discards the previously stored sector address and stores the new sector address. The sector address stored in register 3 is
It is read by the comparison processing circuit 4.

The comparison processing circuit 4 reads the sector address from the register 73 (the sector address read from the disk 59; hereinafter referred to as the sector address A1).
And the sector address read from register 3 (sub-C
Sector address output from PU55. Hereinafter, the sector address A2) is compared with each other, and when it is determined that they match each other (A1 = A2), the control signal S2 (or bar S2) is generated.

The transfer control circuit 75 controls the start and end of the transfer output of the sector from the CD-ROM signal processing circuit 2 to the main CPU 56 and the video / audio reproducing device 58. That is, the transfer control circuit 75 in the inactive state is
When the control signal (enable signal) S2 is input, it is activated, and the main CPU 56 and the video / audio reproduction device 5 are activated from the beginning of the sector output next from the decode core circuit 74.
Transfer to 8 is started. The active state of the transfer control circuit 75 continues until the control signal (disable signal) bar S2 is input. Then, the transfer control circuit 7 in the active state
5 is inactivated when the control signal bar S2 is input,
The transfer from the decode core circuit 74 to the main CPU 56 and the video / audio reproduction device 58 is stopped from the beginning of the next sector. In other words, once the control signal S2 is input, the transfer control circuit 75 causes the main CPU 56 and the audio / video reproduction to output each sector sequentially output from the decode core circuit 74 until the next control signal bar S2 is input. Sequential transfer to the device 58.

Next, the control operation of the sector transfer output from the CD-ROM signal processing circuit 2 to the main CPU 56 and the image / audio reproducing device 58 will be described. The user uses the user interface circuit 57 to instruct the sub CPU 55 as to which sector of the data recorded on the disk 59 the reproduction should be started (or in which sector the reproduction should be ended). For example, disk 5
When a plurality of programs are recorded in 9, the user specifies the program to be reproduced, and the user interface circuit 57
Generates a control signal corresponding to the sector address of the first sector of the program. After that, the user interface circuit 57 generates a control signal corresponding to the sector address of the last sector of the program.

The sub CPU 55 generates the sector address A2 based on the control signal of the user interface circuit 57 (control signal corresponding to the sector address of the first or last sector of the program designated by the user).

That is, the sub CPU 55 first generates the same sector address A2 as the sector address at the beginning of the program (the sector address of the sector to start the transfer output). The sector address A2 is the interface circuit 7
It is transferred to and stored in the register 3 via 2.

The sectors read from the disk 59 are
It is input to the CD-ROM signal processing circuit 2 via the CD signal processing circuit 53. The sector address A1 of the sector is detected by the interface circuit 71, and the sector address A1 is stored in the register 73. Register 7
The sector address A1 stored in No. 3 is compared with the comparison processing circuit 4
Read by.

The comparison processing circuit 4 compares the sector address A1 and the sector address A2, and if it determines that they match, it generates a control signal S2. Transfer control circuit 7
5 is activated according to the control signal S2, and the main CP from the head of the sector next output from the decode core circuit 74.
The transfer is started to the U56 and the image / audio reproduction device 58.

Next, the sub CPU 55 generates the same sector address A2 as the last sector address of the program (the sector address of the sector for which the transfer output is to be ended). The sector address A2 is also transferred to and stored in the register 3 via the interface circuit 72.

The comparison processing circuit 4 compares the sector address A1 and the sector address A2, and if it determines that they match, it generates a control signal bar S2. The transfer control circuit 75 is inactivated in accordance with the control signal bar S2, and stops the transfer from the decode core circuit 74 to the main CPU 56 and the video / audio reproduction device 58 from the beginning of the next sector.

As described above, the comparison processing circuit 4 uses the CD-R
The sector address (or sector address) A2 from which the transfer output is to be started from the OM signal processing circuit 2 and the sector address A1 read from the disk 59 are sequentially compared to determine whether they match. The transfer control circuit 75 is controlled by making a determination and generating a control signal S2 (or bar S2) according to the determination result. That is, the comparison processing circuit 4 makes the above determination for each sector read from the disk 59, and controls the transfer control circuit 75 according to the determination result.

Therefore, the sub CPU 5 in this embodiment is
5 only needs to generate the sector address A2, and there is no need to perform the operation of determining the match of the sector addresses and the operation of controlling the transfer control circuit 75 according to the determination result as in the conventional example.

Therefore, according to this embodiment, the sub CPU 5
It is possible to significantly reduce the load applied to 5. As a result, the operating speed of the sub CPU 55 is improved, and accordingly, the operating speeds of the CD signal processing circuit 53 and the CD-ROM signal processing circuit 2 are also improved.

The above embodiment may be modified as follows, and in that case, the same operation and effect can be obtained. (1) The comparison processing circuit 4 compares the sector address A1 and the sector address A2 and determines that the value of the sector address A1 exceeds the value of the sector address A2 (A1> A).
2) Generate the control signal S2 (or bar S2).

As in the above embodiment, the sector address A1
If the control signal S2 (or bar S2) is generated only when the sector address A2 and the sector address A2 match, the control signal S2 is generated when the sector address A1 is incorrect.
(Or bar S2) will not be output. For example, when the disk 59 is scratched, the sector address A1 of the sector read from the disk 59 may be incorrect. Therefore, if the control signal S2 (or bar S2) is generated when the value of the sector address A1 exceeds the value of the sector address A2, the sector address A2
Even if the sector address A1 to be matched with is wrong, if the correct sector address A2 is input after that, the transfer control circuit 75 can be surely controlled.

(2) Transfer control circuit 75 in the inactive state
Immediately after the control signal S2 is input, starts the transfer to the main CPU 56 and the video / audio reproduction device 58 as it is, even if the sector output from the decode core circuit 74 is in the middle. Then, immediately after the control signal bar S2 is input, the transfer control circuit 75 in the active state sends data to the main CPU 56 and the video / audio reproduction device 58 even if the sector output from the decode core circuit 74 is in the middle. Stop the transfer.

In this case, an incomplete sector which is interrupted on the way is transferred to the main CPU 56 and the image / audio reproducing device 58. Therefore, inside the main CPU 56 and the video / audio reproduction device 58, the sectors transferred from the middle (or the sectors transferred to the middle) are discarded.

(3) Two registers 3 are provided, and CD-RO
The sector address at which transfer output is to be started and the sector address at which transfer output is to be ended are separately stored in the respective registers from the M signal processing circuit 2.

(4) A CD, not a video CD player
-Applies to ROM devices. In this case, the user interface circuit 57 and the video / audio reproduction device 58 are omitted. (5) Applies to all CD-ROM families including not only video CDs but also karaoke CDs. Also, CD-
It applies not only to the ROM family but also to the entire CD family including the CD-DA family.

(6) Not only CD family but VTR
(Video Tape Recorder), LD (Laser Disk), DV
It is applied to all storage media using the MPEG system such as D (Digital Video Disk). Further, the invention is applied not only to storage media but also to all communication media using the MPEG system. In this case, the sector in the above embodiment is MP
Corresponding to the pack in the EG format, the sector header corresponds to the pack header, and the sector address corresponds to the pack address.

(7) It is applied to the processing of a set of data that is serially transferred and to which data is assigned an address for each set. In this case, the format of the data does not matter.

Although the respective embodiments have been described above, the technical ideas other than the claims which can be understood from the respective embodiments will be described.
The effects will be described below. (A) The data processing device according to any one of claims 4 to 6, wherein the sector address setting means comprises a CPU and a user interface.

In this way, the sector address can be set reliably. (B) In the data processing device according to any one of claims 4 to 6, the second register has a register for storing a sector address of a sector whose transfer output to the outside is to be started and a transfer output to the outside. A data processing device comprising two registers, a register for storing a sector address of a sector to be terminated. In this way, the two sector addresses can be stored in separate registers, so that the comparison processing of the comparison processing means can be reliably performed.

By the way, in this specification, the members relating to the constitution of the invention are defined as follows. (A) CD is not only a video CD, but a karaoke CD
It also includes the entire CD-ROM family including the above, and the entire CD family including the CD-DA family.

(B) The sector address setting means is a sub CP
It is composed of a U55 and a user interface circuit 57. (C) The sector address detecting means means the interface circuit 71.

(D) The comparison processing means means the comparison processing circuit 4. (E) The transfer control means means the transfer control circuit 75. (F) The external device refers to the main CPU 56 or the video / audio reproduction device 58.

[0077]

As described above in detail, according to the present invention, it is possible to provide a data processing device capable of reliably controlling the start and end of data transfer output to the outside inside the device.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment.

FIG. 2 is a block circuit diagram of a conventional example.

[Explanation of symbols]

 3 ... Second register 4 ... Comparison processing circuit as comparison processing means 53 ... CD signal processing device 55 ... Sub CPU 57 ... User interface circuit 59 ... Disk 71 ... Interface circuit 73 ... First register 75 ... Transfer control circuit

Claims (10)

[Claims] 1. A data processing device capable of internally controlling the start and end of data transfer output to the outside. 2. When a set of data that is serially transferred and data to which an address is given for each set is input, an address detection unit that detects the address of the data, and a control signal according to the control signal. Transfer control means for switching the active state and the inactive state, transferring the input data to the outside in the active state, and stopping the transfer output of the input data to the outside in the inactive state; Address setting means for setting a data address for starting transfer output to the external device and a data address for ending transfer output for the external device, a first address detected by the address detecting device, and a second address set by the address setting device. And a comparison processing means for generating a control signal according to the comparison result. 3. When a pack conforming to the MPEG format is inputted, a pack address detecting means for detecting a pack address based on the pack header, and an active state and an inactive state are switched in accordance with a control signal, and an active state is set. In the case of, the input pack is transferred to the outside and output, and in the inactive state, the transfer control means to stop the input to the outside transfer output of the pack, and the output to the outside for each input pack The pack address setting means for setting the pack address of the pack to start and the pack address of the pack to end the transfer output to the outside, the first pack address detected by the pack address detecting means, and the pack address setting means. A comparison process for comparing the set second pack address and generating a control signal according to the comparison result. And a data processing device having means. 4. A sector address detecting means for detecting a sector address based on a sector header of an input sector, and an active state and an inactive state are switched in accordance with a control signal. To the external sector, and when it is inactive, transfer control means to stop the external sector output of the input sector, and for each input sector, the sector address of the sector to start the external sector output. , Sector address setting means for setting a sector address of a sector whose transfer output to the outside is to be finished, first sector address detected by the sector address detecting means, and second sector address set by the sector address setting means. And a comparison processing unit for generating a control signal according to the comparison result. 5. A sector address detecting means for detecting a sector address based on a sector header of a sector output from a CD signal processing circuit, and an active state and an inactive state are switched according to a control signal. From the sector address detecting means, transfer control means for transferring and outputting the sector output from the signal processing circuit to the external device and stopping transfer output of the sector output from the CD signal processing circuit to the external device when inactive. For the first register that stores the output sector address, and for each sector that is output from the CD signal processing circuit, the sector address of the sector where you want to start the transfer output to the external device, and the transfer output to the external device. Sector address setting means for setting the sector address of the sector you want to end and sector address setting means The second sector storing the sector address, the first sector address read from the first register, and the second sector address read from the second register, and the comparison result And a comparison processing means for generating a control signal according to the above. 6. A CD signal processing circuit for performing signal processing conforming to the CD format on a sector read from a disc on which data is recorded in the CD format, and a sector output from the CD signal processing circuit. , A sector address detecting means for detecting a sector address based on the sector header of the sector, and an active state and an inactive state are switched in accordance with a control signal. When the active state, the sector output from the CD signal processing circuit is used as an external device. Transfer control means for transferring and outputting to the external device of the sector output from the CD signal processing circuit in the inactive state, and each time a new sector address is output from the sector address detecting means, The first sector that stores the new sector address by discarding the sector address that was stored before For each sector output from the register and the CD signal processing circuit, set the sector address of the sector to start the transfer output to the external device and the sector address of the sector to end the transfer output to the external device. , Sector address setting means for outputting each sector address, and each time a new sector address is output from the sector address setting means, the sector address previously stored is discarded and the new sector address is stored. The second register, the first sector address read from the first register, and the second sector address read from the second register are compared, and a control signal is generated according to the comparison result. A data processing device comprising a comparison processing means. 7. The data processing device according to claim 4, wherein the comparison processing means outputs a control signal when the value of the first sector address matches the value of the second sector address. A data processing device for generating. 8. The data processing apparatus according to claim 4, wherein the comparison processing means outputs a control signal when the value of the first sector address exceeds the value of the second sector address. A data processing device for generating. 9. The data processing device according to claim 4, wherein the transfer control means transfers to the outside from the head of the sector output next from the CD signal processing circuit when the transfer control means becomes active. A data processing device which starts output and stops transfer output to the outside from the head of the sector output next from the CD signal processing circuit when it becomes inactive. 10. The data processing device according to claim 4, wherein the transfer control means, if the sector output from the CD signal processing circuit is in the middle when the transfer control means is in an active state, is externally used as it is. A data processing device which starts the transfer output to the CD and stops the transfer to the outside even if the sector being output from the CD signal processing circuit is in the middle when it becomes inactive.