JPH0820856B2 - Display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device that displays a charactor or the like by using a light bulb, a light emitting diode or the like.

BACKGROUND ART A CRT controller (hereinafter referred to as CRTC) as a display control means in a display device such as a character or a figure such as a character using a cathode ray tube (hereinafter referred to as CRT) as a display means.
However, it is widely used for simplifying the electrical configuration of the display device. CRTC is a device that sequentially addresses and reads the image memory that stores the data of the contents to be displayed on the screen in advance, outputs it to the display means, and displays it.Recently, not only CRT display but display character string In order to form the light emitting diode, a plurality of light emitting diodes, or point light sources such as light bulbs are also used in a display means arranged in a dot matrix.

FIG. 5 is a block diagram showing the electrical configuration of a display device according to the prior art using the CRTC12. From the main control unit 11 via the bus line 11, a random access memory (hereinafter,
Data regarding the contents to be displayed is input and stored in a RAM 13) at each address. The data stored by the RAM 13 is sequentially read by addressing from the CRTC 12 and input to the display means 14 via the line 14 to be displayed.

FIG. 6 is a diagram showing a control mode for displaying a character string for one line by using CRTC12. In FIG. 6, it consists of character areas a, b, c, d for 4 characters per line, and each character area a, b, c, d is composed of 8 × 8 dot pixels such as light emitting diodes or light bulbs. The display screen A is assumed to be the same, and therefore, in each of the character areas a, b, c, and d, in the vertical direction, from the uppermost first stage R0 to the lowermost eighth stage R7. An 8 × 8 dot line is constructed. Each stage R0 ~
Each line of R7 corresponds to a raster line in CRT display.

Assuming that each character area a, b, c, d has a light emitting element of 8 dots for each stage, one dot corresponds to one bit and one address is set with 8 bits. In this way, from the start address A00 for the character area a of the first row R0 to the eighth row R7
The final address A32 for the character area d of is set.

Referring also to FIG. 5, the CRTC 12 causes the display means 14 to display the character while sequentially addressing from the address A00 according to the control mode set in this way. However, CRTC12 is the final address of a stage R0.
After the display related to A03 is performed, instead of moving to the first address A04 of the next stage R1, after addressing the final address A04 of one stage R0, it always corresponds to the horizontal blanking period in the case of CRT display. Address A04 of one stage R0
Must be addressed by at least one address to move to the start address A04 of the next stage R1. A region e in FIG. 6 shows a dummy address region corresponding to such a horizontal blanking period.

Furthermore, CRTC12 is the address of the last character area of one line L0.
After specifying A32, do not move to the start address A32 of the next line L1 immediately, but only after specifying the address corresponding to the vertical blanking period in the case of CRT display.
Cannot move to the start address A32 of L1. Moreover, the address corresponding to at least one row is required as the address corresponding to the vertical blanking period. Row L1 in FIG. 6 shows a dummy address area which is a vertical blanking row for this purpose. At the same time, the memory area specified by the dummy address is set as blank data so as not to be displayed.

If the CRTC12 is used as a display control element in this way, as shown in FIG. 6, one row L0 to be displayed is displayed.
A dummy address area e corresponding to a horizontal blanking period equal to at least one of the following character areas, and a dummy address area corresponding to at least one line corresponding to a vertical blanking period.
L1 must be set. Therefore, an unfavorable result that the ratio of the non-display time (return line period) to the display time is large is brought about.

FIG. 7 is a time chart showing the above-mentioned operation according to the prior art. The period Tcs shows the display cycle for one line,
At the time t0, the first stage display is started first, and the time T0 until the time t1 indicates the display time of the first stage (first stage R0 in FIG. 6). The time Th from the time t1 to the time t2 is a time corresponding to the horizontal blanking period, and the time T1 from the time t2 to the time t3 is the display time of the second stage R1.

After that, the display and the horizontal blanking period are repeated in sequence. When the display of the final row ends at time tv0, the subsequent time Tv is the time corresponding to the vertical blanking period, and as described above, this time Tv
Is equal to the scanning time for one row. In other words, in the prior art using CRTC12, 50% or more of the display cycle is in the non-display period, so that sufficient brightness cannot be obtained and a display screen with a lot of flicker occurs.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the above-mentioned technical problems, to provide a display device which has a high luminosity and little flicker by improving the occupation ratio of the display period during one display cycle.

Configuration of the Invention The present invention is a display means 6 configured by arranging a large number of dot pixels in a matrix, and a memory 5, which are character areas a to d and a dummy address area e respectively corresponding to a plurality of characters. And the display line L0
The display row L0 and the vertical retrace line L1 are provided for each raster line and each vertical retrace line L1.
R0 to R7 are respectively provided, and the character areas a to d are provided at the respective stages R0 to R7.
A memory 5 for storing data of contents to be displayed in a plurality of bits corresponding to the respective pixels and having one address in R7; and a control means 4 for each stage R0 of the character line L0. The display times T0 and T1 corresponding to the character areas a to d and the horizontal blanking period Th corresponding to the dummy address area e are repeatedly addressed for each ~ R7, and the final row R7 of the display row L0 is specified. After the completion of the addressing of the dummy address area e, the vertical synchronizing signal Vsync is output, the vertical blanking line L1 is addressed in the vertical blanking period Tv of the vertical synchronizing signal Vsync, and the reset terminal RST is provided. By inputting the reset signal to the terminal RST, the control means 4 for designating the address of the character line L0 and the vertical synchronizing signal Vsync of the control means 4 are received and given to the reset terminal RST as a reset signal. Means l A display device including:

Further, according to the present invention, the display means 6 configured by arranging a large number of dot pixels in a matrix and the memory 5 are provided with character areas a to d and dummy address areas e respectively corresponding to a plurality of characters. , Display line L0
The display row L0 and the vertical retrace line L1 are provided for each raster line and each vertical retrace line L1.
R0 to R7 are respectively provided, and the character areas a to d are provided at the respective stages R0 to R7.
A memory 5 having a single address in R7 and storing data of contents to be displayed in a plurality of bits corresponding to the respective pixels, and a control means 4 for each stage R0 of the character line L0 Display time T0, T1 corresponding to each character area a to d and horizontal blanking period Th corresponding to the dummy address area e are repeatedly addressed for each ~ R7, and at the same time, in the final row R7 of the display row L0. After the completion of the addressing of the dummy address area e, the vertical synchronizing signal Vsync is output, the vertical blanking line L1 is addressed in the vertical blanking period Tv of the vertical synchronizing signal Vsync, and the reset terminal RST is provided. By inputting the reset signal to the terminal RST, the control means 4 for specifying the address of the character line L0, the means for detecting the leading address by the address specification of the vertical retrace line L1 of the control means 4, and Of detection means And a means l3 for generating a reset signal Vrs in response to the output and supplying the reset signal Vrs to the reset terminal RST.

Embodiment FIG. 1 is a block diagram showing the electrical construction of an embodiment of the present invention, and FIG. 2 is a time chart showing its operation. A main control unit 1 including a read-only memory (hereinafter, referred to as ROM) 2 and a central information processing device (hereinafter, referred to as CPU) 3 and the like is a random memory that stores contents to be displayed on the display unit 6. Data to be displayed is written to an access memory (hereinafter referred to as RAM) 5 via a bus line 1, while the addresses of the RAM 5 are sequentially addressed via a bus line 12 to
When the contents stored in the RAM5 for the screen have been addressed, the control means CRTC4 is initialized.

It should be noted that the reset signal is input to the reset terminal RST of the CRTC4 via the line 13 in the first embodiment shown in the drawing. According to the control mode shown in FIG. 7, CRTC4 performs addressing sequentially from the start address A00, while performing all addressing related to the character area at the final address A31, and the display for one line is completed. When addressing of the address A32 of the dummy address area e is completed and the period corresponding to the vertical blanking period described in the section of the prior art is entered, the CRTC4 outputs the vertical synchronizing signal Vsync from inside thereof.

The display time is shown in FIG. 2 (1). At time t0, the start address of one row, for example, the row L0 in FIG. 7,
For example, address A00 is addressed, and at time T0 until time t1, the display for the first stage R0 of row L0 is performed.

Next, the time Th from the time t1 to the time t2 corresponds to the horizontal blanking period, during which the CRTC4 addresses the dummy address A04, for example. Furthermore, time T1 from time t2 to time t3
Then, the display regarding the second stage R1 of the row L0 is performed.

In the same manner, addressing and display for each stage are sequentially performed, and at time t15, the display for the final stage R7 ends and the display for row L0 ends. At this time CRTC
4 detects that its addressing is completed for one row, and outputs the vertical synchronization signal Vsync shown in FIG. 2 (2) at time t16.

The vertical sync signal Vsync is the reset input pin RST of CRTC4.
CRTC4 is reset because it is added as a reset signal. Therefore, the CRTC4 eliminates the need for performing the dummy addressing corresponding to the vertical blanking period as described in the prior art, and immediately performs the addressing for the second row at time t17. Therefore, during the display cycle Tcs for one row, the non-display time is only a minute time Th corresponding to the horizontal blanking period in the horizontal direction, and the ratio of the display time per cycle reaches 80%. As a result, a significant improvement in brightness is realized. As a result of greatly reducing the non-display time, the flicker as in the prior art is eliminated, and a display device having an excellent display effect can be implemented.

FIG. 3 is a block diagram showing the electrical construction of another embodiment of the present invention, and FIG. 4 is a time chart showing its operation. FIG. 3 is similar to FIG. 1, and the corresponding parts bear the same reference numerals. What should be noted is the creation of the reset signal applied to the reset terminal RST of CRTC4.
While the illustrated embodiment uses the vertical synchronizing signal Vsync at the rising edge of the vertical blanking period as the reset signal, in the present embodiment, the address (address A32 in FIG. 7) corresponding to the final horizontal blanking period is used. The start address immediately after entering the vertical blanking period after the end of specification is detected, and the reset signal Vrs is created by this, and the CRT is sent via line l3.
This is because it is applied to the reset terminal RST of C4.

Fig. 4 (1) shows the display time. After time t0, CRTC4
The address is designated from the top address by, and the display for each stage is performed at time T0, T1, ....
At time tn when the display cycle Tcs of one row has elapsed, the setting of the address (address A32 in FIG. 6) corresponding to the final horizontal blanking period ends. Then, as shown in FIG. 4 (2), at time tn, the start address of the vertical blanking period is
Although specified by CRTC4, this address number is the highest among the address numbers up to that point, so that the reset signal Vrs is output and CRTC4 is reset. In this case as well, the ratio of the non-display period to the display period is significantly reduced, so that it is possible to implement a display device having an excellent display effect as in the previous embodiment.

In the above-described embodiment, the character that can be displayed is described as four characters, and one character area has an 8 × 8 bit structure, but of course the present invention is not limited to this. Further, in this embodiment, as the display means, a display means in which point light sources such as light emitting diodes are arranged in a matrix is exemplified.

Effect According to the present invention, the display means is configured by arranging a large number of dot pixels in a matrix, and the memory 5 displays the display row L0.
In the state in which a plurality of character areas a to d and a dummy address area e are provided in the vertical blanking line L1 and the reset signal is not input to the reset terminal RST of the control means 4, the display line L0 is addressed. Later, the vertical retrace line L1 is configured to be addressed, and when the memory 5 is used to control the display means, the vertical synchronizing signal Vsync of the control means 4 is reset. To the reset terminal RST or detect the start address by addressing the vertical blanking line L1 to create the reset signal Vrs and apply it to the reset terminal RST as a reset signal. The display row L0 can be addressed again without addressing L1 for a relatively long time.
As a result, the non-display period with respect to the display period within the period of the display cycle for displaying one screen, in other words, the non-lighting time is significantly reduced, and most of the time in the cycle period can be used as the display period. . Therefore, it is possible to realize a display device which has a higher brightness than the prior art and has an improved display effect with less flicker.

[Brief description of drawings]

FIG. 1 is a block diagram showing the electrical construction of one embodiment of the present invention, FIG. 2 is a time chart showing its operation, and FIG. 3 is a block diagram showing the electrical construction of another embodiment of the present invention. FIG. 4 is a time chart showing the operation thereof, FIG. 5 is a block diagram showing an electric configuration of the prior art, FIG. 6 is a view showing a control mode, and FIG. 7 is a time chart showing the operation of the prior art. . 1, 11 ... Main control unit, 2 ... Read only memory, 3 ... Central information processing unit (CPU), 4, 12 ... Cathode ray tube display device control means (CRTC), 5, 13 ... Random access memory, 6, 14 ... Display means, A ... Display screen area

Claims (2)

[Claims] 1. A display means 6 comprising a large number of dot pixels arranged in a matrix, and a memory 5 having character areas ad corresponding to a plurality of characters and a dummy address area e. , The display line L0 and the vertical retrace line L1 are provided for each display line L0 and for each vertical retrace line L1.
To R7 respectively, and the character areas a to d are arranged in the respective rows R0 to R7.
A memory 5 for storing data of contents to be displayed in a plurality of bits each having one address and corresponding to each of the pixels, and a control means 4 for each stage R0 to R0 of the character line L0. For each R7, the display times T0 and T1 corresponding to the respective character areas a to d and the horizontal blanking period Th corresponding to the dummy address area e are repeatedly addressed to specify the address, and the dummy data in the final row R7 of the display row L0. After the addressing of the address area e is completed, the vertical synchronizing signal Vsync is output, the vertical blanking line L1 is addressed in the vertical blanking period Tv of the vertical synchronizing signal Vsync, and the reset terminal RST is provided. By inputting the reset signal to RST, the control means 4 for specifying the address of the character line L0, and the means for receiving the vertical synchronizing signal Vsync of the control means 4 and giving it as the reset signal to the reset terminal RST l3 Display device which comprises a. 2. A display means 6 composed of a large number of dot pixels arranged in a matrix, and a memory 5 having character areas a to d and a dummy address area e respectively corresponding to a plurality of characters. , The display line L0 and the vertical retrace line L1 are provided for each display line L0 and for each vertical retrace line L1.
To R7 respectively, and the character areas a to d are arranged in the respective rows R0 to R7.
A memory 5 for storing data of contents to be displayed in a plurality of bits each having one address and corresponding to each of the pixels, and a control means 4 for each stage R0 to R0 of the character line L0. For each R7, the display times T0 and T1 corresponding to the respective character areas a to d and the horizontal blanking period Th corresponding to the dummy address area e are repeatedly addressed and designated, and the dummy in the final row R7 of the display row L0 is performed. After the addressing of the address area e is completed, the vertical synchronizing signal Vsync is output, the vertical blanking line L1 is addressed in the vertical blanking period Tv of the vertical synchronizing signal Vsync, and the reset terminal RST is provided. By inputting the reset signal to RST, the control means 4 for addressing the character line L0, the means for detecting the start address by the addressing of the vertical retrace line L1 of the control means 4, and the detection thereof Of means In response to the force, to create a reset signal Vrs, display device characterized by comprising a means l3 to be given to the reset terminal RST.