JPH08204231A - Emission diode array and fabrication thereof - Google Patents
Emission diode array and fabrication thereofInfo
- Publication number
- JPH08204231A JPH08204231A JP942095A JP942095A JPH08204231A JP H08204231 A JPH08204231 A JP H08204231A JP 942095 A JP942095 A JP 942095A JP 942095 A JP942095 A JP 942095A JP H08204231 A JPH08204231 A JP H08204231A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- emitting diode
- diffusion layer
- light emitting
- diode array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、発光ダイオードアレイ
及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、このような発光ダイオードアレイ
としては、以下に示すようなものがあった。図５はかか
る従来の発光ダイオードアレイの平面図、図６はその発
光ダイオードアレイの断面図であり、図６（ａ）は図５
のａ−ａ線断面図、図６（ｂ）は図５のｂ−ｂ線断面図
である。2. Description of the Related Art Heretofore, there have been the following types of light emitting diode arrays. FIG. 5 is a plan view of such a conventional light emitting diode array, FIG. 6 is a sectional view of the light emitting diode array, and FIG.
6 is a sectional view taken along line aa of FIG. 6 and FIG. 6B is a sectional view taken along line bb of FIG.
【０００３】これらの図に示すように、発光ダイオード
アレイは、選択拡散により基板５４上にアレイ状に形成
したｐ−ｎ接合とｐ側電極５２などから構成される。選
択拡散により形成するＰ型拡散層５３の深さ（接合深
さ）は通常均一な深さである。一般的に発光強度は接合
深さに依存するので光量が最大となるような深さに設定
している。なお、図において、５１は拡散防止膜、５５
はｎ側電極である。As shown in these figures, the light emitting diode array is composed of a p-n junction and a p-side electrode 52 which are formed in an array on a substrate 54 by selective diffusion. The depth (junction depth) of the P-type diffusion layer 53 formed by selective diffusion is usually a uniform depth. In general, the emission intensity depends on the junction depth, so the depth is set so that the amount of light is maximized. In the figure, 51 is a diffusion prevention film, and 55
Is an n-side electrode.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記し
た従来のＬＥＤアレイでは、順方向に電圧を印加した場
合、電極直下に電流の多くが供給され電極直下の接合か
らの発光強度が他の領域に比べて強くなる。しかし、電
極直下の接合からの発光は電極により遮光されるので、
外部に取り出す光量には寄与しない。However, in the above-mentioned conventional LED array, when a voltage is applied in the forward direction, a large amount of current is supplied directly below the electrodes, and the emission intensity from the junction immediately below the electrodes is in another region. It will be stronger than that. However, since the light emitted from the junction directly below the electrode is blocked by the electrode,
It does not contribute to the amount of light extracted to the outside.
【０００５】また、電極直下に電流が集中する場合に
は、欠陥成長の要因となり寿命が短くなる。本発明は、
上記問題点を除去し、発光ダイオードアレイの発光効率
と寿命の向上を図り得る発光ダイオードアレイ及びその
製造方法を提供することを目的とする。If current concentrates just below the electrode, it causes defect growth and shortens the life. The present invention
An object of the present invention is to provide a light emitting diode array and a method for manufacturing the same, which can eliminate the above problems and improve the light emitting efficiency and life of the light emitting diode array.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （１）ｎ型化合物半導体基板にＺｎを選択的に拡散して
なる発光ダイオードアレイにおいて、拡散領域内の一部
に形成される接合深さの浅い拡散層と、この接合深さの
浅い拡散層の周囲に形成される接合深さの深い拡散層
と、前記接合深さの浅い拡散層にコンタクトをとるｐ側
電極とを設けるようにしたものである。In order to achieve the above object, the present invention provides: (1) In a light emitting diode array in which Zn is selectively diffused in an n-type compound semiconductor substrate, a part of the diffusion region is provided. A diffusion layer having a shallow junction depth, a diffusion layer having a deep junction depth formed around the diffusion layer having a shallow junction depth, and a p-side contacting the diffusion layer having a shallow junction depth. An electrode is provided.
【０００７】（２）ｎ型化合物半導体基板にＺｎを選択
的に拡散してなる発光ダイオードアレイの製造方法にお
いて、拡散開口部内に深さの異なる接合領域を形成する
工程と、接合深さの浅い領域へｐ側電極のコンタクトを
とる工程とを施すようにしたものである。 （３）ｎ型化合物半導体基板にＺｎを選択的に拡散して
なる発光ダイオードアレイの製造方法において、拡散開
口部内の中央部に張り出す拡散防止膜を形成し、横方向
拡散による拡散層を形成する工程と、前記拡散防止膜を
除去し、この拡散防止膜が除去された領域にｐ側電極の
コンタクトをとる工程とを施すようにしたものである。(2) In a method of manufacturing a light emitting diode array in which Zn is selectively diffused in an n-type compound semiconductor substrate, a step of forming junction regions having different depths in a diffusion opening and a shallow junction depth. The step of making contact with the p-side electrode to the region is performed. (3) In a method of manufacturing a light-emitting diode array in which Zn is selectively diffused in an n-type compound semiconductor substrate, a diffusion prevention film protruding to a central portion in a diffusion opening is formed and a diffusion layer is formed by lateral diffusion. And the step of removing the diffusion barrier film and making contact with the p-side electrode in the region where the diffusion barrier film is removed.
【０００８】[0008]
（Ａ）上記（１）記載の発光ダイオードアレイによれ
ば、拡散領域内の一部に形成される接合深さの浅い拡散
層と、この接合深さの浅い拡散層の周囲に形成される接
合深さの深い拡散層と、前記接合深さの浅い拡散層にコ
ンタクトをとるｐ側電極とを設けるようにしたので、発
光ダイオードアレイの発光効率と寿命の向上を図ること
ができる。(A) According to the light-emitting diode array described in (1) above, a diffusion layer having a shallow junction depth formed in a part of the diffusion region and a junction formed around the diffusion layer having a shallow junction depth. Since the diffusion layer having a deep depth and the p-side electrode that makes contact with the diffusion layer having a shallow junction depth are provided, it is possible to improve the luminous efficiency and the life of the light emitting diode array.
【０００９】（Ｂ）上記（２）記載の発光ダイオードア
レイの製造方法によれば、相対的にシート抵抗の高い、
浅い拡散領域にｐ側電極のコンタクトを形成するように
したので、光が遮光される電極直下の接合よりも周囲の
接合領域へ電流が流れ、効率よく光を取り出すことがで
きる。また、電極直下への電流集中も緩和され、寿命の
向上を図ることができる。(B) According to the method for manufacturing a light emitting diode array described in (2) above, the sheet resistance is relatively high.
Since the contact of the p-side electrode is formed in the shallow diffusion region, a current flows to the surrounding junction region rather than the junction immediately below the electrode where light is shielded, and light can be efficiently extracted. In addition, current concentration under the electrode is also alleviated, and the life can be improved.
【００１０】（Ｃ）上記（３）記載の発光ダイオードア
レイの製造方法によれば、横方向拡散により拡散開口部
内に形成した相対的にＺｎ濃度の低い部分をｐ側電極コ
ンタクト領域とするので、発光効率の向上と寿命の向上
を図ることができる。(C) According to the method of manufacturing a light emitting diode array described in (3) above, the portion having a relatively low Zn concentration formed in the diffusion opening by lateral diffusion is used as the p-side electrode contact region. It is possible to improve the luminous efficiency and the life.
【００１１】[0011]
【実施例】本発明の実施例について図を参照しながら説
明する。図１は本発明の第１実施例を示す発光ダイオー
ドアレイの平面図、図２はその発光ダイオードアレイの
断面図である。これらの図に示すように、ｐ側電極１４
直下の接合深さ（ｘｊ）1 の浅い拡散層１３ｂと、その
周囲の接合深さ（ｘｊ）2 の深い拡散層１３ａとからな
るＺｎ拡散層１３を有している。Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a light emitting diode array showing a first embodiment of the present invention, and FIG. 2 is a sectional view of the light emitting diode array. As shown in these figures, the p-side electrode 14
The Zn diffusion layer 13 has a shallow diffusion layer 13b having a junction depth (xj) 1 immediately below and a deep diffusion layer 13a having a junction depth (xj) 2 surrounding the shallow diffusion layer 13b.
【００１２】例えば、（Ｘｊ)1は略１μｍ、（Ｘｊ)2は
略５μｍとする。後で述べるように気相拡散によりＺｎ
低濃度拡散した場合、（Ｘｊ)2が略５μｍ程度の均一な
拡散深さのＬＥＤを作製した場合、発光量は最大とな
り、（Ｘｊ)1略１μｍ程度の拡散深さでは約１／１０の
発光量となることを実験的に確認している。このような
構造にすることにより、ｐ側電極１４直下に比べ、周辺
部位の抵抗が低くなるので、順方向に電圧を印加した場
合、ｐ側電極１４より供給する電流はｐ側電極１４直下
の領域よりむしろｐ側電極１４周辺の領域を流れ易くな
る。すなわち、ｐ側電極１４により遮光されない領域の
接合へ効率よくキャリアが注入されて効率よく光を取り
出すことができる。逆に、ｐ側電極１４直下の接合へは
供給される電流が減少し、外に取り出せない光量は減少
する。一方、ｐ側電極１４直下に電流が集中することも
ないので、寿命の観点からも性能の向上を図ることがで
きる。なお、１１はｎ型ＧａＡｓ1-X ＰX エピタキシャ
ル基板、１２は拡散防止膜（Ａｌ2 Ｏ3 膜）、１５はｎ
側電極としてのＡｕ合金電極である。For example, (Xj) 1 is approximately 1 μm, and (Xj) 2 is approximately 5 μm. As described below, Zn
In the case of low-concentration diffusion, when an LED having a uniform diffusion depth of (Xj) 2 of about 5 μm is produced, the maximum light emission amount is obtained, and about 1/10 of the diffusion depth of (Xj) 1 of about 1 μm. It has been experimentally confirmed that the light emission amount is obtained. With such a structure, the resistance of the peripheral portion is lower than that under the p-side electrode 14, so that when a voltage is applied in the forward direction, the current supplied from the p-side electrode 14 is below the p-side electrode 14. It becomes easier to flow in the region around the p-side electrode 14 rather than the region. That is, carriers can be efficiently injected into the junction in the region that is not shielded by the p-side electrode 14, and light can be extracted efficiently. On the contrary, the current supplied to the junction just below the p-side electrode 14 decreases, and the amount of light that cannot be extracted to the outside decreases. On the other hand, since the current does not concentrate right under the p-side electrode 14, the performance can be improved from the viewpoint of life. Incidentally, 11 is an n-type GaAs 1-X P X epitaxial substrate, 12 is a diffusion prevention film (Al 2 O 3 film), and 15 is n.
It is an Au alloy electrode as a side electrode.
【００１３】以下、本発明の第１実施例を示す発光ダイ
オードアレイの製造方法について説明する。図３はその
発光ダイオード（発光ダイオードアレイの発光部）の概
略平面図、図４はその発光ダイオードの製造工程断面図
である。 （１）まず、図４（ａ）に示すように、ｎ型化合物半導
体基板、例えばｎ型ＧａＡｓ1-X ＰX エピタキシャル基
板２１にＺｎ選択拡散のための拡散防止膜２２、例えば
Ａｌ2 Ｏ3 膜を２０００Å膜付けし、アレイ状に拡散開
口部２２ａを形成する。その次に電極パターンにあわせ
て、拡散制御膜２３、例えばＡｌ2 Ｏ3膜を１００Å膜
付けし、ホトリソグラフィーによりパターニングする。
この時、横方向拡散距離を考慮して拡散制御膜のパター
ン形成を設定する。Hereinafter, a method for manufacturing the light emitting diode array showing the first embodiment of the present invention will be described. FIG. 3 is a schematic plan view of the light emitting diode (light emitting portion of the light emitting diode array), and FIG. 4 is a sectional view of the manufacturing process of the light emitting diode. (1) First, as shown in FIG. 4 (a), an n-type compound semiconductor substrate, for example, an n-type GaAs 1-X P X epitaxial substrate 21, is provided with a diffusion barrier film 22 for selective diffusion of Zn, for example Al 2 O 3. A 2000Å film is attached to form diffusion openings 22a in an array. Then, a diffusion control film 23, for example, an Al 2 O 3 film having a thickness of 100 Å is formed according to the electrode pattern and patterned by photolithography.
At this time, the pattern formation of the diffusion control film is set in consideration of the lateral diffusion distance.
【００１４】（２）次に、図４（ｂ）に示すように、気
相拡散において基板表面保護のための拡散保護膜２４、
例えばＰＳＧ膜１５０Åを膜付けし、Ｚｎを含む化合物
あるいは混合物をガス源とし、封管法によりＺｎを拡散
する。例えば、７５０℃、６時間のアニールにより、拡
散開口部２２ａの拡散深さとして約５μｍ、拡散制御膜
２３下の領域で約１μｍの拡散深さの接合が形成され
る。この拡散工程ではＺｎ表面濃度に概ね次のような制
限を加えることが望ましい。(2) Next, as shown in FIG. 4B, a diffusion protection film 24 for protecting the substrate surface in vapor phase diffusion,
For example, a PSG film 150Å is applied as a film, and a Zn-containing compound or mixture is used as a gas source to diffuse Zn by the sealed tube method. For example, by annealing at 750 ° C. for 6 hours, a junction having a diffusion depth of about 5 μm and a diffusion depth of about 1 μm in the region under the diffusion control film 23 is formed. In this diffusion step, it is desirable to apply the following restrictions to the Zn surface concentration.
【００１５】接合深さの浅い拡散層２５ｂで５×１０18
ｃｍ-3＜ＮS ＜１×１０19ｃｍ-3が望ましい。これは、
電極のオーミックコンタクトが良好にとれ、かつ電極直
下の領域の抵抗が拡散開口部２２ａ内のその他の領域の
抵抗より大きくなるようにするためである。例えば、こ
のような値になるように接合深さの浅い拡散層２５ｂを
形成すれば周囲の接合深さの深い拡散層２５ａの抵抗に
比べ１０倍以上のシート抵抗となり、電極より供給され
る大部分の電流は電極直下以外の接合領域へ流れるよう
にすることができる。The diffusion layer 25b having a shallow junction depth is 5 × 10 18.
It is desirable that cm -3 <N S <1 × 10 19 cm -3 . this is,
This is because the ohmic contact of the electrode can be well achieved and the resistance of the region immediately below the electrode is higher than the resistance of the other regions in the diffusion opening 22a. For example, if the diffusion layer 25b having a shallow junction depth is formed so as to have such a value, the sheet resistance becomes 10 times or more the resistance of the diffusion layer 25a having a deep junction depth in the surroundings, and the sheet resistance supplied from the electrode is large. The current of a part can be made to flow to a junction region other than directly below the electrode.
【００１６】（３）次に、図４（ｃ）に示すように、拡
散制御膜２３と拡散保護膜２４を除去した後、接合深さ
の浅い拡散層２５ｂにｐ側電極であるＡｌ電極２６を形
成する。また、基板裏面は研磨後、ｎ側電極であるＡｕ
合金電極２７を形成して完成する。上記実施例では拡散
制御膜２３により形成した接合深さの浅い拡散層２５ｂ
にＡｌ電極２６のコンタクトをとる例を述べたが、電極
形状によっては横方向の拡散を利用することも可能であ
る。(3) Next, as shown in FIG. 4C, after the diffusion control film 23 and the diffusion protection film 24 are removed, the Al electrode 26 which is a p-side electrode is formed on the diffusion layer 25b having a shallow junction depth. To form. Also, after polishing the back surface of the substrate, Au which is an n-side electrode is polished.
The alloy electrode 27 is formed and completed. In the above embodiment, the diffusion layer 25b formed by the diffusion control film 23 and having a shallow junction depth is formed.
Although the example of making the contact with the Al electrode 26 has been described above, lateral diffusion may be used depending on the shape of the electrode.
【００１７】次に、本発明の第２実施例について説明す
る。図７は本発明の第２実施例を示す発光ダイオード
（発光ダイオードアレイの発光部）の第１工程の概略平
面図、図８はその発光ダイオードの第１製造工程の断面
図であり、図８（ａ）は図７のａ−ａ線断面図、図８
（ｂ）は図７のｂ−ｂ線断面図、図９はその発光ダイオ
ードの第２製造工程の説明図であり、図９（ａ）は図７
のａ−ａ線に沿った断面図、図９（ａ）は図７のｂ−ｂ
線に沿った断面図、図１０はその発光ダイオードの第３
製造工程の説明図であり、図１０（ａ）は図７のｂ−ｂ
線に沿った断面図、図１０（ｂ）は図１０（ａ）の平面
図である。Next, a second embodiment of the present invention will be described. FIG. 7 is a schematic plan view of a first step of a light emitting diode (light emitting portion of a light emitting diode array) showing a second embodiment of the present invention, and FIG. 8 is a sectional view of a first manufacturing step of the light emitting diode. 8A is a sectional view taken along the line aa of FIG. 7, FIG.
7B is a sectional view taken along line bb of FIG. 7, FIG. 9 is an explanatory view of the second manufacturing process of the light emitting diode, and FIG.
9 is a cross-sectional view taken along the line aa of FIG.
FIG. 10 is a cross-sectional view taken along the line, FIG.
It is explanatory drawing of a manufacturing process, FIG.10 (a) is bb of FIG.
A cross-sectional view taken along the line, and FIG. 10B is a plan view of FIG.
【００１８】以下、その発光ダイオードの製造方法を説
明する。 （１）図８（ａ）及び図８（ｂ）に示すように、ｎ型Ｇ
ａＡｓ1-X ＰX エピタキシャル基板３１へ拡散防止膜
（Ａｌ2 Ｏ3 膜）３２を２０００Å膜付けし、拡散開口
部３２ａ及び電極パターン形状にあわせて拡散防止膜で
あるＡｌ2 Ｏ3 膜パターン（張り出し部）３３をホトリ
ソグラフィーにより形成する。この場合は、電極幅が拡
散深さの２倍よりも幅の狭い電極が望ましい。The method of manufacturing the light emitting diode will be described below. (1) As shown in FIGS. 8A and 8B, n-type G
A diffusion prevention film (Al 2 O 3 film) 32 is formed on the aAs 1-X P X epitaxial substrate 31 to a thickness of 2000 Å, and an Al 2 O 3 film pattern ( The overhang portion 33 is formed by photolithography. In this case, it is desirable that the electrode width is narrower than twice the diffusion depth.
【００１９】（２）次に、図９（ａ）及び図９（ｂ）に
示すように、拡散保護膜３４を膜付けした後、封管法に
よる気相拡散によりＺｎ拡散領域３５を形成する。 （３）次に、図１０（ａ）及び図１０（ｂ）に示すよう
に、拡散保護膜３４除去後、前工程で拡散開口部３２ａ
内の一部領域に、横方向拡散により形成した部分にあわ
せてｐ側電極であるＡｌ電極３６のコンタクトを形成す
る。後の工程は第１実施例と同様なので省略する。この
場合、Ａｌ電極３６のコンタクト幅は前記横方向拡散に
より形成したＡｌ2 Ｏ3 膜パターン（張り出し部）３３
の幅より狭いことが望ましい。(2) Next, as shown in FIGS. 9A and 9B, after the diffusion protection film 34 is applied, the Zn diffusion region 35 is formed by vapor phase diffusion by the sealed tube method. . (3) Next, as shown in FIGS. 10A and 10B, after the diffusion protection film 34 is removed, the diffusion opening 32a is formed in the previous step.
A contact of the Al electrode 36, which is a p-side electrode, is formed in a partial region in the inside in accordance with the portion formed by the lateral diffusion. The subsequent steps are the same as those in the first embodiment and will not be described. In this case, the contact width of the Al electrode 36 is the Al 2 O 3 film pattern (overhanging portion) 33 formed by the lateral diffusion.
It is desirable that the width is smaller than the width.
【００２０】以上、第１及び第２実施例では気相拡散に
よるＺｎ拡散の例を述べたが、固相拡散によるＺｎ拡散
でもよい。図１１及び図１２はその固相拡散によるＺｎ
拡散の説明図である。例えば、図１１に示すように、拡
散源膜（ＺｎドープＳｉＯ2 膜）４２の下にＳｉＯ2 膜
４１を設け、ｎ型化合物半導体基板４０にＺｎ拡散す
る。なお、４３はアニールキャップである。あるいは、
図１２に示すように、Ｚｎドープ量の低い拡散源膜（Ｓ
ｉＯ2 ）４６を部分的に用いるような例が可能である。
なお、４７はＺｎドープ量の高い拡散源膜（Ｓｉ
Ｏ2 ）、４８はアニールキャップである。ただし、この
場合でも電極下のｎ型化合物半導体基板４５表面のＺｎ
濃度が周囲のＺｎ濃度より低くなるように条件を選択す
る必要がある。In the first and second embodiments, the example of Zn diffusion by vapor phase diffusion has been described above, but Zn diffusion by solid phase diffusion may be used. 11 and 12 show Zn by the solid phase diffusion.
It is an explanatory view of diffusion. For example, as shown in FIG. 11, a SiO 2 film 41 is provided under a diffusion source film (Zn-doped SiO 2 film) 42, and Zn is diffused into the n-type compound semiconductor substrate 40. In addition, 43 is an annealing cap. Alternatively,
As shown in FIG. 12, a diffusion source film (S
An example is possible in which iO 2 ) 46 is partially used.
In addition, 47 is a diffusion source film (Si
O 2 ), 48 are annealing caps. However, even in this case, Zn on the surface of the n-type compound semiconductor substrate 45 under the electrode
It is necessary to select the conditions so that the concentration becomes lower than the surrounding Zn concentration.
【００２１】また、上記実施例では電極と基板間に一層
のＡｌ2 Ｏ3 膜が存在する例について述べたが異種材料
の膜を積層して層間絶縁膜としても効果は変わらないこ
とは明らかである。また、ｎ型ＧａＡｓ1-X ＰX 基板以
外のＧａＡｓ、ＧａＰ、ＡｌＧａＡｓ等の化合物半導体
基板へＺｎを拡散して製造するＬＥＤアレイに対して
も、本発明が適用できることも明らかである。Further, in the above embodiment, an example in which a single layer of Al 2 O 3 film is present between the electrode and the substrate has been described, but it is clear that the effect does not change even if films of different materials are laminated to form an interlayer insulating film. is there. It is also apparent that the present invention can be applied to an LED array manufactured by diffusing Zn into a compound semiconductor substrate such as GaAs, GaP, AlGaAs other than the n-type GaAs 1-X P X substrate.
【００２２】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.
【００２３】[0023]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）請求項１記載の発明によれば、拡散領域内の一部
に形成される接合深さの浅い拡散層と、この接合深さの
浅い拡散層の周囲に形成される接合深さの深い拡散層
と、前記接合深さの浅い拡散層にコンタクトをとるｐ側
電極とを設けるようにしたので、発光ダイオードアレイ
の発光効率と寿命の向上を図ることができる。As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the first aspect of the invention, a diffusion layer having a shallow junction depth formed in a part of the diffusion region and a junction depth formed around the diffusion layer having a shallow junction depth are formed. Since the deep diffusion layer and the p-side electrode that makes contact with the diffusion layer having a shallow junction depth are provided, the light emitting efficiency and the life of the light emitting diode array can be improved.
【００２４】（２）請求項２記載の発明によれば、相対
的にシート抵抗の高い、浅い拡散領域に電極のコンタク
トを形成するようにしたので、光が遮光される電極直下
の接合よりも周囲の接合領域へ電流が流れ、効率よく光
を取り出すことができる。また、電極直下への電流集中
も緩和され、寿命の向上を図ることができる。 （３）請求項３記載の発明によれば、横方向拡散により
拡散開口部内に形成した相対的にＺｎ濃度の低い部分を
電極コンタクト領域とするので、発光効率の向上と寿命
の向上を図ることができる。(2) According to the second aspect of the invention, since the contact of the electrode is formed in a shallow diffusion region having a relatively high sheet resistance, the contact is formed immediately below the electrode where light is shielded. A current flows to the surrounding junction region, and light can be extracted efficiently. In addition, current concentration under the electrode is also alleviated, and the life can be improved. (3) According to the third aspect of the invention, since the portion having a relatively low Zn concentration formed in the diffusion opening by lateral diffusion is used as the electrode contact region, it is possible to improve the luminous efficiency and the life. You can
【図１】本発明の第１実施例を示す発光ダイオードアレ
イの平面図である。FIG. 1 is a plan view of a light emitting diode array showing a first embodiment of the present invention.
【図２】本発明の第１実施例を示す発光ダイオードアレ
イの断面図である。FIG. 2 is a sectional view of a light emitting diode array showing a first embodiment of the present invention.
【図３】本発明の第１実施例を示す発光ダイオード（発
光ダイオードアレイの発光部）の概略平面図である。FIG. 3 is a schematic plan view of a light emitting diode (light emitting portion of a light emitting diode array) showing a first embodiment of the present invention.
【図４】本発明の第１実施例を示す発光ダイオードの製
造工程断面図である。FIG. 4 is a sectional view of a manufacturing process of a light emitting diode showing the first embodiment of the present invention.
【図５】従来の発光ダイオードアレイの平面図である。FIG. 5 is a plan view of a conventional light emitting diode array.
【図６】従来の発光ダイオードアレイの断面図である。FIG. 6 is a cross-sectional view of a conventional light emitting diode array.
【図７】本発明の第２実施例を示す発光ダイオード（発
光ダイオードアレイの発光部）の第１工程の概略平面図
である。FIG. 7 is a schematic plan view of a first step of a light emitting diode (light emitting portion of a light emitting diode array) showing a second embodiment of the present invention.
【図８】本発明の第２実施例を示す発光ダイオードの第
１製造工程の断面図である。FIG. 8 is a sectional view of a first manufacturing process of a light emitting diode showing a second embodiment of the present invention.
【図９】本発明の第２実施例を示す発光ダイオードの第
２製造工程の説明図である。FIG. 9 is an explanatory view of a second manufacturing process of the light emitting diode showing the second embodiment of the present invention.
【図１０】本発明の第２実施例を示す発光ダイオードの
第３製造工程の説明図である。FIG. 10 is an explanatory diagram of a third manufacturing process of the light emitting diode showing the second embodiment of the present invention.
【図１１】本発明の第３実施例を示す発光ダイオードの
拡散層の形成の説明図である。FIG. 11 is an explanatory view of forming a diffusion layer of a light emitting diode showing a third embodiment of the present invention.
【図１２】本発明の第４実施例を示す発光ダイオードの
拡散層の形成の説明図である。FIG. 12 is an explanatory view of forming a diffusion layer of a light emitting diode showing a fourth embodiment of the present invention.
１１，２１，３１ ｎ型ＧａＡｓ1-X ＰX エピタキシ
ャル基板 １２，２２，３２ 拡散防止膜（Ａｌ2 Ｏ3 膜） １３，３５ Ｚｎ拡散領域 １３ａ，２５ａ 接合深さの深い拡散層 １３ｂ，２５ｂ 接合深さの浅い拡散層 １４ ｐ側電極（Ａｌ電極） １５，２７ ｎ側電極（Ａｕ合金電極） ２２ａ，３２ａ 拡散開口部 ２３ 拡散制御膜（Ａｌ2 Ｏ3 膜） ２４，３４ 拡散保護膜（ＰＳＧ膜） ２６，３６ Ａｌ電極 ３３ Ａｌ2 Ｏ3 膜パターン（張り出し部） ４０，４５ ｎ型化合物半導体基板 ４１ ＳｉＯ2 膜 ４２ 拡散源膜（ＺｎドープＳｉＯ2 膜） ４３，４８ アニールキャップ ４６ Ｚｎドープ量の低い拡散源膜（ＳｉＯ2 ） ４７ Ｚｎドープ量の高い拡散源膜（ＳｉＯ2 ）11, 21, 31 n-type GaAs 1-X P X epitaxial substrate 12, 22, 32 diffusion prevention film (Al 2 O 3 film) 13, 35 Zn diffusion region 13a, 25a deep diffusion layer 13b, 25b junction Diffusion layer with shallow depth 14 P-side electrode (Al electrode) 15,27 N-side electrode (Au alloy electrode) 22a, 32a Diffusion opening 23 Diffusion control film (Al 2 O 3 film) 24, 34 Diffusion protection film (PSG) Film) 26,36 Al electrode 33 Al 2 O 3 film pattern (overhanging part) 40,45 n-type compound semiconductor substrate 41 SiO 2 film 42 diffusion source film (Zn-doped SiO 2 film) 43,48 annealing cap 46 Zn doping amount Diffusion Source Film (SiO 2 ) with a Low Concentration 47 Diffusion Source Film with a High Zn Dope (SiO 2 )
Claims (3)
拡散してなる発光ダイオードアレイにおいて、（ａ）拡
散領域内の一部に形成される接合深さの浅い拡散層と、
（ｂ）該接合深さの浅い拡散層の周囲に形成される接合
深さの深い拡散層と、（ｃ）前記接合深さの浅い拡散層
にコンタクトをとるｐ側電極とを具備する発光ダイオー
ドアレイ。1. A light emitting diode array formed by selectively diffusing Zn into an n-type compound semiconductor substrate, wherein: (a) a diffusion layer having a shallow junction depth formed in a part of a diffusion region;
(B) A light-emitting diode comprising a diffusion layer having a deep junction formed around the diffusion layer having a shallow junction depth, and (c) a p-side electrode in contact with the diffusion layer having a shallow junction depth. array.
拡散してなる発光ダイオードアレイの製造方法におい
て、（ａ）拡散開口部内に深さの異なる接合領域を形成
する工程と、（ｂ）接合深さの浅い領域へｐ側電極のコ
ンタクトをとる工程とを施すことを特徴とする発光ダイ
オードアレイの製造方法。2. A method of manufacturing a light-emitting diode array in which Zn is selectively diffused in an n-type compound semiconductor substrate, (a) a step of forming junction regions having different depths in a diffusion opening, and (b) And a step of making contact with the p-side electrode in a region having a shallow junction depth.
拡散してなる発光ダイオードアレイの製造方法におい
て、（ａ）拡散開口部内の中央部に張り出す拡散防止膜
を形成し、横方向拡散による拡散層を形成する工程と、
（ｂ）前記拡散防止膜を除去し、該拡散防止膜が除去さ
れた領域にｐ側電極のコンタクトをとる工程とを施すこ
とを特徴とする発光ダイオードアレイの製造方法。3. A method for manufacturing a light-emitting diode array, which comprises selectively diffusing Zn in an n-type compound semiconductor substrate, wherein (a) a diffusion preventing film is formed to extend to a central portion in a diffusion opening, and lateral diffusion is performed. A step of forming a diffusion layer by
(B) a step of removing the diffusion barrier film and making a contact with the p-side electrode in the region where the diffusion barrier film has been removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP942095A JP3236463B2 (en) | 1995-01-25 | 1995-01-25 | Light emitting diode and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP942095A JP3236463B2 (en) | 1995-01-25 | 1995-01-25 | Light emitting diode and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08204231A true JPH08204231A (en) | 1996-08-09 |
| JP3236463B2 JP3236463B2 (en) | 2001-12-10 |
Family
ID=11719880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP942095A Expired - Lifetime JP3236463B2 (en) | 1995-01-25 | 1995-01-25 | Light emitting diode and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3236463B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4908837B2 (en) | 2005-12-13 | 2012-04-04 | キヤノン株式会社 | Light emitting element array and image forming apparatus |
-
1995
- 1995-01-25 JP JP942095A patent/JP3236463B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3236463B2 (en) | 2001-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6246078B1 (en) | Semiconductor light emitting element | |
| JPH08111544A (en) | Semiconductor light-emitting element | |
| JP2004047760A (en) | Light emitting diode and epitaxial wafer therefor | |
| US5801404A (en) | High efficiency, aluminum gallium arsenide LED arrays utilizing zinc-stop diffusion layers | |
| US6420731B1 (en) | Light emitting diode and manufacturing method thereof | |
| US6384429B1 (en) | Light-emitting semiconductor device with reduced obstructions to light emission | |
| US5994723A (en) | Semiconductor element and its method of manufacturing | |
| JPH08204231A (en) | Emission diode array and fabrication thereof | |
| JP2005235798A (en) | Light-emitting diode, and epitaxial wafer for the same | |
| KR20050035325A (en) | Nitride semiconductor light emitting device and method of manufacturing the same | |
| JPH08213649A (en) | Semiconductor light emitting element | |
| JP3717284B2 (en) | LIGHT EMITTING ELEMENT, LIGHT EMITTING ELEMENT ARRAY, AND LIGHT EMITTING ELEMENT MANUFACTURING METHOD | |
| US6762437B2 (en) | Light emitting semiconductor device | |
| JPH1197741A (en) | Light emitting element, its array and manufacture thereof | |
| JPH08203841A (en) | Solid-phase diffusion of zn and manufacture of led | |
| JPH08186287A (en) | Semiconductor light-emitting diode | |
| JPH077846B2 (en) | Method of manufacturing light emitting device | |
| JP3012151B2 (en) | Light emitting / receiving element and method of manufacturing the same | |
| JP2001196629A (en) | Semiconductor light emitting device and its manufacturing method | |
| JPH0458714B2 (en) | ||
| JP3126897B2 (en) | Manufacturing method of light receiving / emitting element | |
| KR100323673B1 (en) | Laser diode and method for fabricating the same | |
| JPH07235731A (en) | Manufacture of compound semiconductor device | |
| JPH088458A (en) | Surface type light emitting diode | |
| JPH06169104A (en) | Emiconductor light-emitting device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20010918 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070928 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080928 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080928 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090928 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090928 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100928 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110928 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110928 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120928 Year of fee payment: 11 |