JPH08204042A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device which prevents the undesirable spread in the transverse direction of a source-drain diffused layer for a MOS transistor by a method wherein a silicon oxide film in an opening part to be used as a part of a sidewall body is formed by a liquid growth operation so that an emitter diffused layer and an external base diffused layer for a bipolar transistor can be formed in a self-aligned manner. CONSTITUTION: A P-type semiconductor film 13 and a first insulating film 16 are laminated and formed on a region 12 which is to be used as an N-type collector diffused layer in a semiconductor substrate, they are removed, and an opening part 18 which exposes the first region 12 selectively is formed. After that, a silicon oxide film 20 is formed inside the opening part 18 by a liquid growth operation. Then, a sidewall insulating film 22W is formed, and an emitter diffused layer 24 is formed in a self-aligned manner with an external base diffused layer 23 by the silicon oxide film 20 and the sidewall insulating film 22W. As a result, a high-temperature heat treatment to form a thermal oxidation silicon film is not required, and a source diffused layer and a drain diffused layer for a MOS transistor are not short-circuited undesirably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a bipolar transistor for forming an emitter diffusion layer in a self-aligned manner with an external base diffusion layer, which is an insulated gate field effect transistor (hereinafter referred to as MOS transistor, (Hereinafter referred to as ") and other elements on the same semiconductor substrate.

[0002]

2. Description of the Related Art A conventional bipolar transistor will be described with reference to FIG.

First, in FIG. 6A, an N-type epitaxial layer 12 to be a collector diffusion layer is formed on an N-type buried layer 2 on a silicon substrate, and a P-type polysilicon film 13 and CVD silicon are formed on the N-type epitaxial layer 12. The oxide film 16 and the silicon nitride film 29 are stacked, and the silicon nitride film 29, the CVD silicon oxide film 16 and the P-type polysilicon film 13 are selectively etched by using a photoresist pattern (not shown) as a mask to form an N-type epitaxial layer. The upper surface of 12 is selectively exposed.

After removing the photoresist pattern, thermal oxidation is performed in an oxidizing atmosphere to expose N.
A thermal oxide silicon film 30 is formed on the upper surface of the type epitaxial layer 12 and the side surface of the P-type polysilicon film 13. At this time, the P-type external base diffusion layer 23 is formed using the P-type polysilicon film 13 as a diffusion source.

Next, in FIG. 6B, a P-type intrinsic base diffusion layer 21 is formed by boron ion implantation through the thermal silicon oxide film 30 and activation heat treatment. And C
By applying VD silicon oxide film and anisotropic etching,
The side wall insulating film 22W made of this CVD silicon oxide film is formed and the central portion of the thermally oxidized silicon film 30 is removed to form an N-type polysilicon film 25 serving as an emitter electrode, and the N-type polysilicon film 25 is diffused by heat treatment. An N-type emitter diffusion layer 24 is formed in the P-type intrinsic base diffusion layer 21 as a source.

According to this structure, the distance between the N-type emitter diffusion layer 24 and the P-type external base diffusion layer 23 is self-aligned by the side wall body composed of the thermal oxide silicon film 30 and the side wall insulating film 22W. Is decided. For this reason P
The area of the type intrinsic base diffusion layer 21 becomes small, and as a result, a high performance bipolar transistor having a small base-collector parasitic capacitance and a small base resistance can be obtained.

[0007]

In the above-mentioned prior art, since boron ion implantation for forming the P-type intrinsic base diffusion layer 21 is performed through the thermal silicon oxide film 30, a thin P-type intrinsic base diffusion layer 21 is formed. Moreover, the damage to the silicon crystal due to the implantation can be mitigated.

However, this thermal silicon oxide film 30
To form a high temperature steel at 900-950 ℃.
Mux oxidation is required. Therefore, when a fine diffusion layer is already formed in another region of the substrate, there is a problem that the diffusion layer causes an unwanted lateral spread diffusion due to this thermal oxidation step, and its shape collapses or a short circuit occurs. For example, B having a bipolar transistor (Bi) having the structure of FIG.
In iMOS and BiCMOS, since the source and drain diffusion layers of the MOS transistor are already formed and then the above-described thermal silicon oxide film 30 is formed, the source and drain diffusion layers cause an undesired lateral spread during the high temperature heat treatment. However, especially when the gate length is 0.4 μm or less, an accident occurs in which the source diffusion layer and the drain diffusion layer are short-circuited.

Further, when steam oxidation, which is a high-temperature heat treatment in an oxidizing atmosphere, is used, the gate structure of the MOS transistor and the source / drain diffusion layers are covered with only a silicon oxide film, so that the silicon oxide film acts as a barrier for oxidizing species. Characteristic change of the MOS transistor (threshold voltage V _T
Fluctuations and the occurrence of diffusion layer leakage current). In order to prevent such characteristic fluctuations, it is indispensable to cover the entire surface with a silicon nitride film 29 that is an oxidation resistant film, and there is also a problem that the number of steps for forming this silicon nitride film 29 increases. .

In order to further increase the cut-off frequency f _T of the bipolar transistor, phosphorus is ion-implanted with high energy through the thermally oxidized silicon film 30 to form an N-type high-concentration collector diffusion layer 27 shown by a chain double-dashed line. However, at this time, phosphorus penetrates the silicon nitride film 29, the silicon oxide film 16, and the P-type polysilicon film 13 and is also introduced into the substrate portion thereunder, which adversely affects the bipolar transistor characteristics. In order to avoid this adverse effect, it is necessary to perform phosphorus ion implantation using the photoresist pattern used when the opening 31 was formed as a mask again, but in the conventional technique of FIG. 6, the thermal silicon oxide film 30 is formed. This photoresist pattern cannot be used as a mask for phosphorus ion implantation because the photoresist pattern has already been removed for the thermal oxidation treatment. Therefore, in the conventional technique shown in FIG. 6, the N-type region 27 indicated by a two-dot chain line is shown.
It is impossible to improve the cutoff frequency f _T by forming On the other hand, before ion-implanting with high energy using the photoresist pattern as a mask before removing the photoresist pattern and forming the thermal silicon oxide film 30 in FIG. 6, no insulating film is formed on the surface of the epitaxial layer 12. Since it is ion implantation in an exposed state that has not been formed,
The crystal of the epitaxial layer is damaged and the characteristics are deteriorated, and the yield is reduced.

In order to solve these problems, it is possible to use a silicon oxide film formed by the CVD method instead of the thermal silicon oxide film 30. However, in the case of this CVD silicon oxide film, the oxide film thickness at the bottom of the opening varies depending on the width of the opening, so that the depth of the intrinsic base diffusion layer due to ion implantation through the film varies, which causes the Hfe or the like of the bipolar transistor. This causes the inconvenience that the characteristics vary. That is, when the intrinsic base diffusion layer is formed by ion implantation, the implantation energy is set so that the implantation peak concentration comes to the upper surface of the silicon substrate, that is, the interface with the oxide film, so that the opening thickness varies and the peak concentration is increased. Is located in the oxide film, or conversely is located in the silicon substrate, and the junction depth of the intrinsic base diffusion layer does not have a constant value.

Specifically, C on the flat upper surface outside the opening
Even if the film thickness of the VD oxide film is constant, when the aspect ratio of the opening (opening depth / opening width) becomes large, the thickness of the CVD oxide film at the bottom of the opening becomes thin. As described above, the thickness of the CVD oxide film at the bottom of the opening varies depending on the aspect ratio of the opening. For example, when transistors having different emitter sizes are formed on the same substrate, the aspect ratios of the openings forming the emitters are different from each other. Differently, this causes the thickness of the CVD silicon oxide film in the opening to be different, which makes it impossible to set the junction depth of the intrinsic base diffusion layer of the transistor to a predetermined constant value.

Further, the CVD silicon oxide film has a predetermined thickness on the side surface of the opening because the thickness of the CVD silicon oxide film varies even in the vertical portion which constitutes a part of the side wall body. Will be difficult to do.

Therefore, it is an object of the present invention that when a silicon oxide film is formed in an opening to form an emitter diffusion layer and an extrinsic base diffusion layer of a bipolar transistor in a self-aligned manner, another portion of the substrate is already formed. A semiconductor device which does not cause undesired lateral diffusion in a formed diffusion layer, for example, a source / drain diffusion layer of a MOS transistor, and suppresses variations in depth of intrinsic base diffusion layer and variations in emitter position. It is to provide a manufacturing method.

Another object of the present invention is to form the above-mentioned silicon oxide film at another portion of the substrate even if the formation of an oxidation resistant film such as a silicon nitride film for protecting the whole is omitted. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which characteristic variations of elements such as MOS transistors do not occur.

Another object of the present invention is to provide a method for manufacturing a semiconductor device having the above-described method for forming a silicon oxide film, which enables formation of a high concentration collector diffusion layer for improving the cutoff frequency characteristic of a bipolar transistor. is there.

[0017]

A feature of the present invention is that a second conductivity type second region serving as a diffusion source for forming an external base diffusion layer is formed on a first conductivity type first region serving as a collector diffusion layer of a semiconductor substrate. Stacking the first semiconductor film and the first insulating film, forming a photoresist pattern on the first insulating film, and using the photoresist pattern as a mask, the first insulating film and the first insulating film A step of selectively removing the first semiconductor film to form an opening that selectively exposes the first region; and liquid phase growth using the photoresist pattern as a mask to form a bottom surface of the opening. Forming a liquid-phase-grown silicon oxide film having a horizontal portion on the exposed first region and a vertical portion on the first semiconductor film and the first insulating film exposed on the side surface of the opening. And the liquid phase growth A step of ion-implanting an impurity of the second conductivity type into the intrinsic base diffusion layer forming region through the horizontal portion of the conoxide film, and a second step from above the liquid crystal growth silicon oxide film in the opening to above the first insulating film. And a step of performing anisotropic etching to leave the second insulating film as a sidewall insulating film on the vertical portion and the peripheral portion of the horizontal portion of the liquid phase grown silicon oxide film. A second conductivity type is provided in a central portion of the intrinsic base diffusion layer forming region which is separated from the first semiconductor film by a predetermined distance by a vertical portion of the liquid phase growth silicon oxide film and a sidewall insulating film of the second insulating film. And a step of forming an emitter diffusion layer by introducing the impurity of 1.). Here, after the ion implantation of the second conductivity type, heat treatment is performed in an inert gas atmosphere to activate the implanted ions to form an intrinsic base diffusion layer, and at the same time, impurities of the second conductivity type are removed from the first semiconductor film. Can be diffused to form an external base diffusion layer, and a second semiconductor film of the first conductivity type is deposited on the exposed central portion of the intrinsic base diffusion layer forming region, preferably by lamp heating. The emitter diffusion layer can be formed by diffusing impurities of the first conductivity type from the second semiconductor film.

Further, a MOS is formed on the second region of the semiconductor substrate.
Forming a gate structure of a transistor, forming source and drain diffusion layers on both sides of a channel region under the gate structure, covering the whole with an insulating layer, and selecting the insulating layer on the first region of a semiconductor substrate The BiMOS can be manufactured by stacking the first semiconductor film and the first insulating film on the first region exposed by the selective removal.

Further, using the photoresist pattern as a mask, high-energy first-conductivity-type impurities are diffused through the horizontal portion of the liquid-phase-grown silicon oxide film at a deep location in the first region. A high concentration collector region can also be formed by ion-implanting into the layer formation region and heat treatment for activation.

[0020]

According to the above-mentioned manufacturing method, the silicon oxide film of the opening which becomes a part of the side wall body for forming the emitter diffusion layer and the external base diffusion layer of the bipolar transistor in a self-aligned manner is formed by liquid phase growth. Therefore, the thermal oxidation process for this formation is unnecessary, which causes an undesired lateral spread in the diffusion layers already formed in other regions of the substrate, for example, the source and drain diffusion layers of the MOS transistor. Will not occur and a short circuit will not occur.

The film thickness at the bottom of the opening of the silicon oxide film formed by liquid phase growth does not depend on the aspect ratio of the opening, and the film thickness is within ± 10% of the target film thickness even within a fine opening. Since it can be realized, it is possible to suppress the variation in the depth of the intrinsic base diffusion layer formed by ion-implanting impurities through the silicon oxide film regardless of the size of the opening.

Further, since a high temperature heat treatment in an oxidizing atmosphere is unnecessary, even if the formation of an oxidation resistant film such as a silicon nitride film for protecting the whole is omitted, it is formed at another portion of the substrate.
Characteristic variations of elements such as OS transistors do not occur. Therefore, the number of steps can be reduced by the amount by which the protective silicon nitride film is omitted.

Further, since the silicon oxide film is formed by liquid phase growth, it is not necessary to remove the photoresist pattern used for forming the opening when forming the silicon oxide film.
Therefore, using this photoresist pattern as a mask again, impurities of one conductivity type can be ion-implanted through the liquid phase grown silicon oxide film with high energy. As a result, a bipolar transistor having a high-concentration collector diffusion layer formed in a deep portion and improved cutoff frequency characteristics can be obtained with a high yield.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 1A to 1C, the bipolar transistor region 100 is shown on the left side and the MOS transistor region 200 is shown on the right side, and only the bipolar transistor region 100 is enlarged in FIGS. 2A, 2B and 3. And show it.

First, in FIG. 1A, the specific resistance is 5 to 20.
Layer resistance of 15 to 50 Ω / on P type silicon substrate 1 of Ω cm
□ N-type buried layer 2 and layer resistance 200 to 1000Ω / □
After forming the P-type buried layer 3 of, the specific resistance is 0.5 to 2.0Ω.
The N-type epitaxial layer 12 having a thickness of 600 to 1500 nm is formed to form a silicon substrate. Further, boron is introduced by the ion implantation method to form the P-type channel stopper region 5, and the element region is partitioned by the selective thermal oxidation method to partially bury it in the substrate (epitaxial layer).
A 0 nm thick field oxide film 6 is formed.

Thereafter, the bipolar transistor region 100
Then, phosphorus is introduced by an ion implantation method to form a high concentration N-type collector extraction layer 4.

Boron is introduced into the MOS transistor region 200 by an ion implantation method to form a P-type well 7.
There, a gate structure composed of the gate oxide film 8, a polysilicon gate electrode 9 and a sidewall oxide film 10, and an N-type source and drain diffusion layer 19 of LDD structure,
19 is formed.

After that, the film thickness 1 formed by the CVD method
The whole is covered with a silicon oxide film 11 having a thickness of 00 to 300 nm.

Next, referring to FIG. 1B, an opening 11A is formed in the silicon oxide film 11 in the bipolar transistor region 100.
And 11B are formed, and a P-type polysilicon film 13 having a layer resistance of 100 to 300Ω / □ and a film thickness of 150 to 250 nm is deposited on the upper surface of the N type epitaxial layer 12 to be the collector diffusion layer 12 in the opening 11A. , Layer resistance 100
An N-type polysilicon film 14 having a thickness of 150 to 250 nm and a thickness of ˜300 Ω / □ is formed on the upper surface of the N-type collector extraction layer 4 in the opening 11B.

Next, in FIG. 1C, the entire surface is covered with a silicon oxide film 16 having a film thickness of 20 to 50 nm formed by a CVD method, and the photoresist pattern 17 is used as a mask to form the silicon oxide film 16 and the P-type poly. The silicon film 13 is sequentially and selectively etched to form an opening 18 exposing the central portion of the upper surface of the N-type epitaxial layer 12.

Next, referring to FIG. 2A, the silicon substrate (silicon wafer) is immersed in hydrosilicofluoric acid at 35 to 40 ° C. to form a bipolar transistor region 10.
0 silicon oxide film 16 and P-type polysilicon film 13
In the opening 18 provided by selectively etching
Liquid phase growth is performed to form a silicon oxide film 20 having a film thickness of 20 to 40 nm.

Next, referring to FIG. 2B, the energy is 5 to 15 keV and the dose is through the horizontal portion of the liquid phase grown silicon oxide film 20 deposited on the upper surface of the N type epitaxial layer 12 which is the bottom of the opening 18. Is 1 to 4 × 10 ¹³ / c
Boron is ion-implanted to form the P-type intrinsic base diffusion layer 21 under the condition of m ² .

Thereafter, a film thickness of 150 to 25 is formed by the CVD method.
A 0 nm silicon oxide film 22 is entirely formed.

Next, in FIG. 3, heat treatment is performed at 700 to 750 ° C. in a nitrogen atmosphere which is an inert gas atmosphere,
Using the P-type polysilicon film 13 as a diffusion source, the high-concentration P-type external base diffusion layer 23 is formed and the P-type intrinsic base diffusion layer 2 is formed.
The activation process 1 is performed.

After that, the sidewall insulating film 22W is formed from the CVD silicon oxide film 22 by the etch back technique, and at the same time, the central portion of the liquid phase grown silicon oxide film 20 is removed to expose the P-type intrinsic base diffusion layer 21. This sidewall insulating film 2
A sidewall body for forming the emitter diffusion layer from the external base diffusion layer in a self-aligned manner is composed of 2 W and the remaining liquid phase grown silicon oxide film 20.

After that, an N-type polysilicon film 25 having a film thickness of 150 to 250 nm is formed, and 1000 to 1050 ° C., and 1
N-type emitter diffusion layer 24 is formed using N-type polysilicon film 25 as a diffusion source by lamp annealing for 0 to 30 seconds.

FIGS. 4 to 5 show an embodiment in which a part of FIGS. 1 to 3 is modified. In FIGS. 4 and 5, the same or similar portions as those of FIGS. 1 to 3 are denoted by the same reference numerals. The overlapping description will be omitted.

FIGS. 1A, 1B and 1C of the previous embodiment.
After the step of FIG. 2A, the CVD is performed after ion implantation for the P-type intrinsic base diffusion layer 21 in FIG.
Before the silicon oxide film 22 is formed, the energy is 300 to
Phosphorus is ion-implanted through the horizontal portion of the liquid phase grown silicon oxide film 20 under the conditions of 500 keV and a dose amount of 1 to 5 × 10 ¹³ / cm ² . Then, after that, heat treatment is performed at 700 to 750 ° C. in a nitrogen atmosphere of an inert gas atmosphere, and the P-type polysilicon film 13 is used as a diffusion source to obtain a high concentration of P.
During the formation of the type external base diffusion layer 23 and the activation process of the P type intrinsic base diffusion layer 21, the high-energy implanted phosphorus ions are also activated and come into contact with the upper portion of the N type buried layer 2 and above it. High concentration collector diffusion layer 2 protruding to the
7 is formed.

In the bipolar transistor of FIG. 5 according to the process of FIG. 4, since the collector diffusion layer immediately below the emitter diffusion layer 24 has a high impurity concentration due to the high concentration collector diffusion layer 27, the cutoff frequency f _T is improved. But this N
The existence of the high-concentration collector diffusion layer 27 lowers the collector-emitter breakdown voltage. Therefore, this embodiment is suitable for a semiconductor device that requires a high cutoff frequency f _T even if the collector-emitter breakdown voltage is low.

[0041]

As described above, according to the present invention, by using the liquid phase grown silicon oxide film, a high temperature steam oxidation at 900 to 950 ° C. for forming a thermally oxidized silicon film is performed. A high-temperature heat treatment in a gas atmosphere is not necessary, and ion activation heat treatment at a much lower temperature than heat treatment for forming silicon oxide and lamp annealing for a short time in seconds are used. Therefore, for example, a gate length of 0.4 μm or less Even if the source and drain diffusion layers of the MOS transistor having the above are already formed, the formation of this high performance bipolar transistor does not undesirably short-circuit the source diffusion layer and the drain diffusion layer of the MOS transistor.

The activation heat treatment is performed in an inert gas, and the heat treatment in an oxidizing gas atmosphere is not performed. Therefore, when forming a high performance bipolar transistor, it is not necessary to cover an already formed MOS transistor with an oxidation resistant film such as a silicon nitride film. Thereby, the formation of the oxidation resistant film can be omitted, and the manufacturing process can be reduced accordingly.

Further, the film thickness of the silicon oxide film formed by liquid phase growth can be realized with an accuracy within ± 10% of the target film thickness even in a fine opening. Furthermore, the film thickness at the bottom of the opening of the silicon oxide film formed by liquid phase growth does not depend on the aspect ratio of the opening. Therefore, regardless of the size of the opening, it is possible to suppress variations in the depth of the intrinsic base diffusion layer formed by ion-implanting impurities through the horizontal portion of the silicon oxide film.

Further, variations in the film thickness of the vertical portion of the silicon oxide film formed by liquid phase growth are also suppressed, so that the distance between the external base diffusion layer and the emitter diffusion layer can be set to a predetermined value.

Further, regarding the bipolar transistor which requires the high concentration collector diffusion layer immediately below the emitter,
Since it can be formed by ion implantation through the liquid phase growth silicon oxide film using the photoresist pattern for forming the opening as a mask, the yield is improved by about 20% compared to the conventional case.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

2A to 2D are cross-sectional views sequentially showing steps subsequent to FIG. 1 in a bipolar transistor region.

FIG. 3 is a cross-sectional view showing a bipolar transistor obtained by the process continued from FIG.

FIG. 4 is a sectional view showing a part of another embodiment of the present invention.

5 is a cross-sectional view showing a bipolar transistor obtained by a process following that of FIG.

FIG. 6 is a cross-sectional view showing a conventional technique in order of manufacturing steps.

[Explanation of symbols]

 1 P-type silicon substrate 2 N-type buried layer 3 P-type buried layer 4 N-type collector extraction layer 5 P-type channel stopper region 6 field oxide film 7 P-type well 8 gate oxide film 9 polysilicon gate electrode 10 sidewall -Al oxide film 11, 16, 22 CVD silicon oxide film 11A, 11B Opening 12 N-type epitaxial layer (N-type collector diffusion layer) 13 P-type polysilicon film 14 N-type polysilicon film 17 Photoresist pattern 18 Opening 19 N Type Source / drain diffusion layer 20 Liquid phase grown silicon oxide film 21 P type intrinsic base diffusion layer 22W Side wall insulating film 23 P type external base diffusion layer 24 N type emitter diffusion layer 25 N type polysilicon film 27 High concentration collector diffusion layer 29 Silicon nitride film 30 Thermal oxide film 31 Opening 100 Bipolar transistor Pass 200 MOS transistor area

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8222 21/331 29/73 H01L 29/72

Claims (6)

[Claims] 1. A first semiconductor film of a second conductivity type and a first insulating film which are diffusion sources for forming an external base diffusion layer on a first region of the first conductivity type which is a collector diffusion layer of a semiconductor substrate. And a step of forming a photoresist pattern on the first insulating film, and using the photoresist pattern as a mask to selectively remove the first insulating film and the first semiconductor film. Forming an opening selectively exposing the first region, and using the photoresist pattern as a mask to perform liquid phase growth so that the first region exposed horizontally on the bottom surface of the opening is horizontally aligned. Forming a liquid-phase-grown silicon oxide film having a vertical portion on the first semiconductor film and the first insulating film having a portion exposed on the side surface of the opening; Through the horizontal part Ion implantation of an impurity of the second conductivity type into the intrinsic base diffusion layer forming region, and forming a second insulating film from above the liquid phase grown silicon oxide film in the opening to above the first insulating film A step of performing anisotropic etching to leave the second insulating film as a sidewall insulating film on a vertical portion and a peripheral portion of a horizontal portion of the liquid phase grown silicon oxide film; An impurity of the first conductivity type is introduced into a central portion of the intrinsic base diffusion layer forming region which is separated from the first semiconductor film by a predetermined distance by the vertical portion of the oxide film and the sidewall insulating film of the second insulating film. And a step of forming an emitter diffusion layer. 2. After the second conductivity type ion implantation, heat treatment is performed in an inert gas atmosphere to activate the implanted ions to form an intrinsic base diffusion layer, and at the same time, the first conductive film is used to form the second conductivity type. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the external base diffusion layer is formed by diffusing a type impurity. 3. A first-conductivity-type second semiconductor film is deposited on the exposed central portion of the intrinsic base diffusion layer formation region, and impurities of the first-conductivity type are diffused from the second semiconductor film. The method of manufacturing a semiconductor device according to claim 1, wherein the emitter diffusion layer is formed. 4. A gate structure of an insulated gate field effect transistor is formed on a second region of a semiconductor substrate, source and drain diffusion layers are formed on both sides of a channel region below the gate structure, and an insulating layer is formed entirely. 2. The first semiconductor film and the first insulating film are laminated and formed on the first region exposed by covering and selectively removing the insulating layer. Manufacturing method of semiconductor device. 5. A high-concentration collector located at a deep portion of the first region with high energy and impurities of the first conductivity type through the horizontal portion of the liquid-phase-grown silicon oxide film using the photoresist pattern as a mask. 2. The method for manufacturing a semiconductor device according to claim 1, wherein ions are implanted into the diffusion layer forming region, and then the second insulating film forming the sidewall insulating film is formed. 6. After the first-conductivity-type high-energy ion implantation and the second-conductivity-type ion implantation, heat treatment is carried out in an inert gas atmosphere to activate these implanted ions to enhance the first-conductivity-type ion implantation. At the same time as forming the concentration collector diffusion layer and the second conductivity type intrinsic base diffusion layer respectively,
6. The method of manufacturing a semiconductor device according to claim 5, wherein an external base diffusion layer is formed by diffusing a second conductivity type impurity from the first semiconductor layer.