JPH08203912A - Semiconductor wafer, semiconductor device using the same, manufacturing method thereof - Google Patents

Abstract

PURPOSE: To avoid the deterioration in the junction characteristics at the pn junction part of a semiconductor device by avoiding the dislocation of thermal stress imposed on the inside of a bulk crystal and the dislocation caused on the surface of an epitaxial layer. CONSTITUTION: Within a semiconductor wafer composed of an n+type semiconductor substrate 1 wherein arsenic is introduced to a single crystal silicon or another semiconductor wafer composed of n+type semiconductor substrate 1 and n-type epitaxial layer 2, the inter-lattice oxygen concentration of the n+type semiconductor substrate 1 is set not to exceed 9×10<17> [atoms/cm<3> ]. Besides, within a semiconductor device composed of the n+type substrate 1 and the n-type epitaxial layer 2, the interlattice oxygen concentration of the n+type semiconductor substrate 1 is set not to exceed 9×10<17> [atoms/cm<3> ].

Description

Detailed Description of the Invention

[0001]

The present invention relates to arsenic (A
The present invention relates to a semiconductor wafer composed of a semiconductor substrate having s) introduced therein, a semiconductor device using the same, and a technique effectively applied to a method for manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art A plurality of MOSFETs (MetalOxide
SemiconductorFieldEffectTransistor)
Semiconductor devices connected in parallel to obtain high power (Power MO
SFET), for example, a vertical MO of n-channel conductivity type
Semiconductor devices having SFETs have been developed.
The drain region of this n-channel conductivity type vertical MOSFET
The area is an n-type semiconductor substrate and an n-type semiconductor formed on the main surface thereof.
It is composed of a epitaxial layer.

The semiconductor device is formed into a semiconductor wafer in its manufacturing process. The semiconductor wafer is
It is composed of an n-type semiconductor substrate and an n-type epitaxial layer formed on the main surface thereof.

The n-type semiconductor substrate is made of single crystal silicon containing antimony (Sb) and has a high impurity concentration for the purpose of reducing the on-resistance of the vertical MOSFET. Reducing the on-resistance of a vertical MOSFET is an important technical issue for increasing the power gain of a semiconductor device. Therefore, a technique for further reducing the on-resistance of the vertical MOSFET is disclosed in, for example, Japanese Patent Laid-Open No. 3-236225. This technique uses arsenic (As), which has a higher solid solubility limit in single crystal silicon than antimony, and further increases the impurity concentration of the n-type semiconductor substrate to reduce the on-resistance of the vertical MOSFET.

[0005]

However, the present inventor has found that the above-mentioned n-type semiconductor substrate using arsenic (having a main surface of (1
As a result of studying (00) a semiconductor substrate set on a crystal plane), the following problems were found.

As shown in FIG. 12 (schematic plan view) and FIG. 13 (schematic cross-sectional view), a high impurity concentration n-type semiconductor substrate 14 in which arsenic is introduced into single crystal silicon has 10 to 12 × 10.
^It contains a large amount of interstitial oxygen (Oi) of about ¹⁷ [atoms / cm ³ ]. Therefore, many crystal defects 15 due to oxygen precipitation are generated inside the bulk crystal, and many thermal stress dislocations (slip lines) 16 are generated in the peripheral region of the semiconductor wafer 12 in the heat treatment step in the manufacturing process of the semiconductor device. This thermal stress dislocation 16 is, for example, a vertical MO of n-channel conductivity type.
In the case of SFET, a pn junction formed by a source region (n-type semiconductor region) and a channel formation region (p-type semiconductor region) or a channel formation region (p-type semiconductor region) and a drain region (n-type epitaxial layer) The junction characteristics of the pn junction formed in step S4 are deteriorated, resulting in an increase in leak current.

Further, due to the generation of crystal defects 15 due to oxygen precipitation, many dislocations 17 are generated on the surface of the n-type epitaxial layer 13. This dislocation deteriorates the insulation resistance of the gate insulating film (thermal oxide film) of the vertical MOSFET and causes an increase in leak current.

An object of the present invention is to provide a semiconductor wafer which is composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon and which prevents generation of thermal stress dislocations generated inside the bulk crystal.

Another object of the present invention is to provide a semiconductor wafer having arsenic introduced into single crystal silicon and a semiconductor wafer composed of an epitaxial layer formed on the main surface thereof with a thermal stress generated inside the bulk crystal. It is intended to provide a semiconductor wafer which prevents generation of dislocations and also prevents generation of dislocations generated on the surface of an epitaxial layer.

Another object of the present invention is to include a semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on the main surface thereof. The epitaxial layer and the epitaxial layer are formed on the epitaxial layer. Another object of the present invention is to provide a semiconductor device having a semiconductor element having a pn junction formed of a semiconductor region and preventing deterioration of junction characteristics at the pn junction of the semiconductor element.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which prevents deterioration of insulation resistance of a thermal oxide film formed on the surface of an epitaxial layer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) In a semiconductor wafer composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon, the interstitial oxygen concentration of the semiconductor substrate is set to 9 × 10 ¹⁷ [atoms / cm ³ ] or less.

(2) In a semiconductor wafer composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on its main surface, the interstitial oxygen concentration of the semiconductor substrate is 9 × 10 ¹⁷ [atoms]. / Cm ³ ] or less.

(3) An extrinsic gettering layer for trapping heavy metal contaminants is formed on the rear surface of the semiconductor substrate, which faces the main surface of the means (1) and (2). The extrinsic gettering layer is formed of a polycrystalline silicon film, a silicon nitride film, or a crystal defect layer.

(4) It is composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on the main surface thereof, and is formed of the epitaxial layer and a semiconductor region formed in this epitaxial layer. In a semiconductor device having a semiconductor element having a pn junction, the interstitial oxygen concentration of the semiconductor substrate is 9 × 10 ¹⁷ [atoms / cm ³ ].
Set as follows.

(5) In the method of manufacturing a semiconductor device, arsenic is introduced into single crystal silicon, and the interstitial oxygen concentration is set to 9 × 10 ¹⁷ [atoms / cm ³ ] or less and its main surface. The method includes the steps of preparing a semiconductor wafer composed of the epitaxial layer formed above, and forming a thermal oxide film on the main surface of the epitaxial layer.

[0019]

According to the above-mentioned means (1), the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, so that the thermal stress generated inside the bulk crystal in the heat treatment step in the manufacturing process of the semiconductor device. Generation of dislocation can be prevented.

According to the above-mentioned means (2), the amount of crystal defects inside the bulk crystal due to the oxygen precipitation can be reduced, so that the thermal stress dislocation generated in the semiconductor wafer in the heat treatment step in the manufacturing process of the semiconductor device. Can be prevented.

Further, since the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, it is possible to prevent the crystal defects inside the bulk crystal from propagating to the epitaxial layer in the heat treatment step in the manufacturing process of the semiconductor device. It is possible to prevent the generation of dislocations on the surface of the epitaxial layer.

According to the above-mentioned means (3), it is possible to provide the extrinsic gettering effect for capturing the heavy metal substance.

According to the above-mentioned means (4), the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, and thermal stress dislocations occurring inside the bulk crystal in the heat treatment step in the semiconductor device manufacturing process. Since it is possible to prevent the occurrence of the above, it is possible to prevent the deterioration of the junction characteristics at the pn junction of the semiconductor element.

According to the above-mentioned means (5), the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, and dislocations generated on the surface of the epitaxial layer in the heat treatment step in the manufacturing process of the semiconductor device can be reduced. Since it can be prevented from occurring, deterioration of the insulation resistance of the thermal oxide film formed on the surface of the epitaxial layer can be prevented.

[0025]

EXAMPLES The structure of the present invention will be described below with reference to examples.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

Example 1 FIG. 1 shows Example 1 of the present invention.
2 is a plan view of the semiconductor wafer, and FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor wafer.

As shown in FIGS. 1 and 2, a semiconductor wafer is a high impurity concentration n + type semiconductor substrate in which arsenic (As) of about 3 × 10 ¹⁹ [atoms / cm ³ ] is introduced into single crystal silicon. It consists of 1. The interstitial oxygen concentration of the n + type semiconductor substrate 1 is set to, for example, about 9 × 10 ¹⁷ [atoms / cm ³ ]. The main surface of the n + type semiconductor substrate 1 is formed of a (100) crystal plane, and the resistance value on the crystal plane is about 0.006 [Ωcm].
It is set to a degree. Since the solid solution limit of arsenic in single crystal silicon is higher than that of antimony (Sb), the impurity concentration of the n + type semiconductor substrate 1 can be increased as compared with antimony.

An extrinsic gettering layer 3 for trapping heavy metal contaminants is formed on the back surface of the n + type semiconductor substrate 1 which faces the main surface. The extrinsic gettering layer 3 is formed of, for example, a polycrystalline silicon film or a silicon nitride film. The extrinsic gettering layer 3 may be formed of a crystal defect layer (damage layer). The crystal defect layer is formed by roughening the back surface of the n + type semiconductor substrate 1 by polishing. That is, the semiconductor wafer has an extrinsic gettering effect of capturing heavy metal contaminants.

The semiconductor wafer is used in a manufacturing process of a semiconductor device, and a heat treatment step is performed several times in the manufacturing process. Therefore, the present invention is 800-1
An experiment in which the semiconductor wafer was subjected to heat treatment for several times under a temperature condition of about 000 [° C.] was attempted, and then observed with an X-ray topography. As a result, FIG. 3 (schematic plan view) and FIG. As shown in the schematic cross-sectional view), the amount of crystal defects 15 generated inside the bulk crystal was reduced and no thermal stress dislocation was generated. Therefore, the present inventors consider that the occurrence of thermal stress dislocations can be prevented by setting the interstitial oxygen concentration of the n + type semiconductor substrate 1 to 9 × 10 ¹⁷ [atoms / cm ³ ].

As described above, in the semiconductor wafer composed of the n + type semiconductor substrate 1 in which arsenic is introduced into the single crystal silicon, the interstitial oxygen concentration of the n + type semiconductor substrate 1 is 9 × 10.
By setting it to ¹⁷ [atoms / cm ³ ] or less, it is possible to reduce the amount of crystal defects (15) inside the bulk crystal due to oxygen precipitation. Therefore, in the heat treatment step during the semiconductor device manufacturing process, the inside of the bulk crystal can be reduced. It is possible to prevent the occurrence of thermal stress dislocation that occurs in the above.

Further, by forming the extrinsic gettering layer 3 on the back surface of the n + type semiconductor substrate 1, an extrinsic gettering effect for trapping heavy metal contaminants can be provided, so that crystal defects are reduced. Even if the intrinsic gettering effect is reduced, heavy metal contaminants can be captured, and deterioration of the dielectric strength of the thermal oxide film due to heavy metal contaminants can be prevented.

(Embodiment 2) FIG. 5 is a cross-sectional view of essential parts of a semiconductor wafer according to Embodiment 2 of the present invention.

As shown in FIG. 5, the semiconductor wafer is made of single crystal silicon, for example, arsenic of about 3 × 10 ¹⁹ [atoms / cm ³ ].
It is composed of a high impurity concentration n + type semiconductor substrate 1 into which (As) is introduced and an n type epitaxial layer 2 formed on the main surface of the n + type semiconductor substrate 1. The interstitial oxygen concentration of the n + type semiconductor substrate 1 is set to, for example, about 9 × 10 ¹⁷ [atoms / cm ³ ]. The main surface of the n + type semiconductor substrate 1 is formed of a (100) crystal plane, and the resistance value on the crystal plane is about 0.006 [Ω
cm] is set. N type epitaxial layer 2 is composed of single crystal silicon grown on the main surface of n + type semiconductor substrate 1 based on its crystallinity. The n-type epitaxial layer 2 is doped with an n-type impurity having a lower impurity concentration, for example, about 1 × 10 ¹⁶ [atoms / cm ³ ] than the n + type semiconductor substrate 1, and has a resistance value of about 0.6 [Ωcm]. Is set to.

An extrinsic gettering layer 3 for trapping heavy metal contaminants is formed on the back surface of the n + type semiconductor substrate 1 which faces the main surface, as in the first embodiment. That is, the semiconductor wafer of this embodiment has the extrinsic gettering effect of trapping heavy metal pollutants, as in the first embodiment.

The semiconductor wafer is used in a manufacturing process of a semiconductor device, and a heat treatment step is performed several times in the manufacturing process. Therefore, the present invention is 800-1
An experiment was conducted in which the semiconductor wafer was subjected to heat treatment several times under a temperature condition of about 000 [° C.], and then, observation with an X-ray topography was carried out in the same manner as in Example 1 above, and it was found that a bulk crystal was obtained. The amount of crystal defects generated inside was reduced and no thermal stress dislocation was generated. Further, no dislocation was generated on the surface of the n-type epitaxial layer 2. Therefore, similarly to the first embodiment described above, if the interstitial oxygen concentration of the n + type semiconductor substrate 1 is set to 9 × 10 ¹⁷ [atoms / cm ³ ], the occurrence of thermal stress dislocations can be prevented and the n type epitaxial substrate can be formed. It is considered that dislocations generated on the surface of the layer 2 can be prevented.

As described above, in the semiconductor wafer composed of the n + type semiconductor substrate 1 in which arsenic is introduced into the single crystal silicon and the n type epitaxial layer 2 formed on the main surface thereof, the n + type semiconductor substrate 1 is Interstitial oxygen concentration 9 × 10
By setting it to ¹⁷ [atoms / cm ³ ] or less, the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, so that the heat generated inside the bulk crystal during the heat treatment step during the semiconductor device manufacturing process can be reduced. Occurrence of stress dislocation can be prevented.

Since the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, the crystal defects inside the bulk crystal propagate to the n-type epitaxial layer in the heat treatment step in the semiconductor device manufacturing process. It is possible to prevent the occurrence of dislocations on the surface of the n-type epitaxial layer 3.

Further, by forming the extrinsic gettering layer 3 which captures heavy metal contaminants on the back surface of the n + type semiconductor substrate 1, the same effect as that of the first embodiment can be obtained.

According to the present invention, the n + type semiconductor substrate 1 in which arsenic is introduced into single crystal silicon and the p formed on the main surface thereof are used.
It can also be applied to a semiconductor wafer composed of a type epitaxial layer.

(Embodiment 3) FIG. 6 is a cross-sectional view of an essential part showing a schematic structure of a semiconductor device having a vertical MOSFET which is Embodiment 3 of the present invention.

As shown in FIG. 6, the vertical MOSFET Qn
A semiconductor device having a single crystal silicon has, for example, 3 × 10 ¹⁹
Arsenic (As) of about [atoms / cm ³ ] is introduced and formed on the n + type semiconductor substrate 1 and its main surface in which the interstitial oxygen concentration is set to about 9 × 10 ¹⁷ [atoms / cm ³ ] for example. The formed n-type epitaxial layer 2 is formed. The main surface of the n + type semiconductor substrate 1 is formed of a (100) crystal plane, and the resistance value on the crystal plane is set to about 0.006 [Ωcm]. The n-type epitaxial layer 2 is composed of single crystal silicon grown on the main surface of the n + type semiconductor substrate 1 based on its crystallinity. This n-type epitaxial layer 2 is an n + type semiconductor substrate 1
Impurity concentration lower than that of, for example, 1 × 10 ¹⁶ [atoms / c
An n-type impurity of about m ³ ] is introduced, and the resistance value is set to about 0.6 [Ωcm].

The vertical MOSFET Qn is mainly composed of a channel forming region, a gate insulating film 4, a gate electrode 5, a source region and a drain region. The channel formation region is formed by the p-type semiconductor region 6 formed on the main surface of the n-type epitaxial layer 2. Gate insulating film 4 is formed of a thermal silicon oxide film formed on the main surface of n type epitaxial layer 2. Gate electrode 5 is formed of a polycrystalline silicon film formed on the main surface of gate insulating film 4. The source region is n + formed on the main surface of the p-type semiconductor region 6 which is a channel formation region.
It is formed of the type semiconductor region 7. The drain region is formed by the n + type semiconductor substrate 1 and the n type epitaxial layer 2. That is, in the vertical MOSFET Qn, the pn junction formed by the source region (n + type semiconductor region 7) and the channel forming region (p type semiconductor region 6), the channel forming region (p type semiconductor region 6), and the drain region ( It comprises a pn junction formed with the n-type epitaxial layer 2).

Each of the p-type semiconductor region 6 which is the channel forming region and the n + -type semiconductor region 7 which is the source region,
The wiring 10 is electrically connected through the connection hole 9 formed in the interlayer insulating film 8. The wiring 10 is formed of, for example, an aluminum film or an aluminum alloy film.

Although not shown, a final protective film is formed on the main surface of the wiring 10. An electrode 11 is formed on the back surface of the n + type semiconductor substrate 1 which faces the main surface.

Next, a method of manufacturing a semiconductor device having the vertical MOSFET Qn will be described.

First, the semiconductor wafer shown in FIG. 5 is prepared. This semiconductor wafer has the effect of preventing the generation of thermal stress dislocations that occur inside the bulk crystal, the effect of preventing the generation of dislocations that occur at the surface of the n-type epitaxial layer 2, and the extrinsic gettering effect.

Next, a thermal oxidation process is performed to form a gate insulating film 4 made of a thermal silicon oxide film on the main surface of the n-type epitaxial layer 2.

Next, a polycrystalline silicon film deposited by, eg, CVD method is formed on the entire main surface of the gate insulating film 4. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.

Then, the polycrystalline silicon film is patterned to form a gate electrode 5 on the main surface of the element formation region of the gate insulating film 4.

Next, using the gate electrode 5 as a mask for introducing impurities, p-type impurities (for example, boron (B)) are selectively introduced into the main surface of the n-type epitaxial layer 2 by an ion implantation method.

Next, a thermal diffusion process is performed to diffuse the p-type impurities, and as shown in FIG. 7 (a cross-sectional view of an essential part), a p-type channel region, which is a channel forming region, is formed on the main surface of the n-type epitaxial layer 2. The semiconductor region 6 is formed. This thermal diffusion process is about 1000
It is performed in an atmosphere of a temperature of about [° C].

Next, an n-type impurity (for example, arsenic (As)) is selectively introduced into the main surface of the p-type semiconductor region 6 by an ion implantation method.

Next, a thermal diffusion process is performed to diffuse the n-type impurities, and as shown in FIG. 8 (main part sectional view), the main surface of the p-type semiconductor region 6 is an n + -type semiconductor that is a source region. Region 7 is formed. This thermal diffusion process is performed in an atmosphere of a temperature of about 950 [° C.]. In this process, vertical MOS
The FET Qn is almost completed.

Next, an interlayer insulating film 8 is formed on the entire main surface of the substrate including the main surface of the gate electrode 5. The interlayer insulating film 8 is formed of, for example, a silicon oxide film deposited by the CVD method.

Next, a connection hole 9 is formed in the interlayer insulating film 8 to expose the surface of a part of each of the n + type semiconductor region 7 and the p type semiconductor region 6.

Next, as shown in FIG. 9 (main part sectional view), on the main surface of the interlayer insulating film 8 including the surface of a part of each of the n + type semiconductor region 7 and the p type semiconductor region 6. The wiring 10 is formed on the entire surface. The wiring 10 is formed of, for example, an aluminum film or an aluminum alloy film.

Next, a final protective film (not shown) is formed on the main surface of the wiring 10. The final protective film is formed of, for example, a polyimide resin film.

Next, the back surface of the n + type semiconductor substrate 1 is ground by, for example, a polishing technique to reduce the thickness of the n + type semiconductor substrate 1. In this step, the extrinsic gettering layer 3 is removed.

Next, an electrode 11 is formed on the back surface of the n + type semiconductor substrate 1. The electrode 11 is, for example, nickel (Ni)
It is formed of a laminated film in which a film, a titanium (Ti) film, a nickel (Ni) film, and a silver (Ag) film are sequentially laminated. By this step, the semiconductor device having the vertical MOSFET Qn shown in FIG. 6 is almost completed.

As described above, the manufacturing process of the semiconductor device having the vertical MOSFET Qn includes several heat treatment steps, but the interstitial oxygen concentration of the n + type semiconductor substrate 1 is 9 times.
Since it is set to × 10 ¹⁷ [atoms / cm ³ ], the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced, and the occurrence of thermal stress dislocations inside the bulk crystal during the heat treatment step in the manufacturing process. Can be prevented. As a result, the pn junction formed by the source region (n + type semiconductor region 7) and the channel forming region (p type semiconductor region 6), the channel forming region (p type semiconductor region 6), and the drain region (n type epitaxial layer) 2) It is possible to prevent the deterioration of the junction characteristics of the pn junction formed by and.

Further, since the interstitial oxygen concentration of the n + type semiconductor substrate 1 is set to 9 × 10 ¹⁷ [atoms / cm ³ ], the amount of crystal defects inside the bulk crystal due to oxygen precipitation can be reduced and the manufacturing process It is possible to prevent dislocation from occurring on the surface of the n-type epitaxial layer 2 in the heat treatment step. As a result, it is possible to prevent the breakdown voltage of the gate insulating film (thermal silicon oxide film) 4 formed on the surface of the n-type epitaxial layer 2 from being deteriorated.

Further, since the extrinsic gettering layer 3 for capturing heavy metal contaminants is formed on the back surface of the n + type semiconductor substrate 1, it is possible to prevent the deterioration of the insulation resistance of the gate insulating film 4 due to the heavy metal contaminants. You can

The vertical MOSFET Qn has the structure shown in FIG.
The VD-ID characteristic of the data A shown in 1 (voltage-current characteristic diagram) can be obtained, and the amount of leak current between the source region and the drain region can be reduced. In addition, the vertical MOSFET Qn
Shows the VG-IG characteristic like the data C shown in FIG. 12 (voltage-current characteristic diagram), and the amount of leak current of the gate insulating film 4 can be reduced. The data B shown in FIG. 11 is the VD-ID characteristic when a conventional semiconductor wafer is used. Further, data D shown in FIG. 12 is a VG-IG characteristic when a conventional semiconductor wafer is used.

As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0066] For example, the present invention is, IGBT (I nsulated
It can be applied to a semiconductor device having a G ate B ipolar T ransistor).

Further, the present invention can be applied to a semiconductor device having a barrier Kip diode element.

[0068]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor wafer composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon, it is possible to prevent thermal stress dislocations occurring inside the bulk crystal.

In a semiconductor wafer composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on the main surface thereof, generation of thermal stress dislocations occurring inside the bulk crystal can be prevented and at the same time. It is possible to prevent dislocations from occurring on the surface of the epitaxial layer.

A pn junction composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on the main surface thereof, and composed of the epitaxial layer and a semiconductor region formed in the epitaxial layer. In a semiconductor device having a semiconductor element provided with, it is possible to prevent deterioration of the junction characteristics at the pn junction of the semiconductor element.

In the method of manufacturing a semiconductor device, it is possible to prevent the insulation resistance of the thermal oxide film formed on the surface of the epitaxial layer from deteriorating.

[Brief description of drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor wafer that is Embodiment 1 of the present invention.

FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor wafer.

FIG. 3 is a schematic plan view of the semiconductor wafer.

FIG. 4 is a schematic sectional view of the semiconductor wafer.

FIG. 5 is a cross-sectional view of essential parts showing a schematic configuration of a semiconductor wafer that is Embodiment 2 of the present invention.

FIG. 6 is a cross-sectional view of an essential part showing a schematic configuration of a semiconductor device having a vertical MOSFET that is Embodiment 3 of the present invention.

FIG. 7 is a cross-sectional view of a main part for explaining a method for manufacturing the semiconductor device.

FIG. 8 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor device.

FIG. 9 is a cross-sectional view of a main part for explaining a method for manufacturing the semiconductor device.

FIG. 10 is a vertical MOSFE mounted on the semiconductor device.
The voltage-current characteristic view of T.

FIG. 11 is a vertical MOSFE mounted on the semiconductor device.
The voltage-current characteristic view of T.

FIG. 12 is a schematic plan view of a semiconductor wafer for explaining conventional problems.

FIG. 13 is a schematic cross-sectional view of a semiconductor wafer for explaining conventional problems.

[Explanation of symbols]

1 ... n + type semiconductor substrate, 2 ... n type epitaxial layer, 3 ...
Extrinsic gettering layer, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... P-type semiconductor region, 7 ... N + type semiconductor region, 8 ... Interlayer insulating film, 9 ... Connection hole, 10 ... Wiring,
11 ... Electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Rei Meguro 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Eiji Yanokura, Kodaira, Kodaira-shi, Tokyo 5-20-1 Honmachi, Ltd. Semiconductor Division, Hitachi, Ltd. (72) Inventor Tetsuro Iijima 5-2-1, Josui Honcho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi Ltd.

Claims (6)

[Claims] 1. A semiconductor wafer composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon, wherein the interstitial oxygen concentration of the semiconductor substrate is set to 9 × 10 ¹⁷ [atoms / cm ³ ] or less. Semiconductor wafer. 2. A semiconductor wafer composed of a semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on the main surface thereof, wherein the interstitial oxygen concentration of the semiconductor substrate is 9 × 10 ¹⁷ [atoms]. / Cm ³ ], the semiconductor wafer is characterized by being set below. 3. The semiconductor wafer according to claim 1, wherein an extrinsic gettering layer for capturing heavy metal contaminants is formed on the back surface of the semiconductor substrate, which is opposite to the main surface of the semiconductor substrate. 4. The semiconductor wafer according to claim 3, wherein the extrinsic gettering layer is formed of a polycrystalline silicon film, a silicon nitride film, or a crystal defect layer. 5. A semiconductor substrate in which arsenic is introduced into single crystal silicon and an epitaxial layer formed on the main surface of the semiconductor substrate. The epitaxial layer and a semiconductor region formed in the epitaxial layer. A semiconductor device having a semiconductor element having a pn junction, wherein the interstitial oxygen concentration of the semiconductor substrate is set to 9 × 10 ¹⁷ [atoms / cm ³ ] or less. 6. A method for manufacturing a semiconductor device, wherein arsenic is introduced into single crystal silicon and the interstitial oxygen concentration is 9 ×.
10 ¹⁷ [atoms / cm ³ ] or less, a step of preparing a semiconductor wafer composed of a semiconductor substrate and an epitaxial layer formed on the main surface thereof, and a thermal oxide film formed on the main surface of the epitaxial layer. And a step of forming the semiconductor device.