JPH081979B2 - Partial gold specification Solder plating printed wiring board - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder-plated printed wiring board with partial gold specifications in which a gold-plated circuit pattern and a solder-plated circuit pattern are mixed.

[0002]

2. Description of the Related Art When an IC tester, a probe card or the like is required to have particularly high reliability, or when rusting is particularly disliked, the entire surface of a printed wiring board may be plated with gold. However, in order to reduce the consumption of gold and reduce the cost, it is considered that only the minimum necessary circuit pattern is gold-plated and the remaining circuit patterns are solder-plated for fusing finish. Here, fusing is a process of forming a circuit by using solder plating as an etching resist and then melting the solder by heat treatment to homogenize the alloy. Is done in.

In this case, conventionally, a circuit pattern was first formed by gold plating, and then a predetermined pattern was solder-plated. FIG. 6 is a drawing of this conventional manufacturing process, and FIGS.
Is an explanatory diagram during each manufacturing process, and FIGS. 10 and 11 are explanatory diagrams of a finished state.

In FIG. 7, reference numeral 10 is a substrate made of an insulating material, and a copper plating layer 12 is formed over the entire surface of the substrate (step 100 in FIG. 6). The surface of the copper plating layer 12 is polished and washed (step 10
2) The resist 14 is applied so as to cover all the other regions, leaving only the gold-plated circuit pattern (step 104). Then, by immersing in the gold plating solution, the gold plating layer 16 is formed on the portion where the resist 14 is not applied, as shown in FIG. 8 (step 106).

After removing the resist 14 (step 108), a resist 18 is applied so as to cover the gold plating layer 16 and masking is performed (step 110).
At this time, the resist 18 is prevented from adhering to the joint portion with the later-described solder plating layer 20 of the gold plating layer 16. In this way, the pattern of the gold plating layer 16 is masked with the resist 18 and immersed in the solder plating solution to form the solder plating layer 20 on the portion not covered with the resist 18 (step 112). Then, after removing the resist 18 (step 114), etching is performed using the solder plating layer 20 itself as an etching resist to form a circuit (step 116). Next, fusing is performed (step 118). In this step, the entire solder plating layer 20 is melted by heating the whole.

[0006]

[Problems of the prior art] In the above manufacturing process,
The masking resist 18 in step 110 is
The adhesion with the gold plating layer 16 is weak and the resist 18 is easily peeled off. Therefore, when the solder plating layer 20 is formed, the solder plating solution penetrates between the resist 18 and the gold plating layer 16, and the end portion of the gold plating layer 16 is solder-plated as shown in FIG. As a result, when the resist 18 is peeled off and the fusing is performed, the molten solder of the solder plating layer 20 is changed to the gold plating layer 1 as shown by an arrow A in FIG.
Overflows to 6. Further, due to the outflow of the solder plating layer 20, a part of the solder plating layer 20 is depressed as shown by an arrow B in FIG. For this reason, there arise problems that the gold plating layer 16 and the solder plating layer 20 are not smooth, and that the precision of the gold plating circuit pattern dimension is deteriorated.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and the solder plating layer flows out onto the gold plating layer during fusing, or the surface of the solder plating layer is dented. It is an object of the present invention to provide a solder-plated printed wiring board with partial gold specifications, which does not deteriorate the smoothness of layers or reduce the dimensional accuracy of circuit patterns.

[0008]

According to the present invention, the purpose is to provide a copper plating layer formed on a substrate, a partial gold plating layer formed on the copper plating layer, and a part of the gold plating layer overlapping the gold plating layer. In a partial gold-spec solder-plated printed wiring board having a solder-plated layer joined to, a partial-gold-spec solder-plated printed wiring board is characterized in that an underlying copper plating is formed under the solder plating layer. To be achieved.

[0009]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention, FIG.
4 to 4 are explanatory views during the process, and FIG. 5 is an explanatory view of the finished state. In these figures, reference numeral 10 is a substrate, 12 is a copper plating layer, and 16 is a gold plating layer.
00 to 108 are the same as those in FIGS. In the present invention, after the gold plating layer 16 is formed, a thin base copper plating process is performed on the entire surface of the substrate 10 (step 20).
0), the base copper plating layer 30 is formed. After polishing and cleaning the surface of the underlying copper plating layer 30 (step 20
2), the portion other than the circuit pattern to be the solder plating layer is masked with the resist 32 (step 204). Then, when the solder plating process is performed by placing the solder plating solution in the solder plating solution (step 206), as shown in FIG.
Is formed.

When the resist 32 is peeled from the state of FIG. 3 (step 208) and etching is performed, the solder plating layer 34 acts as a resist, resulting in the state shown in FIG. 4 (step 210). Here, the etching of the base copper plating layer 30 penetrates to the inside of the solder plating layer 34 rather than the edge of the solder plating layer 34. That is, the solder plating layer 3
4 overhangs on the underlying copper plating layer 30. When the overhanging portion C is melted by the fusing treatment (step 212), the surface tension of the solder itself is large, so that the overhanging portion C does not spread on the surface of the gold plating layer 16 and stops at the edge of the underlying copper plating layer 30 as shown in FIG.

[0011]

【The invention's effect】

As described above, according to the present invention, after the partial gold plating process is performed, the entire surface of the substrate is subjected to the thin copper plating, that is, the base copper plating process. It does not flow into the layer. Therefore, the smoothness of the solder plating layer and the gold plating layer becomes good, and the accuracy of the circuit pattern dimension can be increased.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention.

FIG. 2 is an explanatory view during the manufacturing process.

[FIG. 3] Similarly, an explanatory view during the manufacturing process.

[FIG. 4] Similarly, an explanatory view during the manufacturing process.

FIG. 5 is an explanatory view showing a finished state.

FIG. 6 is a conventional manufacturing process diagram.

FIG. 7 is an explanatory view during the manufacturing process.

FIG. 8 is an explanatory diagram of the same manufacturing process

FIG. 9 is an explanatory view of the same manufacturing process

FIG. 10 Illustration of the finished state

FIG. 11 is an explanatory diagram of a finished state

[Explanation of reference numerals] 10 substrate 12 copper plating layer 16 gold plating layer 30 base copper plating layer 34 solder plating layer

Claims (1)

[Claims] 1. A copper plating layer formed on a base material, a partial gold plating layer formed on the copper plating layer, and a solder plating layer joined so as to partially overlap the gold plating layer. A solder plating printed wiring board having partial gold specifications, wherein a copper undercoat is formed under the solder plating layer.