JPH081928B2 - Method for forming connection wiring structure of multilayer wiring - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection wiring structure for multilayer wiring and a method for forming the same, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a multilayer wiring structure. is there.

[Prior art]

In recent years, after the completion of the LSI, the technology of correcting defective parts and changing logic by cutting and connecting part of the wiring inside the chip in the state of wafer or chip has become more and more important. There is.

For this purpose, the present applicant has proposed in Japanese Patent Application No. 61-70979 a wiring connection method for LSI by combining an ion beam technology and a laser CVD technology. According to this method, for example, after the completion of an LSI having a two-layer wiring structure, the first layer wirings are connected for the purpose of correcting a defective portion or changing the logic. In this case, the wiring of the uppermost layer is usually laid out widely for the supply of power supply current, so that a connection hole penetrating the wiring of the uppermost layer to reach the lower layer wiring is provided, and the connection wiring is provided through this connection hole. There is a need. For this purpose, first of all, Focused Ion Beam (FIB)
The uppermost insulating film, the second layer wiring, and the interlayer insulating film between the second layer wiring and the first layer wiring are processed by irradiation to form a connection hole, and a first layer is formed in this connection hole. Part of the surface of the eye wiring is exposed. Next, for example, after forming an insulating film such as a SiO ₂ film on the entire surface, this insulating film is patterned by using photolithography and etching techniques, and the insulating film is left only in the vicinity of the connection hole. Next, the insulating film at the bottom of the connection hole is selectively removed by etching, and the surface of the first layer wiring is partially exposed again in the connection hole. Next, a metal is selectively deposited by laser CVD to form connection wirings connecting the first layer wirings through the connection holes. In this case, since the connection wiring is insulated from the second layer wiring by the insulating film formed in the connection hole, a short circuit between the first layer wiring and the second layer wiring is prevented.

[Problems to be solved by the invention]

However, the technique proposed in Japanese Patent Application No. 61-70979 requires photolithography and etching steps to form the insulating film only in the vicinity of the connection hole, and the first and second layers are required. There is a problem that a process for preventing a short circuit between wirings is complicated.

An object of the present invention is to provide a technique capable of forming a connection wiring without causing a short circuit between a lower layer wiring and an upper layer wiring in a multilayer wiring structure.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, according to the first invention, the step of forming a connection hole reaching the lower layer wiring by ion beam irradiation, the step of forming the connection wiring by laser CVD, and the step of forming a groove near the connection hole by ion beam irradiation. And a step of electrically separating the upper layer wiring and the connection wiring.

[Action]

According to the above-mentioned means in the first aspect of the invention, the conductor portion for forming the upper layer wiring, which is electrically connected to the connection wiring through the connection hole, can be electrically separated from the upper layer wiring, and contact between the connection wiring and the upper layer wiring can be prevented. Therefore, the connection wiring can be formed by a simple process without causing a short circuit between the lower layer wiring and the upper layer wiring.

〔Example〕

A reference example will be described below with reference to FIGS. 1 to 6 in describing an embodiment according to FIGS. 7 and 8 of the present invention.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows an LS having a two-layer wiring structure according to an embodiment of the present invention.
FIG. 2 is a plan view showing I, and FIG. 2 is an enlarged cross-sectional view taken along the line XX in FIG.

As shown in FIGS. 1 and 2, the LSI according to this embodiment
₂ , an interlayer insulating film 2 such as a SiO ₂ film is formed on a semiconductor chip 1 such as a silicon chip on which transistors and the like (not shown) are formed, and an aluminum film such as an aluminum film is formed on the interlayer insulating film 2. The first layer wirings (lower layer wirings) 3 ₁ and 3 ₂ are provided. This wiring 3 ₁ ,
3 on _2, for example an interlayer insulating film 4 such as a SiO ₂ film is provided, the second layer wiring, such as on the interlayer insulating film 4, for example an aluminum film (upper wiring) 5 _1, 5 ₂ It is provided. The wire 5 _1, 5 _2, for example constitutes a power supply wiring of the power supply current for supply have been widely laid on the surface of the interlayer insulating film 4. Is provided (not shown in Figure 1) the wiring 5 _1, 5 ₂ further insulating film 6 is formed on. Connection holes 7 ₁ and 7 ₂ are provided so as to penetrate through the insulating film 6, the wirings 5 ₁ and 5 ₂ and the interlayer insulating film 4, and between the lower layer wirings 3 ₁ and 3 ₂ through these connection holes 7 ₁ and 7 _2. A connection wiring 8 for connecting the above is provided. Then, with this connection wiring 8, for example, the defect found after the completion of the LSI is repaired (or the logic is changed). The connection holes 7 ₁ and 7 ₂ may be vertical connection holes or tapered connection holes. The connection wiring 8
Is composed of a metal film of tungsten, molybdenum, cadmium, aluminum or the like selectively formed by laser CVD, for example.

_On the surfaces of the second layer wirings 5 ₁ and 5 ₂ exposed in the connection holes 7 ₁ and 7 ₂ , an insulating film such as alumina (Al ₂ O ₃ ) formed by converting the surface into an insulator is formed. 9 is provided to prevent contact between the connection wiring 8 and the second layer wirings 5 ₁ and 5 ₂ . Therefore, the connection wiring 8 can be formed without causing a short circuit between the first layer wirings 3 ₁ and 3 ₂ and the second layer wirings 5 ₁ and 5 ₂ . The thickness of the insulating film 9 is selected so as to obtain the necessary dielectric breakdown strength according to the potential difference between the first layer wirings 3 ₁ and 3 ₂ and the second layer wirings 5 ₁ and 5 _2. . For example, when the insulating film 9 is made of alumina (withstand voltage is about 500 V / μm) and the potential difference is 5 V, the thickness can be set to, for example, 1000 to 5000 Å.

Next, a method of manufacturing the LSI according to the present embodiment configured as described above will be described.

As shown in FIG. 3, first, after forming a transistor (not shown) on the semiconductor chip 1, the interlayer insulating film 2, the first layer wirings 3 ₁ and 3 ₂ , the interlayer insulating film 4, the second layer are formed. line 5 _1, 5 to form a ₂ and the insulating film 6 to complete the LSI by. Then, consider a case where a defective portion of the wiring is found and repaired. Therefore, for example, by using an ion beam processing apparatus as shown in FIG. 6 proposed in Japanese Patent Application No. 61-70979, a focused ion beam 10 (first Connection hole by irradiating (Fig. 3)
7 ₁ and 7 ₂ are formed. The details of this ion beam processing method will be described below. In FIG. 6, first, the lid 12 of the preliminary exhaust chamber 11 constituting the sample exchange chamber is opened, and the above-mentioned semiconductor chip 1 is placed on the stage 14 on the stage 13. Next, close the lid 12 and open the valve 15 to open the vacuum pump.
The preliminary evacuation chamber 11 is evacuated by 16 to a vacuum. After that, the gate valve 17 is opened, and the stage 14 is transferred onto the XY stage 19 in the vacuum container 18 that has been evacuated in advance by the vacuum pump 18. Reference numeral 20 is a valve, which is normally in an open state. Next, after closing the gate valve 17, the inside of the vacuum container 18 is sufficiently evacuated. Next, a high-brightness ion source 22 such as a liquid metal ion source such as gallium (Ga) provided in an ion beam column 21 provided in the upper part of the vacuum container 18 is installed in the lower part thereof. The ion beam 10 extracted by the extraction electrode 23 is focused and deflected through the electrostatic lens 24, the blanking electrode 25, the deflector electrode 26, etc., and is irradiated onto the semiconductor chip 1. Next, the secondary electrons generated by the irradiation of the ion beam 10 are detected by the secondary electron detector D, and the XY stage is observed while observing the scanning ion beam image by the secondary electron signal on the monitor 28 of the deflection electrode power source 27. 19 is moved to detect the places on the semiconductor chip 1 where the connection holes 7 ₁ , 7 ₂ are to be formed. Then the third
As shown in the figure, the connection holes 7 ₁ and 7 ₂ are formed by irradiating the ion beam 10 only on the places where the connection holes 7 ₁ and 7 ₂ are to be formed. Then, the semiconductor chip 1 is once taken out of the ion beam processing apparatus.

Next, the semiconductor chip 1 is transferred into, for example, an anodic oxidation device (not shown), and the connection hole formed as described above.
The surfaces of the second-layer wirings 5 ₁ and 5 ₂ exposed on 7 ₁ and 7 ₂ are anodized, and as shown in FIG. 4, for example, alumina (Al ₂ O ₃ )
An insulating film 9 such as a film is formed in a self-aligned manner with respect to the connection holes 7 ₁ and 7 ₂ . In addition, at the time of this anodization, the connection hole
7 _1, 7 first layer of wiring in ₂ 3 _1, 3 ₂ insulation on the surface film 9 is formed. Since the surfaces of the second layer wirings 5 ₁ and 5 ₂ exposed in the connection holes 7 ₁ and 7 ₂ are made into an insulating material in this manner, the first layer wirings 3 ₁ and 3 ₂ and the second layer wirings 5 ₁ and 5 ₂ are formed. _It is possible to prevent short circuit with ₁ and 5 ₂ by a simple process without requiring a complicated process such as photolithography.
As a method of forming the alumina film, a method such as O ₂ plasma oxidation (for example, “vacuum”, Vol. 27, No. 12, p. 901, 1984) other than the anodization is used. You can also Further, when a material other than aluminum, for example, a refractory metal such as tungsten or molybdenum is used as the wiring material, an oxide of these metals can be formed by performing low-temperature heat treatment while irradiating ozone, Thereby, the insulating film 9 can be formed. When the connection holes 7 ₁ and 7 ₂ are formed, as a result of the surfaces of the first layer wirings 3 ₁ and 3 ₂ being irradiated with an ion beam, the inner peripheral surfaces of the connection holes 7 ₁ and 7 ₂ are made of, for example, aluminum. Is the third
Attach as shown by the dashed line in the figure
Although the first layer wirings 3 ₁ and 3 ₂ and the second layer wirings 5 ₁ and 5 ₂ may be short-circuited at the stage of forming 7 ₁ and 7 ₂ , the connection holes 7 ₁ and 7 ₂ This problem can be solved by completely converting the aluminum adhering to the inner peripheral surface into an alumina by the above-mentioned anodic oxidation.

Next, during the above-described anodic oxidation, the insulating film 9 formed on the surfaces of the first layer wirings 3 ₁ and 3 ₂ in the connection holes 7 ₁ and 7 ₂ is selectively removed by, for example, laser light irradiation. as shown in FIG. 5, to expose these first layer wiring 3 _1, 3 ₂ of the surface partially.

Next, the semiconductor chip 1 is placed again on the stage 14 on the XY stage 13 shown in FIG.
Transfer to the XY stage 30 in the vacuum container 29 of the D device. Next, the semiconductor chip 1 is moved by the XY stage 30 to the irradiation position of the laser light 32 oscillated by a laser oscillator 31 such as an argon laser, and the wiring correction position is aligned. Next, the laser light 32 is reflected by the dichroic mirror 34 through the shutter 33, further condensed by the objective lens 35, and irradiated through the window 36 provided in the vacuum container 29 to the wiring correction location. At this time, the position of the wiring correction point can be adjusted while observing the correction point via the irradiation optical system 37, the half mirror 38, the laser light cut filter 39, the prism 40, the eyepiece 41, and the like. There is. Next, the valve 42 is opened, and the cylinder 43 connected to the vacuum container 29 and containing the reaction gas composed of an organometallic compound such as Mo (CO) ₆ or W (CO) ₆ is vacuum container.
A reaction gas is introduced into 29, and at the same time, the valve 44 is opened to introduce the inert gas from the cylinder 45 containing the inert gas. In this state, the laser light 29 is selectively irradiated to the wiring correction portion to decompose the reaction gas, and the metal is selectively deposited on the irradiation portion of the laser light 32. As a result, as shown in FIGS. 1 and 2,
A connection wiring 8 for connecting the first layer wirings 3 ₁ , 3 ₂ is formed through the connection holes 7 ₁ , 7 ₂ . In this case, a single scan of the laser beam 32 can deposit a metal film having a thickness of, for example, about 0.5 to 1.0 μm.

In this embodiment, as shown in FIGS. 7 and 8, for example, the second layer wiring (upper layer wiring) 5 ₁ , 5 ₂ around the connection holes 7 ₁ , 7 ₂ is irradiated with, for example, an ion beam. Thus, the groove 46 is formed by selectively removing it together with the insulating film 6 thereon. As a result, the second-layer wiring constituent conductor portions which are electrically connected to the connection wiring 8 through the connection holes 7 ₁ and 7 ₂ are connected to the second-layer wirings 5 ₁ and 5 _2.
Can be electrically separated from each other and contact between the connection wiring 8 and the second layer wirings 5 ₁ and 5 ₂ can be prevented,
First layer wiring (lower layer wiring) 3 ₁ , 3 ₂ and second layer wiring 5 ₁ ,
Short circuit with 5 ₂ can be prevented.

As described above, the present invention has been specifically described based on the examples.
It is needless to say that the present invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention.

For example, in the above-described embodiment, the case where the defective portion is corrected in the state of the semiconductor chip 1 has been described, but it is also possible to correct the defective portion in the state of the wafer before being cut into the chips. . Further, in the above-described embodiment, the case where the wiring is modified or the logic is changed after the completion of the LSI has been described, but it is also possible to form the wiring for realizing the desired logic in the master slice or the gate array, for example. The present invention can be applied.
Further, the present invention can be applied to a case where wirings of the same layer or different layers are formed in the middle of a manufacturing process of an LSI having multilayer wirings, for example. Furthermore, the present invention can be applied to, for example, a printed circuit board having a multilayer wiring structure.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

That is, according to the first aspect of the present invention, it is possible to electrically separate the upper wiring from the upper wiring from the upper wiring, which is electrically connected to the connection wiring through the connection hole, and prevent contact between the connection wiring and the upper wiring. Therefore, the connection wiring can be formed by a simple process without causing a short circuit between the lower layer wiring and the upper layer wiring.

[Brief description of drawings]

FIG. 1 is a plan view showing an LSI having a two-layer wiring structure which is a reference example of the present invention, FIG. 2 is an enlarged sectional view taken along line XX of FIG. 1, and FIGS. 1 is a cross-sectional view for explaining the method of manufacturing the LSI shown in FIGS. 1 and 2 in the order of steps, FIG. 6 is a view showing an ion beam processing apparatus and a laser CVD apparatus, and FIG. FIG. 8 is a plan view showing an LSI having a two-layer wiring structure for preventing a short circuit between the first-layer wiring and the second-layer wiring, which is one embodiment of the present invention. It is an expanded sectional view along. In the figure, 1 ...... semiconductor chip, 3 _1, 3 _2, 5 _1, 5 ₂ ...... wires,
7 ₁ , 7 ₂ ...... Connection hole, 8 ...... Connection wiring, 9 ...... Insulation film, 10
…… Ion beam, 32 …… laser light, 46 …… groove.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hiroshi Yamaguchi Inventor Hiroshi Yamaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Production Engineering Research Laboratory, Hitachi, Ltd. (72) Inventor Mikio Hongo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (56) References JP-A-60-70743 (JP, A) JP-A-56-67938 (JP, A) JP-A-61-224342 (JP, A) JP-A-SHO 63-86455 (JP, A)

Claims (5)

[Claims] 1. A method for forming a connection wiring structure of a multi-layer wiring having a connection wiring connected to a lower layer wiring through a connection hole provided through an upper layer wiring in a plurality of layers of wiring separated from each other by an insulating film. There is a step of forming the connection hole reaching the lower layer wiring by ion beam irradiation, a step of forming the connection wiring by laser CVD, and forming a groove near the connection hole by ion beam irradiation to form the upper layer wiring. And a step of electrically separating the connection wiring from each other, and a method for forming a connection wiring structure of multilayer wiring. 2. The method for forming a connection wiring structure of multi-layer wiring according to claim 1, wherein the wiring of the plurality of layers is a double-layer wiring. 3. The method for forming a connection wiring structure of multilayer wiring according to claim 1 or 2, wherein said wiring is an aluminum wiring. 4. The formation of a connection wiring structure of multi-layer wiring according to claim 1, 2 or 3, wherein the connection wiring is made of a molybdenum film, a tungsten film, a cadmium film or an aluminum film. Method. 5. The multi-layer wiring according to claim 1, wherein the connection wiring is formed by the laser CVD using an organometallic compound. Method of forming connection wiring structure.