JP2708560B2 - Method for forming connection wiring to semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring on a surface of a semiconductor device and a semiconductor device having the wiring formed thereon, and particularly to a defect partially present in a prototyped semiconductor device. Location and cause of the
Alternatively, the present invention relates to a method for forming a subsequent wiring on a semiconductor device suitable for repairing a defect.

[Conventional technology]

2. Description of the Related Art In order to achieve higher performance and higher speed of semiconductor devices, miniaturization and higher integration of semiconductor devices have been performed. As a result, the development of semiconductor devices has become more difficult, leading to a longer development period. Here, the defective part on the chip that does not operate sufficiently with the conventional design is specified, the wiring existing in the part is cut, the wiring is arbitrarily arranged, the defective wiring is repaired, and the provisional is temporarily determined. If a semiconductor device capable of obtaining a complete operation is manufactured, subsequent characteristic evaluation and design change can be performed quickly.

On the other hand, as the prior art, for example, Semiconductor World (Semiconductor World), September 1987, pp27-
As described on page 32, FIB (focused ion beam)
A method is described in which a passivation of the SI chip surface and a hole are formed in the interlayer insulating film to expose the wiring, and then a metal gas is formed by FIBCVD by introducing a CVD gas.

Also, The Laser Society of Japan, Vol. 12, No. 2, April 1987, p.
Pages 1 to 6 introduce a method of removing the passivation film on the LSI chip surface by ablation using laser light to form via holes, and connecting between bias holes with Mo wiring formed by laser CVD. I have.

Further, JP-A-63-100746 or JP-A-63-16424
As disclosed in No. 0, a method is disclosed in which a hole is formed in a passivation film and an interlayer insulating film, and a connection is made by wiring formed by laser CVD.

[Problems to be solved by the invention]

In the first prior art, although a wiring having a width of 1 μm or less can be formed, the forming speed is extremely low and the wiring resistance is high.
In order to lay a wiring on an actual semiconductor device, it is necessary to form a wiring material having sufficiently low resistance at a high speed. Even if only this viewpoint is used, the first conventional technique is not used. Not applicable. Further, it is required that the adhesion strength between the wiring and the base be sufficient, that a wiring shape having a sufficient sectional area be obtained, and that the connection resistance with the Al wiring in the semiconductor device be sufficiently low.

Next, the second prior art shows that a low-resistance wiring can be formed at a higher speed by laser CVD as compared with the first prior art. It is difficult to form the deep hole with high precision. Further, it is required that the connection resistance with the Al wiring in the semiconductor device is sufficiently small.

On the other hand, in the third and fourth prior arts, a deep hole is formed with high precision using a focused ion beam process in a passivation film and an interlayer insulating film of a semiconductor device having a multilayer wiring, and then a low-resistance wiring is formed by laser CVD. Are disclosed that can be formed at high speed and connected. However, the third and fourth prior arts still have a problem in that the connection resistance between the Al wiring in the semiconductor device and the wiring formed by laser CVD is sufficiently reduced.

The object of the present invention is to form a deep hole for connection with high precision and high speed even in the lowermost wiring layer of a semiconductor device having a multilayer wiring, and to form a low resistance wiring in which connection holes are formed by laser CVD. High-speed connection and the Al in the semiconductor device
It is an object of the present invention to provide a method for forming a connection wiring to a semiconductor device which can sufficiently reduce the connection resistance with the wiring.

[Means for solving the problem]

In order to achieve the above object, focused ion beam processing is used for forming the connection hole. In order to increase the processing speed, use a thick beam with a large current or use an assist gas
After exposing the surface of the wiring, a region narrower than a region processed with a thick beam is subjected to finishing with a small current and a focused ion beam. Due to this, when processed with a thick focused ion beam, it was sputtered from the side wall of the hole and reattached to the bottom of the hole
An insulator such as SiO ₂ or a reaction product film is completely removed. Then, after forming a Cr thin film on the entire chip,
The inside of the hole is filled with metal by CVD, and the holes are connected with metal wiring formed by laser CVD. By processing this Cr thin film and the thin beam, the connection resistance between the embedded metal can be reduced, and the Cr thin film improves the adhesiveness of the metal wiring formed thereon, and increases the speed of formation. The transmission of the laser beam to the lower layer can be prevented.

Next, the resistance of the wiring can be reduced by laser annealing the wiring formed by laser CVD in a vacuum.

After that, by removing unnecessary Cr thin film, the lowermost layer of the semiconductor device having a multilayer wiring layer is also drilled at high speed and high precision to perform connection with low connection resistance and high speed formation of low resistance wiring. be able to.

[Action]

When processing with a thick beam that can provide a large current to speed up the formation of the connection hole, the ion beam itself has a Gaussian distribution, so the skirt portion of the beam sputters the side wall of the connection hole Therefore, the insulator such as SiO ₂ forming the side wall is blown into the hole,
An insulating film such as SiO ₂ is re-attached to the exposed Al wiring surface. When an assist gas is used, a reaction product film is formed on the surface of the Al wiring. For this reason, laser CVD
Therefore, even if the metal is completely embedded in the connection hole, the connection resistance varies widely. Then, after forming a connection hole with a thick beam, the bottom of the hole is slightly processed with a thin beam to remove the redeposition film, thereby realizing a low-resistance connection with a metal embedded by laser CVD.

Next, after forming a thin Cr film on the semiconductor device surface,
Metal is buried inside the connection hole by CVD. The Cr film reduces the reflectance of the exposed Al wiring surface, reduces the laser output required for metal deposition, and prevents the Al wiring from being alloyed with the deposited metal, thereby realizing low-resistance connection.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of an ion beam processing apparatus suitable for forming a connection hole in the wiring forming method of the present invention. When forming a focused ion beam, a high-brightness liquid metal ion source or the like is used as the ion source 7, and the ion beam 1 extracted therefrom is focused by lenses 11, 12, and 13, and a wafer 17 as a workpiece 17 is formed. Irradiate and process. At this time, a control electrode 8 for controlling beam emission from the ion source 7, an extraction electrode 9 for applying a voltage for extracting a beam, a defining aperture 10 for determining a beam current and a beam diameter on the workpiece 17, a beam Blanking electrode 14 and beam blanking aperture for turning on and off
15, further pass through a deflector / stigma electrode 16 for deflection and shape adjustment of the beam,
Give shape and direction. It is very useful to use two or more types of beam diameters depending on the purpose in ion beam processing.
Punch one or more apertures and switch between them. Reference numeral 21 denotes a deflector controller having a CRT for displaying a secondary particle image based on a signal from the secondary particle detector 20. 22 is C
This is a means for setting a processing area on the RT. 23 is a table controller. Reference numeral 24 denotes a control power supply for controlling the control electrode 8, the extraction electrode 9, and the electrostatic lenses 11, 12, and 13. Reference numeral 25 denotes a blanking controller that controls the blanking electrode 14. Reference numeral 26 denotes a computer which controls the control power supply 24, the blanking controller 25, the deflector controller 21, and the table controller 23, which controls each controller based on the processing area setting means 22 and other control data.

Here, a case where two large and small holes are formed in the defining aperture 10 will be considered. First, the defining aperture 10 is set so that the large hole enters the optical axis of the ion beam 1.
By setting, a large current can be obtained and the processing speed is high, but the focused beam diameter also becomes large. For example, if the aperture diameter is
In the case of 800 μm, an ion beam with an obtained focusing diameter of about 1 μm and a current of 4 nA can be obtained. This large current / thick beam is scanned in the Y-axis direction by the deflector electrode 16 and the blanking electrode 14 as shown in FIG. 2, then moved slightly in the X-axis direction, and then scanned again in the Y-axis direction. By repeating this from the beginning after scanning to the desired X-direction position, connection holes can be formed in the surface of the semiconductor device, for example, as shown in FIG. FIG. 3 shows a passivation film for exposing the surface of the lower wiring 33 from the gap between the upper Al wirings 31 and 32.
34, a case where a connection hole 36 is formed in the interlayer insulating film 35 is shown. Whether the surface of the Al wiring 33 is exposed can be detected by, for example, the secondary particle detector 20 shown in FIG.
An equivalent function can also be obtained by detecting the wavelength of the fluorescent light emitted by the ion beam 1, which is usually excited.
When the thickness of the Al wiring is about 1 μm, in order to surely expose the Al surface, when the Al wiring is processed about 0.1 to 0.2 μm,
Complete the connection hole formation.

However, the current density distribution of the focused ion beam is generally Gaussian, and the SiO ₂ particles 37 on the side walls sputtered by the ion beam 1 are exposed on the exposed Al wiring 33 at the starting point, the ending point, and the last several scans. To form a thin insulating film. For this reason, even if metal is completely produced in the connection hole 36 in a later process, a low connection resistance cannot be obtained. This is more remarkable as the connection hole is deeper.

Therefore, the defining aperture 10 is moved to position the ion beam optical axis so as to pass through the small hole. This results in a narrow beam with reduced current. For example, if the aperture diameter is 200 μm, an ion beam having a focused beam diameter of 0.1 μm and a current of 0.4 nA can be obtained. By employing a smaller aperture diameter, a smaller focusing diameter can also be obtained. As shown in FIG. 4, this narrow beam is used to scan an area narrower than the area scanned by the thick beam when forming the connection hole 36, and the Al wiring 33 whose surface is exposed as shown in FIG. Remove approximately 0.1 μm, including a very thin layer of SiO ₂ deposited on top. As a result, the insulating film adhered to the surface of the Al wiring 33 is completely removed, and a thin beam is applied only to the inside of the connection hole, so that no new insulating film is formed.

After forming all the connection holes of the parts that need to be connected, to perform sputter deposition while maintaining a high vacuum or maintaining an inert gas atmosphere so that an oxide film is not formed on the exposed Al wiring surface To form a 200-600 ° Cr film on the surface of the semiconductor device. This buffer film (Cr
Film), as disclosed in JP-A-63-100746 or JP-A-63-164240, is used when forming wiring by laser CVD.
This is for improving the adhesion of the VD wiring, preventing laser light transmission to the diffusion layer, etc., and making the wiring width uniform. For this purpose, passivation film (SiO ₂ film or SiN film) and
It is not limited to Cr as long as it has good adhesion to the wiring material formed thereon and low laser light reflectance.
o, W, etc. can be used.

Next, in FIG. 6, a suitable laser is used to fill the inside of the connection hole with metal and form wiring for connecting the connection holes.
1 shows an embodiment of a CVD apparatus. A laser beam 42 oscillated from an Ar laser oscillator 41 is expanded on a beam diameter by a beam expander 43, bent by a mirror 44, and condensed by an objective lens 46 constituting an optical system 45, and mounted on a stage 48 in a CVD chamber 47. Irradiation is performed through a laser light transmission window 50 onto a placed wafer 49 (possible chips). The ON / OFF of the laser beam 42 is performed by the shutter 51, and the adjustment of the laser output can be performed by, for example, the adjustment of the excitation current of the oscillator power supply or the continuous transmittance variable filter. Laser irradiation positioning and observation
This is performed by the TV camera 52 and the monitor 53. After the inside of the CVD chamber 47 is evacuated to, for example, about 10 ⁻⁷ Torr by a vacuum pump 54, a CVD material gas, for example, Mo (Co) contained in a container 55
₆ is introduced to a constant pressure. After that, the connection hole formed in the focused ion beam processing is aligned with the condensing position of the laser beam 42, and the shutter 51 is opened to irradiate the laser beam to bury the metal in the connection hole in the present embodiment. here,
Mo (Co) ₆ ) molybdenum carbonyl) is selected as a CVD material gas and introduced into the CVD chamber 47 at room temperature until the pressure becomes 0.1 Torr. The hole bottom is φ2 to the connection hole of 3-4μm mouth.
When the laser beam 42 focused to 2.5 μm is adjusted to 20 to 200 mW and irradiated, Mo is deposited inside the connection hole by thermal decomposition of Mo (Co) ₆ . It is known that the higher the laser output at this time, the lower the connection resistance between the Al wiring and Mo, but the worse the embedded shape.

Therefore, first, the laser output is adjusted to 100 mW and irradiation is performed for 0.5 seconds. The cross section at that time is, as shown in FIG. 7 (a), a Mo film 62 is formed inside the connection hole on the Cr film 61 formed on the chip surface and inside the connection hole. If the irradiation of 100 mW is continued as it is, the growth of the Mo film at the entrance of the connection hole is faster than at the bottom of the hole, leaving a cavity inside, and the Mo film spreads greatly around the hole due to heat conduction. Therefore, increase the laser output to 30
Fig. 7 (b) by adjusting to mW and continuing irradiation
As shown in the figure, the Mo film grows sequentially from the bottom of the hole and can be completely embedded. The embedding according to the above procedure, when the hole bottom dimension is 3 μm and the depth is 6 μm, the Al wiring 63-Cr film 61-Mo64
1 Ω or less can be obtained as the connection resistance. Generally, when the Al-Mo interface is exposed to a high temperature, a high resistance alloy is formed, and the Al-Mo
Although the Cr film 61 prevents the formation of a high-resistance alloy, the reflectance of the Al wiring surface is as high as about 90%, whereas the Cr film 61 has a reflectance of 50 to 50%. As low as 60%, the laser output can be reduced accordingly.
The interface of Al63-Cr61-Mo64 can be made low temperature. The underlying Si
The effect of heat on the substrate can be reduced.

After embedding all connection holes with Mo by the same procedure,
The stage 48 is driven between the holes to be connected while irradiating the laser beam 62 in the same Mo (Co) ₆ atmosphere and the wafer 49 is driven.
(Or a chip) is moved to form Mo wiring.

After forming all the Mo wiring, the Mo (C
o) Exhaust all ₆ and in a vacuum atmosphere higher than 102 ^-5 Torr,
A laser beam is irradiated onto the Mo wiring while moving along the same path as the path on which the wiring is formed. Thereby, the Mo wiring formed by laser CVD is annealed, and the wiring specific resistance can be reduced by removing impurities and improving the film quality.

Thereafter, the chip on which the wiring has been formed is transferred to the sputter etch chamber, and the Cr film formed on the entire chip surface is removed. At this time, the Cr film to be removed is 200 to 600 mm, and the thickness of the Mo wiring formed under normal conditions is 2000 to 10000 mm (0.2 to 1 μm).
m), there is no problem in terms of wiring resistance even if the Mo wiring is cut to the same extent as the Cr film.

After the above processing, the wafer is again transported to the focused ion beam processing apparatus as needed, and the unnecessary path of the Al wiring in the semiconductor device is cut.

With the above-described procedure, the repair of the wiring in the semiconductor device is completed. Here, Mo (Co) ₆ has been described as a CVD material gas, but the present invention is not limited to this. W
Metal carbonyls such as (Co) ₆ , Ni (Co) ₄ , Fe (Co) ₅ , M
oCl ₅ , MoF ₆ , WF ₆ and other metal halides, Al (CH ₃ ) ₃ , Cd (C ₂ H
₅ ) Alkyl metals such as ₃ can be used.

Here, the wiring forming method of the present invention will be described in detail with reference to FIG. FIG. 8 (a) shows a cross section of a semiconductor device which requires wiring cutting and wiring laying. In the present invention, a wafer on which a large number of semiconductor devices are mounted may be directly targeted for wiring installation, or a chip on which one semiconductor device is mounted may be targeted.

A first-layer Al wiring 72 is formed on a Si substrate 70 with an SiO ₂ film 71 interposed therebetween, and a second-layer Al wiring 74 is formed with an inter-layer insulating film 73 interposed therebetween. Is formed.

Usually, contaminants 76 such as water and oil are formed on the passivation film 75.
Are formed, and when a CVD wiring is formed thereon, problems such as poor adhesion and peeling occur. Then, it is removed by sputter etching using Ar plasma and is cleaned as shown in FIG. 8 (b). Thereafter, it is desirably conveyed to the focused ion beam processing section without being exposed to the atmosphere, and as shown in FIG. 8 (c), the connection of the wirings 74 and 72 is performed by a large current and thick focused ion beam processing capable of high-speed processing. Wirings 7 that need to be connected by forming windows 78, 78 'in the passivation film 75 to necessary parts and, if necessary, in the interlayer insulating film 73
Exposing a part of 2,74.

Next, as shown in FIG. 8 (d), when the ion beam is converted into a small current / narrow beam, the area smaller than the exposed portions of the wirings 72 and 74 is processed, and the processing is performed using the thick beam. The sputtered and re-adhered film is removed from the passivation film 75 or the interlayer insulating film 73 as the inner wall of the window.

Meanwhile, as shown in FIG. 8 (e), a film 79 having good adhesion to the passivation film 75, having conductivity, and having a high laser beam absorptivity without being exposed to the air (specifically, as shown in FIG. Chromium film) 200 ~ 600Å by means such as sputter deposition
Is formed with a thickness of During this time, of course, the exposed wiring 7
2,74 surfaces are not exposed to the atmosphere. Mo (Co)
_The windows 78 and 78 'are irradiated with Ar laser light in a _6- gas atmosphere, and the windows are filled with Mo80 and 80'. At this time, first, a laser beam is irradiated for a short time at a high output (however, in a range where no damage is caused to the wiring), and the Mo film having good adhesion is formed on the windows 78 and 78 '.
Formed inside, then irradiate with low power and window with Mo 78,7
8 'completely embedded inside.

Thereafter, a laser beam is scanned between the window 78 and the window 78 'which need to be connected, so that the Mo wiring 81 as shown in FIG. 8 (g).
To form

After forming the Mo wiring 81 in this way, if necessary, condensed Ar in a vacuum or in an atmosphere of an inert gas such as N ₂ gas or Ar or Ne or a reducing gas such as H ₂
The wafer is moved while irradiating the laser, and an Ar laser is irradiated on the Mo wiring 81 to improve the film quality. By irradiating all the Mo wirings 81, the installation is completed.

Here, an Ar laser is used as a laser light source, but any laser light source having a wavelength that can be absorbed by a buffer film (Cr film) and converted into heat can be used. However, continuous oscillation is more desirable. For example, krypton (Kr) laser, YA
A G laser (including high-frequency oscillation) and a CO ₂ laser if the dimensions of the processed portion allow.

The Cr film 79 has a transmittance of about 14% with respect to the Ar laser beam when the thickness is 300 mm and about 2% when the thickness is 600 mm, and the transmittance does not change extremely with other laser light sources. Thermal effects due to laser irradiation on the base can be prevented. Further, since the Cr film 79 absorbs the laser beam and generates heat, where a decomposition reaction occurs and a Mo film is deposited, the influence of the lower layer such as the passivation film thickness and the presence or absence of the Al wiring is small.
Changes in film thickness and wiring width are small. Furthermore, the Cr film itself
The Mo wiring 81 can be formed with a lower laser output than the Al wiring and with a lower laser output than when the Cr film 79 is not provided, and can be formed at a higher speed with the same output.

Thereafter, as shown in FIG. 8 (h), the exposed Cr film 79 is removed by sputter etching.

Finally, as shown in FIG. 8 (i), the wiring is conveyed to the focused ion beam processing section (it may be exposed to the atmosphere), and the wiring requiring cutting 82 is cut by the focused ion beam processing. Through the above series of steps, it is possible to form a low-resistance metal wiring with low adhesion and good adhesion with the Al wiring in the semiconductor at a high speed.

Although many processes are required in the above embodiment, transport between the processes must be performed without exposing to the atmosphere in order to obtain a low resistance connection. Considering FIG. 8 as an example, (b)
Transport between sputter etch and (c), (d) focused ion beam processing is in vacuum (or dry inert gas atmosphere)
Although it is desirable, it may be in the atmosphere for a short time. A high vacuum is required between (d) focused ion beam processing and (e) sputter deposition. A high vacuum is required between (e) sputter deposition and (f), (g) laser CVD and laser annealing. (G) Between laser annealing and (h) sputter etching and (h) between sputter etching and (i) focused ion beam processing may be in air.

As described above, the transfer in a high vacuum can be performed by connecting the chamber for performing each process to the gate valve. FIG. 9 shows an example of the device configuration.

The load lock chamber 101 is connected to the sputtering chamber 165 by a gate valve 102, and the pipe 10 is connected by a vacuum pump 104.
5. The exhaust can be exhausted through the valve 106. The load lock chamber 101 has a sample stage 10 on which a wafer 107 is placed.
8 and an upper electrode 109 are provided, and further connected to an Ar gas cylinder 112 via a flow control valve 110 and a pipe 111.

The sputtering chamber 165 is connected to the ion beam processing chamber 167 by a gate valve 166, and the laser CVD chamber 1 is connected to the gate valve 168.
The vacuum pump 170 is evacuated via a pipe 171 and a valve 172. In the sputtering chamber 165, a sample table 17 for mounting the wafer 107 'is provided.
3 and the above-mentioned electrode 174 having a sputtering target are provided, and further connected to an Ar gas cylinder 177 via a flow rate adjusting valve 175 and a pipe 176. The Ar gas cylinder 177 may be shared with the Ar gas cylinder 112.

A wafer 107 ″ is placed in the ion beam processing chamber 167, and X
A stage 180 movable in −YZ−θ is mounted, and an ion beam can be irradiated to an arbitrary position by the ion beam optical system 120. In addition, the vacuum pump 181 can exhaust the gas through the valve 182 and the pipe 183.

The laser CVD chamber 169 holds a wafer 107 ″ and is XYZ
A stage 184 movable at −θ is installed, and is connected to a CVD source gas cylinder 187 via a valve 185 for flow rate adjustment and a pipe 186. Then, the valve 18 is operated by the vacuum pump 188.
9. The exhaust can be exhausted through the pipe 190. Further, a laser transmission window 122 is provided in the laser CVD chamber 169, and A
The configuration is such that Ar ion laser light 124 oscillated from the r ion laser oscillator 123 can be condensed by the objective lens 126 via the laser optical system 125 and irradiated onto the wafer 107. After the semiconductor device requiring repair by the above-described device is placed in the load lock chamber 101 in the state of a wafer or a chip, the entire process can be performed without exposure to the air at all, and low-resistance connection and low-resistance wiring can be performed. Can be formed at high speed.

Alternatively, each chamber shown in FIG. 9 is installed independently,
To achieve the same effect by transporting the wafer (or chip) via a carrier capable of maintaining a high vacuum (eg, a vessel equipped with a vacuum pump) or via a vessel filled with dry inert gas Can be.

Next, another embodiment will be described below. FIG. 10 shows a configuration of a processing apparatus suitable for forming a connection hole in a wiring forming method according to another embodiment of the present invention. This is obtained by adding a nozzle 201 for supplying a gas for accelerating the etching to the vicinity of the ion beam 1 irradiation part of the focused ion beam processing apparatus shown in FIG. From this nozzle 201, a fluorine-based gas, for example, a gas selected from CF ₄ , CHF ₃ , F ₂ , SiF ₆ and XeF ₂ is supplied. When the ion beam 1 is irradiated in this state, the processing speed of SiO ₂ can be accelerated 10 times or more as compared with the case where no gas is supplied. That is, high-precision connection hole processing can be performed at high speed, but as shown in FIG.
Al wiring exposed at the bottom of the connection hole 203 formed in the SiO ₂ film 202
The surface of 204 is covered with an Al fluoride (AlF ₃ ) film 205. This fluoride film is an insulator, and a low connection resistance cannot be obtained even if a metal is buried by laser CVD in the next process as it is.

Therefore, when the connection hole 203 is formed and the surface of the Al wiring 204 (actually, the fluoride film 205) is exposed, the irradiation of the ion beam 1 and the supply of the fluorine-based gas from the nozzle 201 are stopped. Thereafter, the inside of the chamber is sufficiently evacuated to a high vacuum (10
^(-6 Torr or more), a region narrower than the bottom of the connection hole 203 is scanned while irradiating the ion beam 1 again while the gas supply is stopped, and the fluorine is supplied as shown in FIG. 11 (b). The oxide film 205 is removed and exposed on the surface of the Al wiring 204. The amount of processing at this time depends on the thickness of the Al wiring 204, but is usually 0.5 to
If it is 2 μm, processing of 0.1 to 0.2 μm is acceptable.

After the formation of the connection holes in the portions requiring connection is completed, as described in the previous embodiment, that is, as shown in FIG. 8, a Cr film is formed on the surface of the semiconductor device, and in a CVD gas atmosphere, Embedding by laser irradiation (at this time, irradiation is performed in two stages of high output and low output), wiring formation by scanning with laser irradiation, in vacuum after exhausting CVD gas (or in inert gas or After laser annealing in a reducing gas atmosphere) and removal of the unnecessary Cr film, the wafer is transported again to the focused ion beam processing apparatus, where the unnecessary wiring is cut. The cutting process at this time may be a mere focused ion beam process, or the process shown in FIG. 10 may be performed with an ion beam while supplying a gas for accelerating the etching. In the latter, first, a fluorine-based gas for processing and removing the passivation film and, if necessary, the interlayer insulating film, that is, a gas selected from F ₂ , CF ₄ , SiF ₆ , XeF ₂ , CHF ₃ or the like is supplied to supply high speed When the Al wiring is exposed and the Al wiring is exposed, a chlorine-based gas, that is, a gas selected from Cl ₂ , CCl ₄ , SiCl _4, etc. will be supplied to remove Al at high speed and complete the wiring cutting. I do. After these steps are completed, it may be necessary to perform a treatment such as heating in a vacuum so that fluorine-based and chlorine-based gases do not remain on the surface of the semiconductor device, but this will not be described further here.

〔The invention's effect〕

As described above, according to the present invention, when forming a connection hole, high-speed processing was performed with a large current and a thick beam, and the small current and a narrow beam re-adhered to the surface of the Al wiring when the connection hole was formed. Since the SiO ₂ film is removed, a low-resistance connection can be obtained.

In addition, since a Cr film is formed on the exposed Al wiring surface when embedding metal in the connection hole by laser CVD, the reflectance of laser light is reduced, and low power laser can be embedded, and at the beginning high power can be embedded. By irradiating for a short time and then irradiating until the low power is completely buried, a good buried shape and low connection resistance can be obtained.

According to another method of the present invention, a focused ion beam is irradiated while supplying an etching gas to form a connection hole at high speed and remove a reaction product film formed on an exposed surface of the Al wiring, , A low resistance connection can be obtained.

[Brief description of the drawings]

FIG. 1 is a structural view of a focused ion beam processing apparatus suitable for carrying out the present invention, FIGS. 2 to 5 are explanatory views for forming connection holes of the present invention, and FIG. 6 is a drawing for carrying out the present invention. FIG. 7 is an explanatory view of a method of filling a connection hole of the present invention, FIG. 8 is a view for explaining all steps of a wiring forming method of the present invention, and FIG. 9 is a view of the present invention. FIG. 10 is a configuration diagram of a wiring forming apparatus suitable for implementation, FIG. 10 is a configuration diagram of a focused ion beam assisted etching apparatus suitable for performing a method according to another embodiment of the present invention, and FIG. It is explanatory drawing of connection hole formation by another Example. 1 ...... focused ion beam, the aperture 10 ...... movable, 37 ...... SiO ₂
Particles, 42 laser light, 61, 79 Cr film (buffer film), 63,
72, 74: Al wiring, 201: Gas nozzle, 205: Fluoride film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Uemura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Research Laboratory (72) Inventor Akira Shimase 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd. Production Technology Laboratory (72) Inventor Takahiko Takahashi 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Emiko Okamoto 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Device Development Center (72) Inventor Satoshi Haraichi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Manufacturing Research Laboratory, Hitachi, Ltd. (72) Inventor Fumika Ito 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Inside the Manufacturing Technology Laboratory (56) References JP-A-62-291048 (JP, A) JP-A-64-71149 (JP, A) JP-A-1-140742 (JP, A)

Claims (4)

(57) [Claims] A semiconductor device having a surface covered with an insulating film; a desired region of the insulating film is irradiated with a focused ion beam to remove a desired portion of the insulating film; Exposing the wiring film, irradiating a focused ion beam to a region inside the boundary between the exposed wiring film and the insulating film, and removing and processing the inner region on the surface of the exposed wiring film; A buffer film is formed on the surface of the semiconductor device including the wiring film in which the inner region is processed, and a new wiring film electrically connected to the wiring film whose surface is processed by laser CVD is formed on the buffer film. Forming a new wiring film, and irradiating the new wiring film with a laser to anneal the new wiring film. 2. The method according to claim 1, wherein the processing of the surface of the inner region of the exposed wiring film is performed by reducing the diameter of the focused ion beam as compared with the processing of removing a desired portion of the insulating film. 2. The method according to claim 1, wherein the connection wiring is formed on a semiconductor device. 3. A process of removing a desired portion of the insulating film and processing a surface of the inner region of the exposed wiring film by scanning while irradiating the focused ion beam. 3. The method according to claim 1, wherein the connection wiring is formed on a semiconductor device. 4. The method according to claim 1, wherein the irradiation of the focused ion beam to a desired area of the insulating film is performed in an atmosphere of an etching gas. .