JPH01217946A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the short-circuit between the lower layer wiring and the upper layer wiring, and form a simple connection wiring, by boring a hole in an insulating film on the upper part of a wiring region to be connected, by a converged ion beam, projecting laser light or ion beam in metal compound gas, and forming the wiring by using metal deposited in the hole. CONSTITUTION:Connection holes 7a, 7b are formed by irradiating a prescribed part of an insulating film 6 surface, with converged ion beam 10 of high working accuracy. The surfaces of a first layer wirings 3a, 3b are partially exposed by selectively eliminating an insulating film 9. From a reaction gas cylinder 43 composed of organic metal compound, reaction gas is introduced into a vacuum vessel 29, and inactive gas is introduced from a gas cylinder 46. In this state, a wiring part to be modified is selectively irradiated with laser light 29 to decompose the reaction gas, and metal is selectively deposited at the part irradiated with the laser light. Thereby a connection wiring 8 to connect the first layer wirings 3a, 3b is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device having a multilayer wiring structure and a method for manufacturing the same. It is something.

[Conventional technology]

In recent years, LSI (Large 5cale Int.
After the completion of the egrated curve, Ueno-
Or, rather than cutting and connecting part of the internal wiring in the chip while it is in the chip state, techniques for repairing defective parts, changing logic, etc. are becoming more and more important.

For this purpose, the applicant proposed an LSI wiring connection method by combining ion beam technology and laser CVD technology in Japanese Patent Application No. 70979/1983. According to this method, for example, the L
After the SI is completed, the first layer wiring will be connected for the purpose of correcting defective areas or changing logic. In this case, the wiring on the top layer is usually laid out widely for supplying power supply current, so a connection hole is provided that penetrates the wiring on the top layer and reaches the wiring on the lower layer, and a connection wiring is provided through this connection hole. There is a need. For this purpose, first, a focused ion beam (Focu
[sed Ion Beam (hereinafter sometimes abbreviated as FIB)] Processes the top layer insulation film, the second layer wiring, and the interlayer insulation film between the second layer wiring and the first layer wiring by irradiation. A connection hole is formed, and a part of the surface of the first layer wiring is exposed to the connection hole. Next, for example, after forming an insulating film such as a silicon dioxide film over the entire surface, this insulating film is patterned using photolithography and etching techniques, leaving the insulating film only in the vicinity of the connection hole. Next, the insulating film at the bottom of the connection hole is selectively etched away to partially expose the surface of the first layer wiring in the connection hole again.

Next, metal is selectively deposited by laser CVD to form a connection wiring that connects the first layer wiring through the connection hole. In this case, this connection wiring is
Since the insulating film formed in the connection hole insulates the wiring from the second layer, a gap between the first and second layer wirings is prevented.

On the other hand, as ICs have become more highly integrated and miniaturized in recent years, it has become necessary to cut and connect parts of the internal wiring of LSI chips during the development process to depack and repair defective areas, resulting in design and process errors. It is becoming increasingly important to discover defects, perform failure analysis, and restore process conditions to improve product yield. Conventionally, examples have been reported in which IC wiring is cut using a laser or an ion beam for this purpose.

That is, the first prior art is Techno, Digest Opcleo 81, 1981, page 160 (Tech,
Digest of CLEO' 81 1981,
p160) l'-Laser Stripe Cutting System for Eye Sea Debacking"La5er Str
ipeCutting System for ICd
ebugging", and there have been reports of examples in which wires are cut with a laser and defective locations are depacked.

Furthermore, as a second prior art, Japanese Patent Application No. 58-42126
There is a publication titled K, which uses ion from a liquid metal ion source in order to deal with fine wiring.

A technique has been proposed in which an on-beam is focused on a spot of 0.5 μm or less to cut the wiring or make a hole, and the ion beam is deposited into the hole to connect the upper and lower wiring.

Furthermore, as a third prior art, Extended Abstract of 17th Conference on Solid State Devices and Materials 1985, p.
th Conf, on 5olid 5tate D
evicesand Material 1985.
p193) Direct Writing of Highly Conductive Molybdenum Lines by Laser Induced Chemical Babies
rect Writing of Highly Con
ductive Mo Lines by Laser
Induced CVD) J is available.

[Problem to be solved by the invention]

However, the technique proposed in Japanese Patent Application No. 61-70979 requires photolithography and etching steps in order to form the insulating film only in the vicinity of the connection hole, and the There was a problem in that the process for preventing short circuits between the eye wires was complicated.

Furthermore, in the first prior art described above, only a means for cutting the wires is shown, and no means for connecting the wires is shown. In addition, when using the laser processing method, (1) the processing process is thermal, and there is heat conduction to the surroundings, and processes such as evaporation and ejection, so 0.5
It is extremely difficult to perform fine processing of micrometers or less. (2) Laser light is difficult to be absorbed by insulating films such as 5int, Si, N, etc. Therefore, it is absorbed by the lower layer A, T, polysilicon, etc., and when it evaporates and ejects, it damages the upper insulating film. Process the insulation film by blowing it away explosively. Therefore, if the insulating film is thicker than 2 μm, processing is difficult. In addition, damage to the periphery (surroundings, upper and lower layers) is large and causes defects. From these results, it is difficult to process multilayer wiring and fine, highly integrated wiring.

Furthermore, the second prior art discloses (3) cutting and drilling using a focused ion beam, and (4) means for connecting upper and lower wiring using a focused ion beam. Processing using a focused ion beam can process 0.5 μm or less, and any material can be easily processed sequentially from the top layer by sputtering, so it covers the problems with the first conventional technology. . However, regarding the means for connecting wires in (4) above, only the procedure for connecting upper and lower wires is shown, and there is no mention of the means for connecting one wire to another. It has not been done.

In the third prior art, molybdenum carbonyl Mo
In a gas of an organic compound of metal such as (CO)a,
An ultraviolet laser is irradiated onto a silicon Si substrate coated with SiOz, and photo-thermal
) or photochemical
A method of directly drawing and forming metal wiring by decomposing Mo(Co)a and depositing a metal such as molybdenum Mo on a substrate using a laser-induced CVD process has been proposed.

However, in this case, Mo wiring is simply formed on the insulating film, and in an actual IC, the wiring under the protective film or interlayer insulation film will be short-circuited with the wiring above. There is no indication as to how to connect without any connection.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device in which connection wiring can be formed without causing short-circuits between lower layer wiring and upper layer wiring in the multilayer wiring structure of the semiconductor integrated circuit device. .

Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can easily form connection wiring between lower layer wiring and upper layer wiring in a multilayer wiring structure.

Another object of the present invention is to enable fine holes to be formed in an insulating film such as a protective film or an interlayer insulating film in an IC, and to connect the wiring underneath the hole to other parts, thereby depacking and repairing the IC. , I made it possible to perform failure analysis, etc.
An object of the present invention is to provide a method for connecting wiring of C and its IC.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and relates to a semiconductor integrated circuit device and a method for manufacturing the same. C
Wiring is formed using the metal deposited in the holes using the VD method. Furthermore, in this case, when electrical continuity is established between the upper layer wiring and the lower layer wiring of the multilayer wiring using the connecting wiring, measures are taken to electrically insulate and separate the middle layer wiring through which the connecting wiring passes. ing.

[Effect]

Since metal wiring is formed in selective areas by drilling with a focused ion beam and photo-excited CVD, it not only allows for microfabrication, but also enables electrical connections between the internal wiring after the LSI is completed, making it possible to depack the LSI, Be able to make corrections, analyze defects, etc.

[Example 1] Hereinafter, an example of the present invention will be specifically described using the drawings.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 shows an LS with a two-layer wiring structure according to an embodiment of the present invention.
FIG. 2 is an enlarged sectional view taken along the line XX in FIG. 1; FIG.

As shown in FIGS. 1 and 2, the LSI according to this embodiment
For example, a semiconductor substrate (wafer) 1, such as a silicon substrate, on which a semiconductor integrated circuit is formed, on which a plurality of semiconductor elements such as transistors (not shown) are formed, is coated with a semiconductor substrate (wafer) 1, such as SIO, a film, etc. An interlayer insulating film 2 is formed, and on this interlayer insulating film 2, first 1a wirings (lower layer wirings) 3a and 3b, such as aluminum At films, are provided. For example, on these wirings 3a and 3b,
A glabellar insulating film 4 such as an Oz film is provided, and a second layer arrangement (upper layer wiring) 5a, 5b such as an aluminum At film is provided on this interlayer insulating film 4. The wirings 5a and 5b constitute, for example, a power supply wiring for supplying power current, and are widely laid out on the surface of the interlayer insulating film 4. An insulating film 6 (not shown in FIG. 1) is further provided on this wiring M 5 a +5b. Connection holes 7a and 7b are provided through these insulating films 6, wirings 5a and 5b, and interlayer insulating film 4, and these connection holes 7
a.

A connection wire 8 is provided to connect the lower layer wires 3a and 3b through 7b. For example, defects discovered after the LSI is completed are repaired (or logic is changed, etc.) using the connection wiring 8. Note that the connection hole 7
a and 7b may be vertical connection holes or tapered connection holes. The connection wiring 8 is formed by, for example, laser CVD.
Tungsten W and molybdenum Mo selectively formed by.

It is made of metal film such as cadmium Cd, aluminum A2, etc.

Second layer wiring 5a, 5 exposed to the connection holes 7a, 7b
An insulating film 9 made of, for example, alumina (AltOs) is provided on the surface of b, which is formed by converting this surface into an insulator, thereby establishing a connection between the connection wiring a8 and the second layer wirings 5a and 5b. Prevented. Therefore, the connection wiring 8 can be formed without electrical continuity between the first layer wirings 3a, 3b and the second layer wirings 5a, 5b, that is, without causing a short circuit. The thickness of the insulating film 9 is selected so as to obtain the necessary dielectric breakdown strength depending on the potential difference between the first layer wirings 3a, 3b and the second layer wirings 5a, 5b. To give a numerical example, for example, when this insulating film 9 is made of alumina (withstand voltage is about 500 V/μm) and the potential difference is 5 V, for example, 1000
Thicknesses can range from ~5000A.

Next, a method for manufacturing an LSI according to this embodiment configured as described above will be explained.

As shown in FIG. 3, first, a silicon wafer 1 as a starting material is subjected to impurity diffusion, thermal oxidation of the silicon wafer, thin film formation using the CVD method, and various pattern formation using photolithography technology. After forming the integrated circuit, interlayer insulating film 2, first layer wiring 3
a, 3b, interlayer insulating film 4, second layer wiring 5 a * 5
b and an insulating film 6 are formed to complete the LSI. After this, we will consider the case where a defective part of the wiring is discovered and repaired.

For this reason, for example, using an ion beam processing apparatus as shown in FIG. 6 proposed in the above-mentioned Japanese Patent Application No. 61-70979, a predetermined portion of the surface of the insulating film 60 is irradiated with a focused ion beam 10 with high processing accuracy. Possibly connecting hole 7a
, 7b (Fig. 3). The details of this ion beam processing method will be explained below. In FIG. 6, first, the cover 12 of the preliminary evacuation chamber 110 constituting the sample exchange chamber is opened, and the above-mentioned semiconductor wafer 1 is placed on the stage 14 on the stage 13. Next, close the lid 12 and close the valve 1.
5 is opened and the preliminary evacuation chamber 11 is evacuated by the vacuum pump 16. Thereafter, the gate valve 17 is opened, and the
The stage 14 is transferred onto the Y stage 19. Note that the reference numeral 2o is a valve, which is normally in an open state. next,
After closing the gate valve 17, the inside of the vacuum container 8 is sufficiently evacuated. Next, a high-intensity ion source 22, such as a liquid metal ion source such as gallium (Ga), is installed in an ion beam column 21 installed at the top of the vacuum vessel 18, and a The ion beam 10 extracted by the extraction electrode 23 is passed through an electrostatic lens 24.
Focusing and deflecting through blanking electrode 25, deflector electrode 26, etc.1. The semiconductor wafer 1 is irradiated. next,
The secondary electrons generated from the irradiation of the ion beam 10 are detected by the secondary electron detector DK t7, and the scanned ion beam image by this secondary electron signal is observed by the monitor 28 of the deflection electrode power source 27. Move the stage 19 to detect the location on the semiconductor wafer 1 where the connection holes 7a, 7b should be formed.Thereafter, as shown in FIG. The connection holes 7a and 7b are formed by irradiating the ion beam 10 only on the desired locations.Then, the semiconductor wafer 1 is taken out of the -H ion beam processing apparatus.

Next, the semiconductor wafer 1 is transferred to, for example, an anodizing apparatus (not shown), and the connection holes 7 formed as described above are
a, 7b Kjl The surfaces of the second layer wirings 5a, 5b are anodized to form alumina (for example) as shown in FIG.
The connection holes 7a, 7 are connected to the insulating film 9, such as a
Formed in a self-aligned manner with respect to b. When using aluminum (Al) as the wiring material, anodizing is performed as follows:
Platinum (Pt) may be used as the cathode, and 5% phosphoric acid, phosphoric acid, chromic acid, sulfuric acid, or the like may be used as the electrolyte. Note that during this anodic oxidation, the connection holes 7a, 7
In b, an insulating film 9 is also formed on the surfaces of the first layer wirings 3a and 3b. Since the surfaces of the second layer wirings 5a, 5b exposed through the connection holes 70, 7bK are insulated, the first layer wirings 3a, 3b and the second layer wirings 5a+
5b can be prevented by a simple process without requiring a complicated process such as photolithography. Note that as a method for forming the alumina film, in addition to the anodic oxidation described in 1., a method such as 0. plasma oxidation may also be used. Regarding plasma oxidation technology, see, for example, "Vacuum", Vol. 27, 1.
No. 2, p. 901, 1984. Also,
Materials other than aluminum as wiring materials, such as tungsten W.

When using a high-melting point metal such as molybdenum Mo, oxides of these metals can be formed by performing low-temperature heat treatment while irradiating with ozone, and thereby the insulating film 9 can be formed.

Note that when forming the connection holes 7a, 7b, the surfaces of the first layer wirings 3a, 3b are irradiated with an ion beam, and as a result, for example, aluminum is deposited on the inner peripheral surfaces of the connection holes 7a, 7b at one point in FIG. As shown by the dashed line.

At the stage when the contact holes 7a, 7b are formed, the first layer wirings 3a, 3b and the second layer wirings 5a, 5b are attached.
Although there may be a short circuit between the connecting holes 7a. 7
This problem can be solved by completely converting the aluminum adhering to the inner circumferential surface of b into alumina by, for example, the above-mentioned anodic oxidation.

Next, the insulating film 9 formed on the surfaces of the first layer wirings 3a and 3b in the connection holes 7a and 7b during the above-described anodic oxidation is selectively removed by, for example, laser beam irradiation.
As shown in FIG. 5, these first layer wirings 3a, 3b
partially expose the surface of

Next, the semiconductor wafer 1 is placed again on the stage 14 on the XY stage 13 in FIG. 6, and the stage 14 is transferred onto the XY stage 30 in the vacuum chamber 29 of the laser CVD apparatus. Next, the semiconductor wafer 1 is moved by the XY stage 30 to the irradiation position of lasers yt and 32 emitted by a laser oscillator 31, such as an argon laser, and alignment of the wiring correction portion is performed. Next, the laser beam 32 is reflected by a dichroic mirror 34 via a shutter 33, further condensed by an objective lens 35, and irradiated through a window 36 provided in the vacuum container 29 onto the wiring repair area. At this time, the alignment of the wiring correction points is
Irradiation optical system 37. Half mirror 38, laser light cut filter 39. prism 40. Via the eyepiece 41 etc. (
- This allows you to make corrections while observing the parts to be corrected. Next, the valve 42 is opened, and the cells connected to the vacuum container 29, for example, Mo(CO)e, W(Co)a, are
A reaction gas is introduced into the vacuum container 29 from a cylinder 43 containing a reaction gas consisting of an organometallic compound such as, and at the same time, the pulp 44 is opened and an inert gas is introduced from a cylinder 45 containing an inert gas. Introduce.

In this state, the laser beam 29 is selectively irradiated to nine wiring correction locations to decompose the reactive gas and selectively deposit metal on the irradiated portions of the laser beam 32. As a result, as shown in FIGS. 1 and 2, the connection hole 7
A connection wiring 8 is formed to connect the first layer wirings 3a and 3b through the wirings 3a and 7b. In this case, a metal film having a thickness of, for example, about 0.5 to 1.0 μm can be deposited by scanning the laser beam 32 once.

Although the present invention has been specifically described above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof.

For example, in the above-described embodiment, a case was explained in which defective parts were repaired while the semiconductor wafer 1 was in the state.
After dividing the semiconductor wafer into individual semiconductor chips,
Of course, it is also possible to repair defective parts in the semiconductor chip state. Furthermore, in the above embodiments, the case where the wiring is modified or the logic is changed after the completion of the LSI is explained, but it is also possible to form the wiring to realize the desired logic in a master slice or gate array, for example. The present invention can be applied. Furthermore, the present invention can be applied, for example, to the case where interconnections in the same layer or different layers are formed during the manufacturing process of an LSI having multilayer interconnections.

Furthermore, the present invention can be applied to, for example, a printed circuit board with a multilayer structure.

Note that, as shown in FIGS. 7 and 8, for example, the connection hole 7
The connection between the connecting wire 8 and the upper layer wires 5a, 5b can also be achieved by selectively removing the upper layer wires 5a, 5b around the upper layer wires 5a, 5b together with the insulating film 6 thereon by, for example, ion beam irradiation to form the groove 46. Since contact can be prevented, short circuits between these wirings 3a, 3b and wirings 5a, 5b can be prevented.

[Embodiment 2] FIG. 9 is a plan view showing an LSI with a two-layer wiring structure according to another embodiment of the present invention, and FIG.
FIG. 2 is an enlarged cross-sectional view taken along xm.

As shown in FIGS. 9 and 10, K, LS according to this embodiment
In I, a semiconductor substrate (wafer) 1 on which a semiconductor integrated circuit is formed, such as a silicon substrate on which semiconductor elements such as a plurality of transistors (not shown) are formed.
An interlayer insulating film 2 made of, for example, SiOtM is formed thereon, and first layer wiring (lower layer wiring) 3a, 3b made of, for example, an aluminum (AL) film is provided on this glabellar insulating film 2. On these wirings 3a and 3b, for example, Si
n.

An interlayer insulating film 4 like a film is provided, and this interlayer insulating film 4
Second layer interconnects (upper layer interconnects) 5a and 5b made of, for example, an aluminum (Al) film are provided thereon. The wirings 5a and 5b constitute, for example, a power supply wiring for supplying power supply current, and are widely laid out on the surface of the interlayer insulating film 40. An insulating film 6 (ninth
(not shown in the figure) is provided. Connection holes 7a and 7b are provided through the insulating film 6, the arrangements 5a and 5b, and the interlayer insulating film 4, and these connection holes 7a+7b
tj! I: Connection wiring that connects lower layer wiring 3a and 3b through ? #A8 is provided. And this connection wiring 8
For example, defects found after the LSI is completed are repaired (or logic is changed, etc.). Note that the connection holes 7a and 7b may be vertical connection holes or tapered connection holes.

The connection wiring 8 is composed of eight buffer films such as a chromium (Cr) film and a metal film 8B such as a tungsten (W) film. The metal film 8B is made of, for example, tungsten (W), molybdenum (Mo), or cadmira A (Cd) selectively formed by laser CVD.

It is made of a metal film consisting of a single layer film such as aluminum (Al) or a multilayer film thereof.

On the other hand, the buffer film 8, which is the other component of the connection wiring 8, is
Specifically, chromium (Cr), molybdenum (Mo)
S I T G e *G containing metals such as , tungsten (W), nickel (Ni), or active impurities
Semiconductors such as aAs and polysilicon, and silicide, which is an alloy of metal and silicon. These substances are used in the 5iOt backbasion film that covers the surface of semiconductor devices,
It has excellent adhesion to wiring materials laid by laser CVD.

Therefore, the wiring material does not peel off from the surface of the semiconductor device, and cracks do not occur in the wiring material after installation.

Furthermore, since the buffer film 8A has a high absorption rate for the laser light that causes the CVD phenomenon, the wiring material can be deposited without increasing the laser output, and CVD can be performed with good controllability. In other words, wiring can be laid even if the laser beam is scanned at high speed.

Furthermore, since the presence of the buffer film 8A can alleviate the influence of the material structure of the underlying layer, it becomes easier to keep the width and film thickness of the wires laid constant. Conversely, since the buffer film 8A absorbs most of the energy of the laser beam and reflects a portion of it, the thermal influence on the underlying wiring can be reduced. Experiments have revealed that a chromium (Cr) film is particularly suitable and practical for the buffer film 8A.

A more detailed explanation of the effects, effects, etc. of these eight buffer membranes and their manufacturing method can be found in the patent application filed by the same applicant at the Japan Patent Office, Japanese Patent Application No. 61-245215 (filed in October 1986). 17th) for details.

The second layer wiring 5a with the connection holes 7a and 7b exposed 1-
, 5b is provided with an insulating film 9 made of, for example, alumina (A40S), which is formed by converting this surface into an insulator, thereby connecting the connection wiring 8 and the second layer wiring 5a. Contact with 5b is prevented. Therefore, the connection wiring 8 can be formed without electrical continuity between the first layer wirings 3a, 3b and the second layer wirings 5a, 5b, that is, without shorting. The thickness of this insulating film 9 is
First layer wiring 3a, 3b and second layer wiring 5a, 5b
The material is selected so that the necessary dielectric breakdown strength can be obtained depending on the potential difference between the two. To give a numerical example, for example, this insulating film 9 is made of alumina (withstand voltage is approximately 500 V/μm)
, and when the potential difference is 5V, for example, 10
The thickness can range from 00 to 5oooλ.

The LSI manufacturing method of Example 2 is the same as that of Example 1 described above.
This can be carried out by applying the method for manufacturing a buffer film disclosed in Japanese Patent Application No. 61-245215 to the method for manufacturing SI.

Although the present invention has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

For example, in the above-mentioned embodiment, a case was explained in which defective parts were repaired in the semiconductor wafer state, but after dividing the semiconductor wafer into individual semiconductor chips, Of course, it is also possible to make corrections. Furthermore, in the above embodiment, the LSI
Although the case has been described in which the wiring is modified or the logic is changed after the completion of the process, the present invention can also be applied to the case where, for example, wiring is formed to realize a desired logic in a master slice or a gate array. Moreover, the present invention
For example, it can be applied to the case where interconnections in the same layer or different layers are formed during the manufacturing process of an LSI having multilayer interconnections.

Furthermore, the present invention can be applied to, for example, a printed circuit board with a multilayer wiring structure.

As shown in FIGS. 9 and 1O, the upper layer wirings 5a and 5b around the connection holes 7a and 7b are selectively removed together with the insulating film 6 thereon by, for example, ion beam irradiation to form the grooves 46. By forming this, it is possible to prevent contact between the connection wiring 8 and the upper layer wirings 5a and 5b, thereby preventing short circuits between these wirings 3a and 3b and the wirings 5a and 5b.

[Example 3] FIG. 11 shows L of a two-layer wiring structure according to an example of the present invention.
FIG. 12 is a plan view showing SI, and FIG. 12 is a plan view showing the SI.
It is an enlarged sectional view along the X-ray.

As shown in FIGS. 11 and 12, L according to this embodiment
In SI, multiple transistors etc. (not shown)
A semiconductor substrate (wafer) on which a semiconductor integrated circuit is formed, such as a silicon substrate on which semiconductor elements are formed.
For example, S io on l.

A film-like insulating film 2 between the eyebrows is formed, and this insulating film 2 between the eyebrows
First layer wiring (lower layer wiring) 3a, 3b made of, for example, an aluminum (Al) film is provided thereon. An interlayer insulating film 4 such as a Sin film is provided on the wirings 3a and 3b, and a second layer wiring (upper layer wiring) such as an aluminum (Al) film is formed on this interlayer insulating film 4. ) 5a and 5b are provided. The wirings 5a and 5b constitute, for example, a power supply wiring for supplying power current, and are widely laid out on the surface of the interlayer insulating film 4. An insulating film 6 (not shown in FIG. 11) is further provided on the wirings 5a and 5b. Connection holes 7a,
7b is provided, and a connection wire 8 is provided that connects the lower layer wires 3a, 3b through these connection holes 7a, 7b. By means of this connection wiring 8, for example, an LSI
Repair of defects discovered after completion (or change in logic, etc.)
is being carried out. Note that the connection holes 7a and 7b may be vertical connection holes or tapered connection holes. The connection wiring 8 is made of, for example, tungsten (W), molybdenum (Mo), or molybdenum (Mo) selectively formed by laser CVD.
It consists of a metal film such as cadmium (Cd) or aluminum (A, l, ).

The second layer wiring 5 exposed through the connection holes 7a and 7b
a, 5b are holes 5c having a diameter larger than that of the connecting holes 7a, 7b, as is clear from FIG.
, 5d are provided. These holes 5c and 5dK prevent contact between the connection wiring 8 and the second layer wirings 5a and 5b. Therefore, the first layer arrangement 3a, 3b and the second layer wiring 5a.

The connection wiring 8 can be formed without creating electrical continuity with the wiring 5b, that is, without creating a seam.

A method for forming the holes 5c and 5d will be described later.

Next, a method for manufacturing an LSI according to this embodiment configured as described above will be explained.

As shown in FIG. 13, first, impurity diffusion is performed on a silicon wafer 1 as a starting material, thermal oxidation of the silicon wafer, thin film formation using the CVD method, and various pattern formation using photolithography technology are performed to form a semiconductor. After forming the integrated circuit, form the glabellar insulation film 2, first layer wiring 3a, 3b, interlayer insulation film 4, second layer wiring 5a, 5b, and insulation film 6 to complete the LSI. After this, we will consider the case where a defective part of the wiring is discovered and repaired.

For this reason, for example, using an ion beam processing apparatus as shown in FIG. The connection holes 7a and 7b are formed by irradiating the contact holes 7a and 7b (Fig. 13).

The details of this ion beam processing method are omitted since they were carried out using FIG. 6 when explaining the first embodiment mentioned above.

Next, as shown in FIG. 14, using the insulating film 6 as an etching mask, for example, an aluminum (Al) film, which is the second layer marks lfM5a and 5b whose surfaces are exposed through the connection holes 7a and 7b, is wetted. Etching is performed to form holes 5c and 5d in the second layer wirings 5a and 5b, each having a diameter larger than that of the connection holes 7a and 7b. This hole 5c.

5d, the aperture Aμ of the holes 5c and 5d is
For example, m is 4 μm larger than the diameter B μm of the connection holes 7a and 7b.
By making the connection holes 7a and 7b larger by about m
It is preferable that the ends of the holes 5c and 5d, which are drilled in the second layer wirings 5a and 5b, exist at positions recessed by about 2 μm from the opening ends of the holes. The connection hole 7a has such a shape. By providing a removed portion of the second layer wiring 5a, 5b in the portion 7b, the connection wiring 8 to be described later can be replaced with the second layer wiring 5a.
.

5b, that is, they are not in a short-circuit state.

In short, the hole 5 is the removed portion of the second layer wiring 5a, 5b.
The sizes of c and 5d are such that the connection wiring 8 connected to the first layer wirings 3a and 3b through the connection holes 7a and 7b is connected to the second layer wirings 5a and 5b due to the presence of the holes 5e and 5d.
Any size is sufficient as long as it has a shape that is not electrically connected to.

As mentioned above, the second layer 1J5a and 5b are formed using a material mainly composed of aluminum, such as aluminum or aluminum containing about 0.5% to 1.0% silicon (Si). As I said. Wet etching solutions for these aluminum-based materials include phosphoric acid, glacial acetic acid, nitric acid, and water.
It is preferable to use a mixed solution mixed in a volume ratio of 15:3:5. This etching solution can be used not only for etching aluminum, but also for alumina, which is an oxide of aluminum.
Altos) also has the property of niche-megging. Therefore, even if the wiring film is made of a material whose main component is aluminum, where the surface of the aluminum film is oxidized to form a thin alumina film, only the desired portions can be reliably etched away. It should be noted that there are various wet etching solutions for materials containing aluminum as a main component other than those mentioned above.

Next, as shown in FIG. 15, an ion beam processing device is used to irradiate the area of the glabella insulating film 4 whose surface is exposed through the connection holes 7a and 7b with a focused ion beam with high processing precision. Holes 4a and 4b are formed. In this case, due to the straightness of the focused ion beam, the connection hole 7a,
A hole 4a having approximately the same diameter as the connecting holes 7a and 7b is provided below 7b.

4b will be formed.

Next, as shown in FIGS. 11 and 12, photoexcitation C
Tungsten (5) is produced by scanning a laser beam using laser CVD, which is a VD method.

A metal film such as molybdenum (Mo) is formed in a predetermined pattern.

In addition, in FIG. 12, reference numbers 5e and 5f indicate void areas. This void area 5e.

The connection wiring 8 and the second layer wiring 5a, 5b are electrically insulated and separated by 5f.

In this embodiment, the connection wiring 8 and the second layer wiring 5a.

5b is electrically insulated from the second layer wiring 5a, 5b by wet etching the gap regions 5e, 5f.
This is done by forming a Therefore, since it is wet etching, compared to the method described in Example 1,
It has the advantage of being easy to operate and can be done in a short time. Furthermore, the insulation separation method using the anodic oxidation method described in Example 1 is carried out by immersing the sample in an electric bath containing an electrolytic solution, so the electrolytic solution and various contaminants are crushed on the sample. Even if it is cleaned and removed, a complicated process is required to completely remove it, and in normal cleaning and removal work, electrolytes and various contaminants inevitably remain on the sample, which reduces the reliability of LSI characteristics after mounting. There is a risk of deterioration in performance and electrical characteristics in the future. Furthermore, when converting selective areas of aluminum wiring to alumina by anodizing, undesired areas of the sample are not anodized, which can lead to deterioration of the electrical characteristics of the sample, such as LSIs, and failures. occurrence, and there is a risk that reliability will deteriorate in the future. For example, as a sample, bump electrodes made of various solder materials are used as external terminals. , CCB (Controlled C
For example, in computer LSIs implemented using the o11apse bonding method,
Some wX10L S I chips have hundreds of bump electrodes on a flat surface, but when the aluminum wiring is anodized, the bump electrodes are also anodized, resulting in deterioration of electrical characteristics and defects. There is a risk that accidents may occur.

On the other hand, the insulation separation method using wet etching described in this example has the advantage of being able to completely clean (remove) the etching solution adhering to the sample in a short time with a simple operation, and eliminating various undesirable problems associated with anodizing. There are no problems at all. Therefore, it should be noted that this method is more practical than the anodic oxidation method, and is a good method that will not cause deterioration of the electrical characteristics of the sample or decrease in reliability in the future.

In addition, as the connection wiring 8 in this example, Example 2
A composite film of 8 buffer films and metal 111!8B as described above may be used.

Although the present invention has been specifically described above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof.

For example, in the above-mentioned embodiment, a case was explained in which defective parts were repaired while the semiconductor wafer 1 was in the state.
Of course, it is also possible to divide a semiconductor wafer into individual semiconductor chips and then repair defective parts in the semiconductor chips. Furthermore, in the above embodiment, the LSI
Although the case has been described in which the wiring is modified or the logic is changed after the completion of the process, the present invention can also be applied to the case where, for example, wiring is formed to realize a desired logic in a master slice or a gate array. Moreover, the present invention
For example, the present invention can be applied to the case where interconnections in the same layer or different layers are formed during the manufacturing process of an LSI having multilayer interconnections.

Furthermore, the present invention can be applied to, for example, a printed circuit board with a multilayer wiring structure.

[Example 4] In this Example 4, a hole is made in the insulating film above the wiring location to be connected using a focused ion beam, and then a focused laser beam or ion beam is irradiated in a metal compound gas. , a wiring is formed using the metal deposited in the hole. Further, in this case, the upper part of the hole is processed to be wider so that a particularly large amount of metal is deposited in the hole part, so that the metal is embedded, and the connection with the lower wiring is made sufficiently.

With this configuration, the locations of multiple wirings to be connected are detected using a scanning ion microscope that uses secondary electron signals or secondary ion signals from the sample, and after positioning and determining the irradiation location, the ion A beam is irradiated to remove the insulating film on the wiring in this area. In this case, since a focused ion beam is used instead of a laser, 0.5 μm
It is fully possible to focus and process the following. Also, since there is no selectivity in processing depending on the material, SiO□, Si3N4
Insulating films such as these can also be processed sequentially from the top, and holes can be made in them to expose the wiring underneath.

After that, a metal compound gas is introduced into this vacuum container through a nozzle or piping, and the sample stage is moved relatively so that the area where wiring is to be formed is irradiated with a focused ion beam or focused laser beam. Then, metal wiring is formed by an ion beam induced CVD process or a laser CVD process. As a result, after the IC is completed, the internal wiring can be connected, and the IC can be depacked, modified, and analyzed for failure. Note that depacking an IC here refers to finding and correcting wiring connections inside an IC, and depacking an IC.
This includes diagnosing.

Furthermore, in order to prevent the buried metal for connection with the lower wiring from becoming electrically conductive with the upper layer wiring, there is a method of notching the upper layer wiring that is in contact with the buried metal.

FIGS. 16 and 17 are diagrams showing the formation of wiring connections to an IC according to an embodiment of the present invention.

FIG. 17 is a cross-sectional view of an IC chip, in which an insulating film 101 (Sin.

etc.), and wirings 102a and 102b are placed above it.

102c (Al, etc.) is formed across the insulating film 101, and a protective film (SiOy + Si3N4
etc.) 101 is formed.

Now, if you want to electrically connect the lower layer arrangement 102a and other wiring (not shown), use a focused ion beam to connect the arrangement 102a
A hole 103a is formed in the insulating film 101 on top of the hole 103a.

103b is opened to expose a part of the wiring 102a.

After that, holes 103a are formed by laser-induced CVD or the like.

103b is filled with metal 104, and then metal wiring 104 is formed up to a desired connection point. Prior to the formation of the metal wiring 104, a structure may be provided in which the buffer film described in the second embodiment is provided.

The IC uses multilayer wiring, and the -th layer (bottom layer) 1
When connecting from 02a, upper layer wiring must be avoided. In FIG. 16, holes are drilled at positions avoiding the second layer 02b. However, the third layer (top layer) 102
Since c is a power supply wiring and has a wide width W as shown in FIG. 16, it is difficult to always set the location where the connection is desired to be made at a position away from the third layer. For this reason, in most cases, the hole 103b is drilled through the third layer wiring 102c, and this hole is filled with metal-to-metal ml by laser CVD or the like.
When O4'a' is formed, the -th layer 102a and the third layer 10
2c is shorted. Therefore, a cutout groove 105 (width W) shown in FIG. 16 is formed outside the hole 103b for the third layer wiring 1.
Processing is performed at a depth Z that is slightly deeper than the depth 02C, and the portion that contacts the metal wiring 104 is electrically separated from the other portions of the third layer wiring 102C. Thereafter, metal wiring is created by laser CVD or the like in the direction of the opening of the notch 105.

As shown in FIG. 18, if the third layer wiring 102c is bent, the third layer wiring may be cut out in an oblique straight line. This has the advantage that the ion beam can be scanned simply.

Further, the cutout groove may be formed into a circular arc shape as shown in FIG. 19. In this case, the ion beam can be scanned by superimposing sinusoidal waves in the X and Y directions, so it has the advantage of being simple.

When the second layer arrangement 102b is present below the cutout groove 105 as shown in FIG. 16, the following points must be further noted. In such a case, as the density of ICs is increasing, the second layer wiring exists at a pitch of, for example, 5 to 10 μm, so if the processed holes 103a and 103b are positioned away from the second layer arrangement 102b, It often happens that the notch groove overlaps the second layer wiring. In this case, controlling the notch groove depth is important.

According to experimental results (Figures 20 and 21), when there is a convex step on the workpiece surface, when sputter etching is performed using a focused ion beam, the step shape progresses from concave to convex. shown.

This is because, as is well known, when the angle of incidence of the beam on the surface to be etched is around 40-70°, a sputtering rate of 1.5-2 times can be obtained than when the angle of incidence is 00°. It is a filter (Figure 22). From FIG. 21, in this experiment, the step progresses when θ is about 45°.

If you look at the processing examples in Figures 1 and 2 on the Y-Y cross section, you will see that the 23rd
It becomes a figure. Since the level difference in the third layer wiring 102c causes the level difference 106 in the protective film 101, the notch groove 1
The shape of the step 106 is reflected on the bottom of 05,
A part of the second layer wiring 102b is etched. For this reason, as shown in FIG. 24, which is a cross section taken along the Z-Z line in FIG. 23, the cross-sectional area of the second layer wiring 102b is reduced, and the reliability of the device is impaired. Alternatively, when the second layer wiring 102b is spanter-etched, a problem arises in that wiring material adheres to the side wall of the notch groove, and the deposit 107 of this wiring material causes a short circuit between the second layer and the third layer.

As a countermeasure against this, as shown in FIG. 25, the edge portion 108 of the step 106 is captured as a secondary particle image as shown in FIG.
Start scanning 9.

The machining depth Z (t> shown in FIG. 26) is proportional to the machining time t when the ion current is sufficiently stable (within a normal device, it is within ±5%), so it is determined as a function of the time t.

Further, the slope ψ of the step 106 is constant in the case of the same device due to the film forming process, and can be known in advance. By shifting the scan position of the focused ion beam to the left by Δ(t)=Z(t)/tan tp from Z(t) and ψ, processing can always be performed from the edge portion 108. This function is not limited to the above functions. If the above-mentioned adjustment of the scan start position is continued until the step height reaches 2°-Z(t), the processed bottom surface will be at the same level as the element surface.

Thereafter, by performing normal machining, it is possible to complete the notched groove 105 with a flat bottom surface, as shown in FIG. This K can improve the yield of preventing short circuits caused by notches in the third layer wiring.

As mentioned above, after drilling the connection part and cutting the notch to prevent short circuit, laser or ion beam induced CV
By generating the metal wiring 104 between desired connection points by D, the lower layer wiring 102b and other wiring are connected.

As explained above, according to the present invention, it is possible to arbitrarily connect wires located at different locations in a highly integrated, multilayered IC, and thereby facilitate failure analysis in LSI design, prototyping, and mass production processes. It is easy to perform, and has the effect of shortening the development process, shortening the start-up period for mass production, and improving yield.

〔Effect of the invention〕

The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and relates to a semiconductor integrated circuit device and a method for manufacturing the same. C
Wiring is formed using the metal deposited in the holes using the VD method. In addition, in this case, when attempting to establish electrical continuity between the upper layer wiring and the lower layer wiring of the multilayer wiring using the connecting wiring, measures are taken to electrically insulate and separate the middle layer wiring through which the connecting wiring passes. ing. The present invention configured as described above has the following features:
Metal wiring can be formed in selective areas by drilling with a focused ion beam and photo-excited CVD, etc.
In addition to being able to perform fine processing, it is also possible to electrically connect internal wiring after the LSI is completed, and to perform depacking, modification, failure analysis, etc. of the LSI.

[Brief explanation of the drawing]

FIG. 1 shows an LS with a two-layer wiring structure according to an embodiment of the present invention.
FIG. 2 is an enlarged cross-sectional view taken along line X-X in FIG. A cross-sectional view for explaining the method step by step, FIG. 6 is a diagram showing an ion beam processing device and a laser CVD device, and FIG. FIG. 8 is a plan view showing another example of
FIG. 9 is a plan view showing an LSI according to another embodiment of the present invention; FIG. 10 is an enlarged cross-sectional view taken along line Y-Y in FIG. FIG. 11 is a plan view showing an LSI that is still another embodiment of the present invention; FIG. 12 is an enlarged cross-sectional view taken along X-XIJK in FIG. 11; Figures 13 to 15 show the LS shown in Figures 11 and 12.
16 and 17 are cross-sectional views for explaining the manufacturing method of I in the order of steps. FIGS. The figure is a sectional view taken along the line XX in FIG. 16, FIGS. 18 and 19 are views showing other embodiments of the present invention, respectively, and FIG. 21
The figure is a sectional view taken along the line XX in FIG. 20, FIG. 22 is a graph for explaining the results in FIG. 20, FIG. 23 is a sectional view taken along the Y-X line in FIG. 16, and FIG. 23-2 cross-sectional view and FIGS. 25 to 27 are diagrams showing an example of a processing method for eliminating steps on the workpiece surface, and FIG. It is a YX sectional view of the figure. 1... Semiconductor substrate (wafer), 2... Interlayer insulating film,
3a, 3b... lower layer wiring, 4... interlayer insulating film, 5
a. 5b... Upper layer wiring, 6... Insulating film, 7a, 7b...
・Connection hole, 8... Connection wiring, 9... Insulating film, 10.
...Focused ion beam. Figure 7 Figure 2 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure □ 77. jl Figure 72 Figure 76 Figure 7 Figure 77 2, Figure 78 Figure 20 Figure 27 3 22 Inryu shoulder 28 Figure 102a

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a multilayer wiring in which a first insulating film is interposed between an upper wiring and a lower wiring, and the surface of the upper wiring is protected by a second insulating film. A contact hole is provided in the second insulating film, the upper layer wiring thereunder, and the first insulating film thereunder, and in the contact hole and a selective region of the surface of the second insulating film, A connection wiring is formed that is electrically connected to the lower layer wiring whose surface is exposed through the connection hole, and the connection wiring and the upper layer wiring are electrically insulated and separated. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the connection hole is a small hole formed by focused ion beam processing. 3. In the case where the connection wiring and the upper layer wiring are electrically insulated, the connection wiring and the upper layer wiring are electrically isolated by interposing an insulator formed by oxidizing the upper layer wiring around the connection wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is insulated and isolated. 4. Upper layer wiring is aluminum or 0.5~1.0
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is made of a material whose main component is aluminum, such as aluminum containing silicon (Si). 5. The semiconductor integrated circuit device according to claim 1, wherein the connection wiring is a multilayer film consisting of a buffer film and a metal film. 6. The semiconductor integrated circuit device according to claim 1, wherein the connection wiring is a multilayer film consisting of a chromium film and a metal film formed by a photo-excited CVD method. 7. In a semiconductor integrated circuit having a multilayer wiring in which a first insulating film is interposed between an upper layer wiring and a lower layer wiring, and a surface of the upper layer wiring is protected by a second insulating film, a second insulation film is provided. A contact hole is provided in the film, an upper layer wiring thereunder, and a first insulating film thereunder, and the contact hole and a selective area of the surface of the second insulating film have a surface formed by the contact hole. A connection wiring is formed that is electrically connected to the exposed lower layer wiring, and the connection wiring and the upper layer wiring are electrically insulated and separated by a gap region provided therebetween. A semiconductor integrated circuit device characterized by: 8. A method for manufacturing a semiconductor integrated circuit device having a multilayer wiring in which a first insulating film is interposed between an upper wiring and a lower wiring, and a surface of the upper wiring is protected by a second insulating film, a step of preparing a substrate in which an integrated circuit including a semiconductor element having a junction is formed on a semiconductor substrate, and a multilayer wiring electrically connected to the integrated circuit is formed on the surface of the semiconductor substrate; The second insulating film, the upper layer wiring thereunder, and the first insulating film thereunder are sequentially selectively removed by focused ion beam processing to form a connection hole, and the surface of the lower layer wiring is exposed through the connection hole. a step of chemically converting a region of the upper layer wiring whose surface is exposed by the contact hole into an insulating material; 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a connection wiring electrically connected to a lower layer wiring whose surface is exposed through a connection hole. 9. For the upper layer wiring, use a material whose main component is aluminum, and in order to convert the area whose surface is exposed by the connection hole in the upper layer wiring into an insulator, oxidize the material whose main component is aluminum to form alumina. Claim 8
A method of manufacturing the semiconductor integrated circuit device described above. 10. As a photo-excited CVD method, C
The VD method is used, and the material for the connection wiring is tungsten (
Claim 8: W), molybdenum (Mo), cadmium (Cd), and aluminum (Al).
A method of manufacturing the semiconductor integrated circuit device described above. 11. The connection wiring is provided with a buffer film as a lower layer conductor, and the material of the buffer film is chromium (C).
9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein one of the following materials is used: r), molybdenum (Mo), tungsten (W), and nickel (Ni). 12. The substrate may be a semiconductor wafer in which a plurality of semiconductor integrated circuits are formed vertically and horizontally, or a semiconductor integrated circuit chip in which the semiconductor wafer is divided into individual semiconductor integrated circuit chips (pellets). 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8. 13. A method for manufacturing a semiconductor integrated circuit device having a multilayer wiring in which a first insulating film is interposed between an upper wiring and a lower wiring, and a surface of the upper wiring is protected by a second insulating film, comprising: a step of preparing a substrate in which an integrated circuit including a semiconductor element having a junction is formed on a semiconductor substrate, and a multilayer wiring electrically connected to the integrated circuit is formed on the surface of the semiconductor substrate; selectively removing the second insulating film by focused ion beam processing to form a connection hole that exposes the surface of the upper layer wiring in that region; selectively removing the second insulating film by wet etching using the second insulating film as an etching mask to form an opening region in the upper layer wiring having a diameter larger than the connection hole; and a step of opening the surface by the connection hole. a step of selectively removing the first insulating film that has been removed by focused ion beam processing to form an opening that exposes the surface of the underlying wiring in that region; A semiconductor integrated circuit comprising the step of forming a connection wiring electrically connected to a lower layer wiring whose surface is exposed through the connection hole in a selective region of the surface using a photo-CVD method. A method of manufacturing a circuit device.