JPH11340334A - Semiconductor device and correction method for interconnection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which an interconnection can be corrected surely in a comparatively short time and to provide a correction method for a semiconductor device. SOLUTION: In a correction method for a semiconductor device, a plurality of window parts 4 are formed in an interconnection layer, for a power supply, in the upper layer of the semiconductor device in such a way that they correspond to interconnection parts in an interconnection layer in the upper layer of the interconnection layer for the power supply. In addition, a focused ion beam is applied on the semiconductor device, the interconnection parts in the interconnection layer in the upper layer of the window parts 4 are exposed inside the window parts 4 in the interconnection layer for the power supply. While a source gas is being supplied to parts near the window parts 4, interconnection films which are connected to the interconnection parts exposed when the focused ion beam is applied are formed on an insulating film which covers the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring correction method such as a logic correction of a logic LSI, and more particularly, to a semiconductor device structure capable of improving the yield of wiring correction and shortening the required time, and adopting the structure. The present invention provides a wiring correction method that can be performed.

[0002]

2. Description of the Related Art In recent years, a semiconductor device, that is, an LSI, which is formed of a semiconductor device formed by laminating an insulating layer, wiring, and a through hole provided in the insulating layer by implanting impurities into a substrate, has been developed. With miniaturization and high capacity, the difficulty of development is increasing. However, in order to enter the market at an appropriate time and establish the semiconductor business, it is necessary to resolve various defects generated in the development stage at an early stage. For example, a logic LS built into a large computer
In the case of I, a mistake in logic design or the like may cause a situation in which debugging of the computer assembly is stopped. At this time, it is necessary to promptly supply LSIs with normal logic, but it takes about one month for normal LSI remanufacturing, which delays assembly debugging and extends the development period of the entire device. Therefore, a method has been put into practical use in which wiring is directly reconnected in the state of a stock chip, and a normal chip having a changed logic of the LSI is supplied to the assembling process in a few days. For this purpose, a local processing / film formation technique using a processing / film formation by a focused ion beam and a film formation by a laser beam shown in FIG. 19 is adopted.

The focused ion beam 43 focuses an ion beam extracted from a high-brightness ion source called a liquid metal ion source into a spot of 0.1 μm or less, and irradiates the surface of the LSI. The ions are accelerated to several tens of kV, and the energy causes the constituent materials of the LSI to be sputtered from the surface. By applying this, it is possible to process any part of the wiring in the LSI, and if processing is performed until the wiring is removed, the wiring can be cut.If processing is stopped in the middle of the wiring, the wiring can be processed. You can open the window to At present, when a focused ion beam 43 is irradiated in the presence of a CVD gas 44 such as W (CO) 6, a window is opened using a focused ion beam CVD process in which the CVD gas 44 is decomposed and a metal film is deposited. The filling metal 45 is embedded in the hole.

[0004] The LSI that has been advanced to the above process is replaced by a laser C
It is transported to the VD device to form wiring. Laser for wiring formation
Use a CVD process. This is a method of irradiating a laser beam 46 in the presence of a CVD gas 47 and depositing a metal from a CVD gas 47 such as Mo (CO) 6 by thermal decomposition, similarly to the focused ion beam CVD. As a result, compared with focused ion beam CVD, low-resistance wiring can be formed at high speed, and even large-scale wiring correction in actual logic LSI can be performed with practical performance logical correction .

FIG. 20 shows an example in which wiring correction is actually performed. Although the logic of the logic LSI has been changed, as shown in FIG.
The feature of I, especially in the case of a bipolar logic LSI, is a wide power supply wiring in the uppermost layer. Here, the designation of the wiring layer is referred to as a power supply wiring from the upper layer, which is different from the actual wiring forming step, but the layer below it is referred to as the first layer signal wiring, and the wiring therebelow is referred to as the second layer signal wiring. I will call it. Now, it is assumed that the connection part 23A of the leftmost second-layer signal wiring 8 and the connection part 23B of the right second-layer signal wiring 8 are connected. Connection part 2
In FIG. 3A, as shown in FIG.
The filling metal 45 is deposited by focused ion beam CVD in the hole opened by the window. From here, metal is deposited by laser CVD, and a laser CVD wiring 24 is formed up to the connection portion 23B. Similarly, connection between the connection part 23C and the connection part 23D is also possible. Here, as described in JP-A-3-27550,
By adopting a method in which a part of the power supply wiring is separated and passed through the spare wiring 22 which can be used as wiring, a long laser CVD wiring is not routed, and Crossing is also possible. Here, the connection parts 23B, 23C, and 23D are drawn out from under the wide power supply wiring 1. In this case, there is a problem that the second layer signal wiring 8 and the power supply wiring 1 connected as shown by the connection portion 23C in FIG. 21 are short-circuited by the filling metal 45 formed by focused ion beam CVD. For this reason, the portion around the connecting portion has been short-circuited with the power supply wiring 1 until now, but has been cut off from the power supply wiring 1 around the portion to substantially prevent the short-circuit.

[0006]

The notch 25 as shown in FIG. 20 employs a method of forming a thin groove around the connection portion 23. Since it takes a lot of processing time to remove the entire periphery of the processing portion by the focused ion beam processing, the groove is processed. However, although the processing volume is reduced by forming a groove, the time required for cutting, opening a window, and filling the metal is several minutes, while the time required for this notch is 10 minutes. It is on the order of minutes to tens of minutes, and accounts for a large proportion of the entire time required for wiring correction. The object to be cut is the power supply wiring, and the material is metal. Metals are usually in a polycrystalline state, and in sputtering by a focused ion beam, there is a phenomenon that the processing speed varies depending on the crystal orientation. Therefore, the progress of the processing differs depending on the location in the groove. This causes a metal residue in the groove and reduces the yield of the notch. Furthermore, except for the notch, the shape of the processing and film formation by the focused ion beam is constant depending on the location. However, in the notch, it is necessary to set a different groove length depending on the location. A cumbersome algorithm is required to generate a film formation execution command. In the actual wiring correction, the position of the connection part is selected so as to reduce the number of notch points as much as possible, but for this reason, the processing difficulty of other connection parts increases, In some cases, the content of the correction must be changed. Moreover, it is difficult to completely avoid the notch.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of repairing a semiconductor device capable of reliably performing wiring repair in a relatively short time in view of the above-mentioned disadvantages of the prior art.

[0008]

Means for solving the problems Notches can not be avoided, but as a method of reducing the load of the notch as much as possible, a method of forming a slit in a power supply wiring as disclosed in Japanese Patent Application Laid-Open No. 3-36750 has been proposed. I have.

However, according to the present invention, the time required for wiring correction can be reduced and the yield can be improved by completely eliminating the notch as described above. Normally, a uniform power supply wiring having a wide width is subjected to patterning so that wiring can be easily corrected without a cutout.

That is, according to the present invention, in order to achieve the above object, in a semiconductor device in which an insulating layer and a wiring layer are laminated on a substrate and a power supply wiring layer is formed thereon, A plurality of windows are formed corresponding to the wiring of the wiring layer below the power supply wiring layer.

Then, the plurality of windows are formed at intervals corresponding to the width direction position and the pitch of the wiring in the lower wiring layer.

Further, the width of each of the plurality of windows is formed larger than the dimension in the width direction of the wiring of the lower wiring layer.

According to the present invention, in order to achieve the above object, in a semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate and a power supply wiring layer is formed thereover, The power supply wiring layer is characterized in that a window larger than the width of the wiring of the wiring layer is formed.

A plurality of the windows are formed at intervals corresponding to the position and the pitch in the width direction of the wiring in the lower wiring layer.

According to the present invention, in order to achieve the above object, in a semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate and a power supply wiring layer is formed thereon, A plurality of windows are formed corresponding to the wiring of the lower wiring layer of the power supply wiring layer, and wirings connected to the wiring of the lower wiring layer through the windows are formed.

The wiring connected to the wiring in the wiring layer is
The window is electrically insulated from the power supply wiring layer.

According to the present invention, in order to achieve the above object, in a semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate and a power supply wiring layer is formed thereon, A plurality of windows are formed corresponding to the wiring of the lower wiring layer of the power supply wiring layer, and wirings connecting different wirings of the lower wiring layer are formed through the plurality of windows. . The wiring connecting these different wirings is electrically insulated from the power supply wiring layer at the window.

According to the present invention, in order to achieve the above object, an insulating layer or a wiring layer is laminated on a substrate, and a power supply wiring layer having a window is formed thereon, and the surface is formed of an insulating film. The coated semiconductor device is irradiated with a focused ion beam to expose a wiring portion of a wiring layer below the window portion inside the window portion, and is irradiated with the focused ion beam while supplying a material gas near the window portion. A wiring film connected to the exposed wiring is formed on an insulating film covering the surface.

According to the present invention, in order to achieve the above object, an insulating layer and a wiring layer are laminated on a substrate, and a power supply wiring layer having a plurality of windows is formed on the insulating layer and the wiring layer. A semiconductor device covered with a film is irradiated with a focused ion beam, and a first wiring portion of a wiring layer below a first window portion of the plurality of windows and a second window portion of the plurality of windows. To expose the second wiring portion of the lower wiring layer, and irradiate a focused ion beam while supplying a material gas to form a first lower portion of the lower portion of the first window portion.
And a wiring for electrically connecting the wiring portion of the second portion and the second wiring portion under the second window portion is formed on an insulating film covering the surface.

The first wiring section and the second wiring section are in different wiring layers.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] In this embodiment, notches are avoided by patterning windows on power supply wiring 1 at regular intervals.

If there are windows formed at regular intervals as shown in FIG. 1, it is not possible to see all the wires from the window 4, but a certain number of the first-layer signal wires 7 and the second-layer signal wires 8 is made possible via the window 4. For example, like the connection from the connection part peeping through the gap of the power supply wiring 1 like the connection part 23G, since the connection part 23E is peeping through the window 4, it is processed here and the wiring is drawn out, and another connection is made. In the case of connecting to the portion 23F by the laser CVD wiring 24, if both are opened from the window 4, the notch processing which conventionally required a longer processing length near the center of the power supply wiring 1 is not required. In addition, the processing time can be shortened, and the reduction in the processing yield due to the notch remaining frequently occurring due to the long notch can be avoided.

As for the cutting process, since the power supply wiring 1 can be processed to be larger than the area of the cutting process, a window can be opened, and the cutting process can be performed in the window. It may be about the wiring pitch. However, if cutting through the window 4 is possible as in the cutting section 27 shown in FIG. 1, the processing time can be reduced as compared with processing the power supply wiring 1. If the pitch can be set to twice or more, the wiring correction time can be further reduced. The pitch of the window 4 can be set to be 1.5 times or more the wiring pitch when the size of the window 4 is in accordance with the pitch of the underlying signal wiring. If the window 4 is to be greatly opened, the pitch becomes longer accordingly.

Although the opening position of the window 4 itself does not correspond to the position of the lower signal wiring in FIG. 1, it should be aligned with the center of the signal wiring as far as the lower signal wiring can look. desirable. In particular, as shown in FIG. 1, the first layer signal wiring 7 is relatively likely to be peeped between the power wirings 1 because the power wiring 1 is vertically long, but the second layer signal wiring 8 is Since the wiring direction coincides with the long side direction of 1, the probability of seeing between the power supply wirings 1 is low. Therefore, the center of the window 4 is made to coincide with the center line of the second-layer signal wiring as much as possible under conditions such as not including a region where the through hole between the power supply wiring 1 and the first-layer signal wiring 7 is set as the window 4. The design rule is set as follows. However, the power supply wiring 1 needs to satisfy the current capacity as a required specification for the power supply wiring, and the size and the formation pitch of the window 4 are set within a range satisfying the power supply wiring specification.

[Second Embodiment] In the first embodiment, the windows are arranged at regular intervals. However, since the power supply wiring specifications are finally given priority, the size and pitch of the windows are limited in an LSI that flows a large current. Situation occurs. Therefore, in the present embodiment, a necessary and sufficient window is formed by limiting a place where the window needs to be actually opened.

The signal lines are always connected to each other via through holes. If the through hole is a signal wiring that is not under the power supply wiring, the signal wiring always extends to the gap between the power supply wirings. Therefore, it is set as a design rule for opening a window that a through hole is provided under the power supply wiring, and that either of the signal wirings is stopped in the through hole. However, in this case, the through holes for making the windows correspond to the through holes between the layers to be processed for wiring correction are limited. Under these conditions, the current burden on the power supply wiring can be reduced, and a window necessary and sufficient for wiring correction can be formed. Even under this condition, if the load on the power supply wiring is too great, it is possible to remove selected through-holes at a fixed rate and set the level to satisfy the power supply wiring.

FIG. 2 shows an example of the present embodiment. The layers to be processed here are limited to the first-layer signal wiring 7 and the second-layer signal wiring 8, and at the position of a through hole between the two signal wirings,
In addition, the window 4 is formed only at a position where one of the two signal lines is stopped at that position, that is, only at a T-shaped portion. The size of the window 4 may be about the same as the signal wiring pitch if the cutting is performed through the power supply wiring 1, and may be at least twice the signal wiring pitch if the cutting is also performed through the window. Is required as described in the first embodiment.

The wiring modification shown in FIG. 2 shows an example of connection from the connecting portion 23H to the connecting portion 23I by the laser CVD wiring 24. However, since the through hole 14 can be seen through the window 4,
There is no need to prevent short circuits due to the notches, and the effects of shortening the time and improving the yield described in the first embodiment are the same. In this example, since the size of the window is set to twice the signal wiring pitch, the cutting portion 27 is also opened from the window 4, and cutting is performed through the window 4. In addition, through hole 1
4, the connection target layer becomes thicker than when the signal wiring is opened. In addition, a metal material such as W, which is often used for a through hole, has a high yield of secondary ions generated when a focused ion beam is irradiated. For this reason, the end point of the processing is easily detected. Further, when the processing hole is set deeper, a contact area of the filling metal in the focused ion beam CVD can be increased, and a secondary effect such as a reduction in connection resistance of the wiring can be obtained.

[Embodiment 3] In the embodiments described above, the method of using the laser CVD wiring for forming the wiring between the connection parts has been described. In this embodiment, a method in which a power supply wiring is used as a spare wiring and a laser CVD wiring is not used will be described. In addition, as shown in FIG. 20, there has been a conventional auxiliary wiring, but the direction of the auxiliary wiring is limited to the long side direction of the power supply wiring.

This embodiment is performed by the embodiment shown in FIG. In this embodiment, the slit 5 is formed in the power supply wiring 1 instead of the window. Japanese Patent Application Laid-Open No. 3-36750 discloses that a slit is provided in a power supply line, but the direction of the slit is different from that of the present embodiment by 90 °. The effect obtained in the embodiment cannot be expected.

In the present embodiment, the slit 5 is connected to the power supply wiring 1
Are formed along the short side direction. As described in Embodiment 1, the signal wiring extending in the short side direction is likely to extend between the power supply wirings, but the signal wiring extending in the long side direction is less likely to extend between the power supply wirings. In some cases, the through-holes 3 between the first-layer signal wiring 7 and the power supply wiring 1 are formed side by side in the short side direction, and it is necessary to form the slit 5 along this. This is the reason for forming the slit 5 in the side direction.

Here, the slit width is set in accordance with the pitch of the first layer signal wiring 7 and the slit pitch is set in the first layer signal wiring 7.
Is set to three times the pitch of The middle line of the slit 5 is made to coincide with the middle line of the gap of the first layer signal wiring 7. However, the slit 5 cannot be formed in the line where the through hole 3 to the power supply wiring 1 exists. With such a setting, the second-layer signal wiring 8 extending in the long side direction of the power supply wiring 1 is opened upward from the gap of the slit 5, and the possibility of making them open to them becomes easy.

As shown in the wiring modification example shown in FIG. 3, the connection of the wiring from the connecting portion 11A to the connecting portion 11B is performed by connecting the predetermined second-layer signal wiring 8 and the power supply wiring 1 in the shape of a sword. This is possible through the power supply wiring 1. However, the power supply wiring 1 is connected at the lateral end since it originally has a purpose of applying a constant voltage. For this reason, the cutting part 12 is connected to the connecting part 1.
It is provided outside 1A and the connecting portion 11B. In addition, connection section 1
In order to connect the wiring to the adjacent power supply wiring portion or further away from 1C, the power supply wiring 1 is connected to the conventional spare wiring 22.
May be cut off and used as wiring for connection.

Since the connection at each connection portion is short, it is not always necessary to employ laser CVD capable of forming low-resistance wiring, and connection by focused ion beam CVD is sufficient. As a connection method, for example, as shown in FIG. 4, windows are opened in the power supply wiring 1 and the signal wiring 7 to be connected, and the focused ion beam is applied to the CV so as to include them.
The filling metal 13 may be precipitated by irradiation in a D gas atmosphere. Alternatively, as shown in FIG. 5, the power supply wiring 1 and the signal wiring 7 are formed as one processing hole,
May be precipitated. Further, a method shown in FIG. 6 in which a window is opened through the power supply wiring 1 to the signal wiring 7 and the filling metal 13 is deposited therefrom is also possible. If you connect
Any process can be connected. However, when the connection resistance becomes a problem, a method of processing in two steps as shown in FIG. 13 is also effective.

In the method shown in FIG. 6, when the processing proceeds from the top, the insulating layer is processed after the upper power supply wiring 1 comes off, and the insulator sputtered during the processing is processed. Attaches to sidewall of hole. The adhesion layer increases the connection resistance of the upper and lower wirings.

On the other hand, in the method shown in FIG. 7, during processing of the insulating layer between the two wiring layers, the sputtered insulating material is shielded by the shelf formed in the middle of the power supply wiring 1 so that the processing is performed. Since the filled metal 13 does not adhere to the side wall of the power supply wiring 1 and the power supply wiring 1 and the signal wiring 7 are in contact with the exposed surfaces of the respective metals, a low connection resistance can be obtained.
In FIG. 3, the connection with the auxiliary wiring 22 also requires the connection with the power supply wiring 1, which includes a part where the power supply wiring 1 has a window opened and a part where the auxiliary wiring 22 has a window opened. As CV
Irradiation with a focused ion beam in an atmosphere of D gas allows deposition and connection of a metal film. Here, the shape of the precipitation is L-shaped in this example, but this is usually provided with a function of scanning an arbitrary shape in the focused ion beam, and can be easily executed by using the function.

If the width, pitch and position of the slit 5 are set to 1.5 times and 2.5 times the signal wiring pitch, for example, as shown in FIG. From the gap of the slit 5, not only the second-layer signal wiring 8 but also the first-layer signal wiring 7 can be processed, so that the ease of wiring correction is improved. However, it is necessary to give priority to the function as the power supply wiring, and to follow the slit design conditions that allow a necessary current to flow. Within this range, it is desirable to increase the processing location from the slit gap as much as possible.

[Embodiment 4] In recent LSIs, not only a power supply wiring provided in the uppermost layer but also a shield wiring for avoiding disturbance is further provided in an upper layer. The power supply wiring and the shield wiring are often formed in directions orthogonal to each other. Therefore, when such wide wirings are present, it is difficult to process the wiring below them, and it is essential to form a pattern on them for facilitating focused ion beam processing. Although it is possible to select a method similar to that of the first embodiment, an example similar to that of the second embodiment will be described here.

FIG. 9 shows this embodiment. Basically, the concept is the same as that of the second embodiment.
And a window 5 is formed in a wide wiring having two layers. The window 5 is, as described in the second embodiment,
A condition is set as a rule, which is a position of a through hole between wiring layers to be processed and a position where one of the signal wirings is stopped there. In this case, since the two wide wirings are orthogonal to each other, it is possible to form an orthogonal wiring as a spare wiring, and there is also an effect that the expandability of wiring formation is wider than in the second embodiment. .

The wiring correction method shown in FIG. 9 is also the same as that described in the second embodiment.
Are connected by laser CVD wiring 24. In this case, it is necessary to make the size of the window 5 larger than that of the second embodiment in consideration of the fact that the processing hole becomes tapered due to the formation of the connection hole because the insulating layer above the signal wiring is thick. However, the window to be actually set is determined depending on the structure of each LSI. If two layers of wide wiring exist on the signal wiring, and if cutting processing is not performed through the window, a large processing hole is formed through the shield wiring 2 to the insulating layer thereunder. Then, a processing hole is further drilled through the power supply wiring 1 to the insulating layer thereunder, and further a three-step processing is performed such that a processing hole for cutting the signal wiring is formed therein. Need to avoid short circuit.

[Embodiment 5] In this embodiment, a slit forming method in the case where shield wiring is provided in addition to power supply wiring will be described. In the fourth embodiment, the slit is formed in the short side direction of the power supply wiring. However, if the slit is formed in the same direction as the shield wiring, the slits are orthogonal to each other. Can be formed. The use of this wiring is useful for realizing a wiring correction process that requires a short time in application of wiring correction in which logic is changed by adding wiring. FIG. 10 shows the shapes of the power supply wiring and the shield wiring.

In FIG. 10, the slit is formed in the same manner as described in the fourth embodiment. The middle line and the middle line of the first layer signal wiring 7 are matched. The middle line of the slit of the shield wiring 2 is made to coincide with the middle line of the second-layer signal wiring 8. Thereby, the parent wiring is arranged to be viewed from the slit, and the focused ion beam processing and film formation for wiring correction are facilitated.

An example of wiring correction is shown in FIG.
A part of the power supply wiring 1 cut by the cutting unit 12 is used from the connection unit 11F to the connection unit 11G. In addition, the power supply wiring 1 and the shield wiring 2 are used from the connection portion 11H to the connection portion 11I. Since the power supply wiring 1 and the shield wiring 2 are on different layers and are orthogonal to each other, it is easy to intersect a wiring path added by wiring correction. As described in the fourth embodiment, the connection portion 11 can be formed by the method shown in FIGS.

The connection section 13 connects the power supply wiring 1 and the shield wiring 2. This is similar to the connection between the power supply wiring and the signal wiring shown in FIGS.
As shown in (1) and (2), a method in which a hole penetrating both wiring layers is processed, and then the filling metal 13 is deposited by focused ion beam CVD, or the processing method in FIG. 14 is also possible.

In FIG. 14, the beam scanning area 16 is scanned in the scanning direction 15 toward the intersection of the sub-wiring of the power supply wiring 1 and the sub-wiring of the shield wiring 2. Usually, the focused ion beam is scanned a number of times in the processing area to perform processing such that the processing bottom surface becomes flat. At this time, the beam scanning speed is adjusted so as to be lower than in the past, and once. The processing is performed by setting the conditions for processing to a predetermined depth in the scanning of. In this processing method, as shown in FIG. 15, the substance sputtered by the processing comes to adhere in the direction opposite to the beam scanning direction 15, and almost no spattered substance is formed at the intersection of the wires set as the final beam scanning line. No clean surface can be exposed. Focused ion beam CV there
If the filler metal 13 is deposited with D, connection with low resistance is possible. This is also effective as one method of connecting two layers.

When one logic does not operate in the logic change, it is necessary to switch to a normal logic. For this case, the spare cell 30 is connected to the sub-wiring portion of the shield wiring 2 as shown in FIG. Keep it. In some cases, it becomes possible only by checking the operation of the LSI by reconnecting the wiring from the defective cell to the connection wiring 32 to the spare cell 30. In FIG. 16, the spare cell 30 is shown separately for the sake of convenience in the drawing, but is actually one of the cells built in the LSI. This may be a cell that is not operated originally, or a cell that operates less frequently may be selected and connected.

[Embodiment 6] The above embodiment is directed to an LSI
A description has been given of several methods in which power supply wiring and shield wiring, which are indispensable for the operation, are partially formed by patterning them in order to facilitate wiring correction. In the case of ASICs where it is necessary to start up the logic corresponding to each customer as soon as possible, for the purpose of facilitating debugging of the logic part at the development stage, make a spare wiring of the above-mentioned childlike pattern like above It is effective.

FIG. 17 shows such a form, in which a spare wire 34 in the shape of a pen and a similar spare wire 35 orthogonal to it are formed. Under these layers, a logic wiring pattern to be actually operated is formed. The auxiliary wirings in the upper layer are connected to the ground when the LSI is completed in order to cause various problems if they are not electrically connected. Pads may be used for this, and FIG. 1
A bump such as 7 may be used. Here, bump 2
If the connection to 0 is also a sashimi pattern, the connection can be made by opening a through hole 29 through the gap between the lower sashimi and the upper sashimi, and the restriction on the formation position of the bump 20 is eased. As the form of the wiring correction, as described in the sixth embodiment, the same processing and film forming process as in FIG. 10 can be adopted.

Further, in this embodiment, since the spare wiring does not have a function as a power supply wiring, it is not necessary to consider the position of the through hole from the lower layer in the patterning, and it is not necessary to consider the current capacity. In addition, the restrictions on the pattern formation conditions of the spare wiring are gradual, for example, the wiring can be made thin and the gap can be made large.

This pattern is used until the logic is determined in the development stage of the ASIC, and is used to shorten the period. After that, it is not necessary to keep it. However, since this pattern has an effect as a shield, The state in which this pattern is left can be shipped as a product.

As a pattern to be formed on the uppermost layer during the development stage of the ASIC, the pattern shown in FIG. 17 is suitable and desirable for drawing wiring in both the vertical and horizontal directions. But,
If increasing the number of steps for forming two layers is a problem,
As shown in FIG. 18, a pattern extending vertically and horizontally may be formed in one layer. In FIG. 18, the pattern of the spare wiring 33 is inclined as an example to match the case where logic cells having similar functions are arranged in an oblique direction. The method of matching with the direction is more general. Also, in FIG. 18, the direction of the lantern is from the upper right direction to the lower left direction. This is a pattern that is replaced for each area, and a method that facilitates the routing of the correction wiring using the auxiliary wiring in both the vertical and horizontal directions is also available. is there. The patterning of the spare wiring layer depends on the wiring pattern of the target ASIC, and it is necessary to design a suitable pattern from the type.

[0053]

According to the present invention, in the correction of wiring by applying focused ion beam processing / film formation and laser CVD, a narrow groove employed for preventing short-circuiting when wiring is drawn out from under a wide power supply wiring. Do not use the notch that is processing,
Wiring correction is possible, shortening the time required for correction,
This is effective in improving the correction yield. Further, this effect widens the application range of wiring correction, and improves the effectiveness as a tool for shortening the LSI development period.

[Brief description of the drawings]

FIG. 1 is a plan view of a logic LSI showing a first embodiment of the present invention.

FIG. 2 is a plan view of a logic LSI showing a second embodiment of the present invention.

FIG. 3 is a plan view of a logic LSI showing a third embodiment of the present invention.

FIG. 4 is a sectional view of a logic LSI showing a third embodiment of the present invention.

FIG. 5 is a cross-sectional view of a logic LSI showing a third embodiment of the present invention.

FIG. 6 is a sectional view of a logic LSI showing a third embodiment of the present invention.

FIG. 7 is a cross-sectional view of a logic LSI showing a third embodiment of the present invention.

FIG. 8 is a plan view of a logic LSI according to a third embodiment of the present invention.

FIG. 9 is a plan view of a logic LSI showing a fourth embodiment of the present invention.

FIG. 10 is a plan view of a logic LSI showing a fifth embodiment of the present invention.

FIG. 11 is a plan view of a logic LSI showing a fifth embodiment of the present invention.

FIG. 12 is a sectional view of a logic LSI according to a fifth embodiment of the present invention.

FIG. 13 is a sectional view of a logic LSI showing a third embodiment of the present invention.

FIG. 14 is a plan view of a logic LSI showing a fifth embodiment of the present invention.

FIG. 15 is a cross-sectional view of a logic LSI illustrating reattachment of a sputtered material.

FIG. 16 is a plan view of a logic LSI showing a fifth embodiment of the present invention.

FIG. 17 is a plan view of a logic LSI showing a sixth embodiment of the present invention.

FIG. 18 is a plan view of a logic LSI showing a sixth embodiment of the present invention.

FIG. 19 is a cross-sectional perspective view of a logic LSI in which wiring has been modified in a conventional technique.

FIG. 20 is a plan view of a logic LSI on which wiring correction has been performed by a conventional technique.

FIG. 21 is a cross-sectional view of a logic LSI in which wiring has been modified by a conventional technique.

[Explanation of symbols]

1: power supply wiring, 2: shield wiring, 3: through hole,
4 Window, 7 First layer signal wiring, 8 Second layer signal wiring, 9
... 3rd layer signal wiring, 10 ... 4th layer signal wiring, 11 ... connection section, 12 ... cut section, 13 ... filled metal, 14 ... through hole, 15 ... beam scanning direction, 16 ... beam scanning area, 1
7: reattachment, 22: spare wiring, 23: connection, 24 ...
Laser CVD wiring, 27 cutting part, 28 focused ion beam CVD wiring, 30 spare cell, 31 spare cell wiring, 32 spare cell wiring, 33 spare wiring, 34 spare wiring, 35 spare wiring, 41 ... insulating layer, 42 ... substrate, 4
3 Focused ion beam, 44 CVD gas, 45 filling metal, 46 laser beam, 47 CVD gas, 48
Laser CVD wiring.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshinobu Mizumura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. Hitachi, Ltd., Production Technology Laboratory

Claims (12)

[Claims] 1. A semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate and a power supply wiring layer is formed thereon, wherein the power supply wiring layer has a wiring layer below the power supply wiring layer. A plurality of windows are formed corresponding to the wiring of (1). 2. The semiconductor device according to claim 1, wherein said plurality of windows are formed at an interval corresponding to a position and a pitch in a width direction of the wiring of said lower wiring layer. 3. The semiconductor device according to claim 1, wherein each of the plurality of windows is formed to have a width larger than a width of the lower wiring layer in a width direction. 4. A semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate and a power supply wiring layer is formed thereover, wherein the power supply wiring layer above the wiring of the wiring layer is provided with the wiring layer. A semiconductor device, wherein a window larger than the width of the wiring is formed. 5. The semiconductor device according to claim 4, wherein a plurality of the windows are formed at intervals corresponding to a position and a pitch in a width direction of the wiring of the lower wiring layer. 6. A semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate, and a power supply wiring layer is formed thereover, wherein the power supply wiring layer is provided under the power supply wiring layer. A plurality of windows are formed corresponding to the wiring of (1), and a wiring connected to the wiring of the lower wiring layer through the window is formed. 7. The semiconductor device according to claim 6, wherein a wiring connected to the wiring of the wiring layer is electrically insulated from the power supply wiring layer at the window. 8. A semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate and a power supply wiring layer is formed thereover, wherein the power supply wiring layer is provided under the power supply wiring layer. A plurality of windows are formed corresponding to the wirings, and wirings connecting different wirings of the lower wiring layer are formed through the plurality of windows. 9. The semiconductor device according to claim 8, wherein a wiring connecting the different wirings is electrically insulated from the power supply wiring layer at the window. 10. A semiconductor device having an insulating layer or a wiring layer laminated on a substrate, a power supply wiring layer having a window formed thereon, and a surface covered with an insulating film is irradiated with a focused ion beam. The wiring portion of the wiring layer below the window portion is exposed inside the window portion, and is connected to the exposed wiring by irradiating the focused ion beam while supplying a material gas near the window portion. A wiring correction method, comprising: forming a wiring film in an insulating film covering the surface. 11. A semiconductor device in which an insulating layer or a wiring layer is laminated on a substrate, a power supply wiring layer having a plurality of windows is formed thereon, and a semiconductor device having a surface covered with an insulating film is irradiated with a focused ion beam. And a first wiring portion of the wiring layer below the first window portion of the plurality of window portions and a second wiring portion of the wiring layer below the second window portion of the plurality of window portions. Is exposed to the focused ion beam while supplying a material gas, and the first wiring portion below the first window portion and the second wiring portion below the second window portion are exposed. A wiring for electrically connecting the wiring portion to the wiring portion on the insulating film covering the surface. 12. The wiring correction method according to claim 11, wherein said first wiring part and said second wiring part are in different wiring layers.