JPH08191330A - System and method for encoding, system and method for decoding, device and method for recording encoded data, device and method for transmitting encoded data, and recording medium - Google Patents

Abstract

PURPOSE: To obtain accurate decode data which vary in bit rate without reference to delay fluctuations of a network. CONSTITUTION: A packetizing circuit 82 packetizes data inputted from an encoder 1 and adds a time stamp to the packet. The data packetized by the packetizing circuit 82 are transmitted to the decoding system through a buffer memory 83, a composing circuit 84, and the network 3. Each time data of one packet are stored in the buffer memory 83, an interval detector 85 sends the count value of a counter 87 at the point of time to the decoding system as the interval of the packet from the last packet. The decoding system detects the interval data and corrects the delay fluctuations of the packets.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention digitizes audio data and video data, and, for example, MPEG (Moving)
According to the Picture Experts Group) method, these data are packetized and transmitted through a predetermined network,
The present invention relates to an encoding system and an encoding method, a decoding system and a decoding method, an encoded data recording apparatus and an encoded data recording method, an encoded data transmission apparatus and an encoded data transmission method, and a recording medium which are suitable for use when the receiving side receives the information. .

[0002]

2. Description of the Related Art FIG. 12 shows a configuration example of a conventional data transmission system.

The encoder 1 encodes, for example, a video signal and an audio signal as data to be transmitted in MPEG.
-2 encoding, system encoder 2
To enter. The system encoder 2 packetizes the input video signal and audio signal, adds a time stamp, and transmits the time stamp on the network 3.
This network 3 is, for example, an ATM (Asynchronous T
ransfer Mode: Asynchronous transfer mode) The network is used for statistical multiplexing. That is, when the data of a predetermined packet is transmitted, another packet is held in the buffer memory. Then, when the transmission of a predetermined packet is completed, another packet (cell) is read from the buffer memory and transmitted, which is executed on a large number of nodes constituting the network 3.

The data transmitted via the network 3 is input to the system decoder 4. The system decoder 4 is composed of a time stamp extraction circuit 11, a PLL circuit 12, and a system decoding unit 13, as shown in FIG. 13, for example. System decoding unit 13
Cancels packetization of the input packetized audio data and video data, and outputs the resulting audio stream and video stream to the decoder 5.

On the other hand, the time stamp extraction circuit 11 extracts the time stamp included in the input data and outputs it to the PLL circuit 12. The PLL circuit 12 uses the input time stamp to generate a system clock and outputs it to the decoder 5. In the case of the MPEG-2 system, the frequency of this system clock is 27 MHz.

The decoder 5 decodes the audio data and video data streams supplied from the system decoding unit 13 based on the system clock input from the PLL circuit 12.

The PLL circuit 12 is constructed, for example, as shown in FIG. The time stamp extracted by the time stamp extraction circuit 11 is input to the subtractor 21. This time stamp is used for PCR (Program Cl
ock Reference) has been. This transports
The stream is a fixed packet of 188 bytes and is transmitted as a fixed rate stream. PCRs are sent at intervals of at least 0.1 seconds. When transmitted, it is placed in the header of the packet.

In this PCR, the encoding timing in the encoder 1 is represented by the count value of the system clock in the system encoder 2. The subtractor 21 uses the PCR and the system clock of the counter 24 (system clock in the system decoder 4).
The difference from the count value of is calculated. The output of the subtractor 21 is
It is input to a low pass filter (LPF) 22, smoothed, and then input to a DA (Digital / Analog) converter / VCO (voltage controlled oscillator) 23. DA converter and V
The CO 23 converts the digital signal input from the low pass filter 22 into an analog signal, and uses the analog signal as a control voltage to generate a system clock having a frequency corresponding to the control voltage.

This system clock is supplied to the decoder 5 and also input to the counter 24 to be counted. Then, the count value of the counter 24 is supplied to the subtractor 21 as a signal representing the frequency and phase of the system clock at that time.

[0010]

As described above, when the data encoded on the transmitting side is transmitted to the receiving side via the network 3 and is decoded on the receiving side,
If the time stamps arrive at the decoder side at exactly the same intervals, it is easy to synchronize the system clock on the decoder side with the system clock on the encoder side.

However, in reality, the network 3
Above, delay fluctuations occur. That is, the network 3 statistically multiplexes data for each packet, but in order to transmit a predetermined packet and another packet on one transmission path, when one packet is transmitted,
The other packet needs to be stored in the buffer memory and kept waiting. Then, when the transmission of one of the packets is completed, the processing of transmitting the other packet which is made to stand by in the buffer memory is executed. Since such processing is performed on a large number of nodes (ATM switches) in the network 3, the packets (A
TM cells) have random delay fluctuations.

In addition, the encoder 1 performs an encoding process at a variable bit rate. As a result, a complex image has a large amount of data, and a simple image has a small amount of data.

On the other hand, in the transport stream, since the packet length is a constant value of 188 bytes, eventually, when the data amount is large, the packet arrival interval becomes short and the data amount becomes small. When the number is small, the packet arrival interval becomes long. That is, the data rate at the time of transmitting a packet changes according to the generated code amount of the encoder 1.

If such changes in arrival intervals and delay fluctuations are left as they are, it becomes difficult for the decoder side to perform accurate decoding.

Therefore, in order to eliminate this random change, it is conceivable to rewrite the time stamp, for example, with a value in consideration of the change. However, doing so complicates the configuration of the network 3.

It is also conceivable that the PLL circuit 12 absorbs random changes. However, since this change is very large, in order for the PLL circuit 12 to absorb this, it takes a considerably long time for the PLL circuit 12 to synchronize, or if the PLL circuit 12 has a complicated circuit configuration. I have no choice.

Further, even when the data output from the system encoder 2 is not directly transmitted but is once recorded and transmitted on, for example, a recording medium, the above-mentioned problem occurs.

The present invention has been made in view of such a situation, and it is possible to absorb a change in a packet arrival interval and a change in which delay fluctuations are combined without complicating the structure. .

[0019]

An encoding system according to claim 1, wherein the encoding means encodes the data at a variable bit rate, and the packetizing means adds the time stamp to the encoded data to packetize the encoded data. And a transmission unit for transmitting the interval data corresponding to the interval calculated by the calculation unit, and the packet conversion unit for calculating the interval between the packets packetized by the packetization unit. Is characterized by.

A decoding system according to a second aspect of the present invention detects storage means for storing variable bit rate data transmitted in units of packets, and interval data corresponding to an interval between packets transmitted together with the data. An interval data detecting means and a delay time controlling means for controlling a delay time from the storage of the packet in the storage means to the reading of the packet in correspondence with the detection result of the interval data detecting means are provided. .

The storage means is provided with a first storage means for storing a plurality of packets and a second storage means for storing one packet read from the first storage means. Controls the first storage means and the second storage means such that the total time of the delay time of the first storage means and the delay time of the second storage means becomes a predetermined time set in advance. Can be allowed to. In addition, a storage amount detection unit that detects the amount of packets stored in the storage unit, and an output rate control that controls the output rate at which the packets are read from the storage unit and output according to the detection result of the storage amount detection unit. And means may be further provided.

According to a sixth aspect of the present invention, data is encoded at a variable bit rate, the encoded data is packetized by adding a time stamp, the encoded data is packetized, and the packet interval is calculated. It is characterized in that the interval data corresponding to the interval is transmitted together with the packet.

In the decoding method according to the seventh aspect, the variable bit rate data transmitted in units of packets is stored in the memory, and the interval data corresponding to the packet interval is extracted from the data and extracted. The data stored in the memory is read according to the interval data,
The output rate is controlled, the time stamp is extracted from the data output from the memory, the system clock is generated using the extracted time stamp, and the data output from the memory is generated using the generated system clock. Is to be decoded.

The encoding system according to claim 8 is
Encoding means for encoding data at a variable bit rate, packetizing means for adding encoded time stamps to the encoded data, and setting means for setting a data rate for transmitting a packet for each predetermined section. And a calculation means for calculating a packet transmission interval corresponding to the data rate, and a transmission means for transmitting the packet at the transmission interval calculated by the calculation means together with the data rate data corresponding to the data rate. Is characterized by.

According to a ninth aspect of the present invention, the encoding method encodes data at a variable bit rate, adds a time stamp to the encoded data to form a packet, and transmits the packet at predetermined intervals. A data rate is set, a packet transmission interval is calculated in accordance with the data rate, and the packet is transmitted at the calculated transmission interval together with the data rate data corresponding to the data rate.

According to a tenth aspect of the present invention, there is provided an encoded data recording apparatus, wherein input encoded data encoded at a variable bit rate is added with a time stamp into a packet and data when the packet is transmitted. Storage means for storing the data rate data corresponding to the rate, and reading the data stored in the storage means,
A recording means for recording on a recording medium is provided.

The encoded data recording method according to the eleventh aspect of the present invention is a method in which input encoded data encoded at a variable bit rate is packetized with a time stamp, and data for transmitting the packet. Stores the data rate data corresponding to the rate,
It is characterized in that the stored data is read and recorded in a recording medium.

According to the twelfth aspect of the present invention, in the encoded data transmission device, the encoded data encoded at the variable bit rate is packetized by adding a time stamp, and the packet corresponds to the data rate at the time of transmitting the packet. Reading means for reading data from a recording medium recorded together with the data rate data, detecting means for detecting the data rate data from the data, and calculating means for calculating the packet transmission interval corresponding to the data rate data. And a transmission unit that transmits packets together with the data rate data at the transmission intervals calculated by the calculation unit.

In the encoded data transmission method according to the thirteenth aspect, encoded data encoded at a variable bit rate is added to a packet with a time stamp added, and the packet corresponds to the data rate at the time of transmitting the packet. Data is read from the recording medium that is recorded together with the data rate data, the data rate data is detected from the data, and the data rate data is detected.
The packet transmission interval is calculated, and the packet is transmitted at the calculated transmission interval together with the data rate data.

In the recording medium according to the fourteenth aspect, encoded data encoded at a variable bit rate is packetized by adding a time stamp, and the data rate corresponds to the data rate at the time of transmitting the packet. It is recorded together with the data.

[0031]

In the encoding system according to the present invention, the encoding means encodes the data at a variable bit rate, and the packetizing means packetizes the encoded data by adding a time stamp. There is. Further, the calculating means calculates an interval between the packets packetized by the packetizing means, and the transmitting means stores the data packetized by the packetizing means,
The interval data corresponding to the interval calculated by the calculating means is transmitted.

In the decoding system according to the second aspect, the storage means stores variable bit rate data transmitted in units of packets, and the interval data detection means has an interval between packets transmitted together with the data. The interval data corresponding to is detected.
The delay time control means is adapted to control the delay time from when the packet is stored in the storage means to when it is read out, corresponding to the detection result of the interval data detection means.

In the encoding method according to the sixth aspect, the data is encoded at a variable bit rate, and the encoded data is packetized with a time stamp added. In addition, the packet interval of the encoded data is calculated, and the interval data corresponding to the interval is transmitted together with the packet.

In the decoding method according to the seventh aspect, variable bit rate data transmitted in units of packets is stored in a memory, and interval data corresponding to packet intervals is extracted from the data. Has been done. In addition, the output rate of reading and outputting the data stored in the memory is controlled corresponding to the extracted interval data, and the time stamp is extracted from the data output from the memory. Further, the system clock is generated using the extracted time stamp, and the data output from the memory is decoded using the generated system clock.

In the encoding system according to claim 8, the encoding means encodes the data at a variable bit rate, and the packetizing means adds a time stamp to the encoded data to form a packet. There is. Also, the setting means sets a data rate for transmitting a packet for each predetermined section,
The calculation means is adapted to calculate the packet transmission interval in accordance with the data rate. Then, the transmission means transmits the packet together with the data rate data corresponding to the data rate at the transmission intervals calculated by the calculation means.

In the encoding method according to the ninth aspect, the data is encoded at a variable bit rate, the encoded data is added with a time stamp into a packet, and the packet is transmitted every predetermined section. The data rate at that time is set, and the packet transmission interval is calculated according to the data rate. Then, the packet is transmitted at the calculated transmission interval together with the data rate data corresponding to the data rate.

In the encoded data recording device according to the tenth aspect, the storage means stores the input encoded data encoded at the variable bit rate into a packet with a time stamp and the packet. The data rate data corresponding to the data rate at the time of transmission is stored, and the recording means reads the data stored in the storage means and records it on the recording medium.

According to the eleventh aspect of the present invention, in the encoded data recording method, the input encoded data encoded at the variable bit rate is added with a time stamp into a packet, and the packet is transmitted. The data rate data corresponding to the data rate is stored, and the stored data is read and recorded on the recording medium.

According to the twelfth aspect of the present invention, in the encoded data transmission device, the read means converts the encoded data encoded at the variable bit rate into a packet by adding a time stamp, and transmits the packet. The data is read from the recording medium recorded together with the data rate data corresponding to the data rate, and the detecting means detects the data rate data from the data. The calculating means calculates the packet transmission interval in accordance with the data rate data, and the transmitting means transmits the packet together with the data rate data at the transmission interval calculated by the calculating means. .

In the encoded data transmitting method according to the thirteenth aspect, encoded data encoded at a variable bit rate is added with a time stamp into a packet, which corresponds to the data rate at the time of transmitting the packet. The data is read from the recording medium recorded together with the data rate data, and the data rate data is detected from the data. Also, the packet transmission interval is calculated corresponding to the data rate data, and together with the data rate data,
The packets are transmitted at the calculated transmission intervals.

In the recording medium according to claim 14,
The encoded data encoded at the variable bit rate is added as a packet with a time stamp,
It is recorded together with data rate data corresponding to the data rate at the time of transmitting the packet.

[0042]

EXAMPLES Examples of the present invention will be described below, but before that, in order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means will be described. In parentheses after the, add the corresponding example (however, one example),
The features of the present invention will be described as follows.

That is, the encoding system according to the first aspect is an encoding means for encoding data at a variable bit rate (for example, the encoder 1 shown in FIG. 1).
Generating means for generating a time stamp to be added to the data (for example, the time stamp generating circuit 81 shown in FIG. 1), and packetizing means for adding the time stamp to the encoded data and packetizing the encoded data (for example, FIG. 1), a computing means for computing the interval between the packets packetized by the packetizing means (for example, the interval detector 85 shown in FIG. 1), and the packetizing means. It is characterized by comprising a packet and a transmission means (for example, the synthesizing circuit 84 shown in FIG. 1) for transmitting the interval data corresponding to the interval calculated by the operation means.

A decoding system according to a second aspect of the present invention transmits the data together with the storage means (for example, the buffer memories 41A and 41B shown in FIG. 4) for storing the variable bit rate data transmitted in units of packets. Interval data detecting means (for example, the interval detecting circuit 61 shown in FIG. 4) for detecting the interval data corresponding to the interval of the incoming packet, and the packet is stored in the storing means in correspondence with the detection result of the interval data detecting means. A delay time control means (for example, the delay time control circuit 63 shown in FIG. 4) for controlling the delay time from the storage to the reading is provided.

In the decoding system according to the third aspect, the storage means includes a first storage means (for example, a buffer memory 41A shown in FIG. 4) for storing a plurality of packets,
The second storage means (for example, the buffer memory 41B shown in FIG. 4) storing one packet read from the first storage means is provided, and the delay time control means is provided with the delay time of the first storage means. And the delay time of the second storage means is set to a predetermined time set in advance,
The storage means and the second storage means are controlled.

The decoding system according to claims 4 and 5 includes a storage amount detecting means (for example, the counter 43 shown in FIG. 4) for detecting the amount of packets stored in the storage means, and a storage amount detecting means. Corresponding to the detection result of the means,
It is characterized by further comprising an output rate control unit (for example, an output rate control circuit 55 shown in FIG. 4) for controlling the output rate of reading the packet from the storage unit and outputting the packet.

The encoding system according to claim 8 is
Encoding means for encoding data at a variable bit rate (for example, encoder 1 shown in FIG. 8), generating means for generating a time stamp to be added to data (for example, time stamp generating circuit 81 shown in FIG. 8),
A packetizing means (for example, the packetizing circuit 82 shown in FIG. 8) for converting the encoded data into a packet by adding a time stamp, and a setting for setting a data rate for transmitting the packet for each predetermined section. Means (for example, the section bit rate value setting circuit 91 shown in FIG. 8) and a calculating means for calculating the packet transmission interval corresponding to the data rate (for example, the interval calculation setting circuit 93 shown in FIG. 8). , And transmission means (for example, the packet output circuit 92 shown in FIG. 8) for transmitting packets at the transmission intervals calculated by the calculation means together with the data rate data corresponding to the data rate.

According to a tenth aspect of the present invention, there is provided an encoded data recording apparatus, wherein input encoded data encoded at a variable bit rate is packetized with a time stamp and data when the packet is transmitted. Storage means for storing data rate data corresponding to the rate (for example, the buffer 111 shown in FIG. 9)
And a recording unit that reads out the data stored in the storage unit and records it on a recording medium (for example, the recording circuit 11 shown in FIG. 9).
2) and the like.

According to the twelfth aspect of the present invention, in the encoded data transmission device, the encoded data encoded at the variable bit rate is packetized by adding a time stamp, and the packet corresponds to the data rate at the time of transmitting the packet. Read-out means for reading data from a recording medium recorded together with the data rate data (for example,
A read control circuit 102 shown in FIG. 11), and a detection unit for detecting data rate data from the data (for example, a bit rate detector 104 shown in FIG. 11),
A calculation unit that calculates the packet transmission interval corresponding to the data rate data (for example, the interval calculation setting circuit 105 shown in FIG. 11), and the packet together with the data rate data at the transmission interval calculated by the calculation unit. Transmission means for transmitting (for example, the transmitter 106 shown in FIG. 11)
And characterized in that:

Of course, this description does not mean that each means is limited to the above.

FIG. 1 shows a configuration example of a system encoder 2 which constitutes the encoding system of the present invention. Also in this embodiment, the data transmission system is configured similarly to the case shown in FIG. The encoding system is composed of an encoder 1 and a system encoder 2, of which the system encoder 2 is configured as shown in FIG.

In this embodiment, the encoded video data and audio data supplied from the encoder 1 are input to the packetizing circuit 82 and packetized. The time stamp generation circuit 81 also generates, for example, a time stamp as information (time information) corresponding to the encoding time output by the encoder 1, and outputs the time stamp to the packetization circuit 82. The packetizing circuit 82 adds this time stamp to the header of the packet.

The packetized data output by the packetizing circuit 82 is stored in the packet size buffer memory 83.
After being supplied to the network 3 and stored therein, it is read out again and transmitted to the network 3 via the combining circuit 84.

On the other hand, the interval detector 85 receives the detection signal when one packet of data is stored in the buffer memory 83.

The counter 87 counts the clock output from the oscillator (OSC) 86 and outputs the count value to the interval detector 85. When the interval detector 85 receives a signal indicating that one packet of data has been stored from the buffer memory 83, the interval detector 85 determines the count value held by the counter 87 at that time as data indicating the packet interval (packet length). Is constant, the data indicating the packet interval (interval data can be said to correspond to the data rate at the time of transmitting the packet) is taken in, and this count value is output to the combining circuit 84. The synthesizing circuit 84 transmits this interval data on the network 3.

When the interval detector 85 outputs the interval data, the counter 87 is reset and starts the timing operation until the next data is stored in the buffer memory 83 for one packet.

Thus, in this embodiment,
The video data and the audio data encoded by the encoder 1 are packetized by the system encoder 2 and transmitted on the network 3, and the interval data is also transmitted on the network 3 together.

FIG. 2 shows a temporal relationship between packet data synthesized by the synthesis circuit 84 and output, and packet interval data. As shown in the figure, the nth packet interval data is transmitted prior to the nth packet data.

In the above embodiment, this interval data is transmitted on the network 3 as the data of the channel (format) different from the packetized data, but this interval data is also similar to the time stamp and the like. It is also possible to packetize and transmit.

As described above, the data transmitted via the network 3 is the same as in the conventional case shown in FIG.
It is supplied to the system decoder 4 and a system clock is generated.

FIG. 3 shows a configuration example of the system decoder 4. As shown in the figure, the data transmitted from the network 3 is input to the adjustment circuit 31, where the adjustment processing corresponding to the change of the packet interval and the delay fluctuation is performed, and then the data is transmitted to the system decoding unit 13. It is input, decomposed into an audio stream and a video stream, and then supplied to the decoder 5.

Further, the time stamp extraction circuit 11 extracts the time stamp from the output of the adjustment circuit 31, and outputs the time stamp PL.
It is output to the L circuit 12. The PLL circuit 12 is shown in FIG.
The system clock is constructed similarly to the case shown in FIG.

FIG. 4 shows a configuration example of the adjusting circuit 31. The packetized data transmitted via the network 3 is input to the buffer memory 41A, temporarily stored therein, and then read out again.
It is supplied to B, stored again there, and then further read therefrom and outputted to the decoder 5. The buffer memory 41A has a capacity corresponding to a plurality of integer number of packets (that is, is adapted to store a plurality of integer number of packets), and the buffer memory 41B has a capacity of packet size (1 Packet capacity).

The interval detection circuit 61 detects interval data from the data transmitted from the network 3 and outputs the detection output to the parameter setting circuit 62. The parameter setting circuit 62 has a sampling time for detecting the section delay time and the additional delay time in the delay time control circuit 63 and the packet storage amount of the buffer memory 41A in the sampling time generator 49, corresponding to the detected interval data. Parameters such as ST, the reference level REF in the reference level generator 45, the output rate OR in the conversion circuit 51, the maximum value MAXR of the output rate, the minimum value MINR of the output rate, and the change width Δ of the output rate are set to predetermined values. .

The packet detector 42 uses the buffer memory 4
When one packet of data is stored in 1A, it is detected and the detection pulse is supplied to the addition input terminal of the counter 43. The subtractor input terminal of the counter 43 has a comparator 5
The packet output pulse output by 3 is input. The counter 43 increments the count value by 1 each time a pulse is input from the packet detector 42, and decrements the count value by 1 each time a pulse is input from the comparator 53.

Counter 4 of timing signal generating circuit 46
7 counts the clock output by the oscillator (OSC) 50 and outputs the count value to the comparator 48.
The comparator 48 compares the count value of the counter 47 with the output of the sampling time generator 49, and when both are equal, outputs an enable signal to the comparator 44. The counter 47 is adapted to be reset based on this enable signal.

The comparator 44 compares the count value of the counter 43 with the reference level of the reference level generator 45, and outputs the comparison result to the conversion circuit 51.

The conversion circuit 51 calculates the output rate OR from the output of the comparator 44 and sets the calculation result in the output rate setting circuit 52. Counter 54
Counts the clock output from the oscillator 50 and outputs the count value to the comparator 53. The comparator 53 compares the output of the output rate setting circuit 52 and the count value of the counter 54, and when both are equal, outputs a packet output pulse to the subtraction input terminal of the counter 43 and outputs the output rate control circuit 55. Is output to.

When the packet output pulse is input, the output rate control circuit 55 controls the buffer memory 41A so that the buffer memory 41A outputs one packet of data. The counter 54 is reset based on the packet output pulse output from the comparator 53.

Next, the operation of the embodiment shown in FIG. 4 will be described with reference to FIG.
6 will be described with reference to the flowchart of FIG.

Data in packet units input from the network 3 is stored in the buffer memory 41A, delayed by a predetermined time (interval delay time T _A ), read from the buffer memory 41A, and then buffer memory 4A.
Stored in 1B. Then, after being delayed by the additional delay time T _B by the buffer memory 41B, it is read from the buffer memory 41B and supplied to the system decoding unit 13 and the time stamp extraction circuit 11.

The section delay time T _A and the additional delay time T _B in the buffer memories 41A and 41B, and the output rate (readout rate O in the buffer memory 41A).
R) is controlled based on the interval data transmitted through the network 3 together with the packetized data as follows.

That is, the interval detection circuit 61 detects the interval data transmitted through the network 3 and outputs the detection signal to the parameter setting circuit 62. The parameter setting circuit 62 detects this interval data and executes the processing shown in the flowchart of FIG.

First, in step S1, when the parameter setting circuit 62 receives the interval data, the process proceeds to step S2, and the section delay time T _A is calculated according to the following calculation formula. T _A = (INT [d / T] +0.5) × T (1) Here, INT [] represents an integer (decimal point is cut off) of the operation value in [], and d is a constant and corresponds to a time interval for sampling the number of packets stored in the buffer memory 41A. Furthermore, T
Is the packet interval time (arrival interval time) detected from the interval data.

The parameter setting circuit 62 outputs the delay time to the delay time control circuit 63 after calculating the section delay time T _A according to the above equation. Delay time control circuit 63
Controls the buffer memory 41A so that the delay time from the input of one packet of data to the buffer memory 41A to the output of the buffer memory 41A becomes the section delay time T _A.

Next, in step S3, the additional delay time T _B in the buffer memory 41B is calculated by the following equation. T _B = T _V −T _A (2) Here, T _V is preset as the total delay time of the section delay time T _A in the buffer memory 41A and the additional delay time T _B in the buffer memory 41B. Delay time (average delay time), which is a constant defined by the following equation. T _V = d + T _MAX / 2 (3) T _MAX is the maximum value of the interval T.

Then, the additional delay time T _B is output to the delay time control circuit 63. The delay time control circuit 63 controls the buffer memory 41B so that the time until the data is read after being input to the buffer memory 41B is the additional delay time T _B. That is, the total delay time is controlled to be the average delay time T _V by the section delay time T _A and the additional delay time T _B of the buffer memories 41A and 41B.

Further, the parameter setting circuit 62 controls the sampling time S in the sampling time generator 49.
T is calculated by the following equation. ST = T _A + d (4)

When calculating the sampling time ST, the parameter setting circuit 62 outputs the calculated value to the sampling time generator 49 to set it.

Further, the parameter setting circuit 62 calculates the output rate (reading rate) OR in the buffer memory 41A by the following equation. OR = 1 / T (5)

The maximum value MAX of this output rate OR
The values of R, the minimum value MINR, and the change width Δ are calculated corresponding to the arrival interval time T.

The output rate O thus obtained
R, maximum value MAXR of output rate OR, minimum value MIN
The R and the change width Δ are supplied to the conversion circuit 51, respectively. The conversion circuit 51 is configured to obtain a predetermined output rate OR from the output of the comparator 44 according to the parameters set in this way and output it to the output rate setting circuit 52. The details of the processing will be described later.

After the processing in step S3 is completed as described above, the parameter setting circuit 62 receives the interval data (interval time T) newly output from the interval detection circuit 61 in step S4. In step S5, it is determined whether or not the newly detected interval time T has changed to a value different from the immediately preceding interval time T. When it is determined that the new interval time T is equal to the immediately preceding interval time T, the process proceeds to step S6, and the sampling time ST is calculated according to the following equation. ST = d (6)

Then, the sampling time ST thus set is output to the sampling time generator 49 and set. As a result, the comparator 48, whenever the value of the counter 47 becomes a constant value (value corresponding to d),
An enable signal will be output to the comparator 44.

The output rate OR, the section delay time T _A , the additional delay time T _B , the maximum value MAXR, the minimum value MINR, and the change width Δ are not changed and the previous values are continuously used as they are.

After the process of step S6, the process returns to step S4, and the subsequent processes are repeatedly executed.

On the other hand, in step S5, the interval time T
However, when it is determined that the value has changed to a value different from the immediately preceding interval time T, the process proceeds to step S7. The process of step S7 basically includes steps S2 and S3.
The process is the same as the process described in. That is, the section delay time T _A and the output rate OR are calculated according to the following equations, as in steps S2 and S3, respectively. T _A = (INT [d / T] +0.5) × T (7) OR = 1 / T (8)

The maximum value MAXR, the minimum value MINR,
The change width Δ is also calculated corresponding to the new interval time T. However, the additional delay time T _B is calculated according to the following equation. T _B = T _AN −T _AO (9) Here, T _AN is the newly calculated section delay time T _A , and T _AO is the section delay time T _{A up} to that point.

The sampling time ST is calculated according to the following equation, as in the case of step S6. ST = d (10)

After the process of step S7, the process returns to step S4, and the subsequent processes are repeatedly executed.

As described above, the buffer memory 41A
And 41B, the section delay time T _A and the additional delay time T _B are appropriately controlled by the delay time control circuit 63 corresponding to the interval time T, and the sampling time ST of the sampling time generator 49 and the conversion circuit 51 The process of changing the output rate OR, the maximum value MAXR, the minimum value MINR, and the change width Δ to predetermined values corresponding to the interval time T is repeatedly executed.

Here, the section delay time T _A and the additional delay time T _B will be further described by taking specific numerical values as examples. Now, it is assumed that data of 10 Mbps arrives at the buffer memory 41A at intervals of 3 seconds, or data of 3 Mbps arrives at intervals of 10 seconds. In addition, the packet detector 42 detects an interval d (however, it is detected that one packet of data is input to the buffer memory 41A.
The time conversion value of the count value of the counter 47) is 34 seconds. In this case, the count value BL (the number of packets stored in the buffer memory 41A) by the counter 43 is expressed by the following equation. BL = INT [d / T] (11)

Since the count value BL of the counter 43 is an integer, when 10 Mbps data is input, BL
= 11, and when 3 Mbps data is input,
BL = 3. Therefore, the section delay time T _A in the buffer memory 41A is 34.5 seconds (=
(INT [34/3] +0.5) × 3).

The buffer memory 41B in the subsequent stage of the buffer memory 41A has a section delay time T of the buffer memory 41A.
_This is for absorbing the fluctuation of _A and keeping the average delay time T _V as a whole constant, and it is only necessary to be able to adjust 1/2 of the maximum value of the interval of arriving data. In the present case, this maximum value is 10 seconds (interval is 10 seconds or 3 seconds), and therefore, adjustment of 5 seconds (= 10/2) is sufficient, and the average delay time T _V Is 39 from the equation (3).
Seconds (= 34 + 5). Therefore, the additional delay time T
_B is 4.5 seconds (= 39-34.5).

On the other hand, when 3 Mbps data is input, the section delay time T _A is 35 seconds (= (INT
[34/10] +0.5) × 10), and the additional delay time T _B becomes 4 seconds (= 39−35).

In this way, the section delay time T _A of the buffer memory 41A is controlled according to the number (integer) of packets stored in the buffer memory 41A,
Actually, the buffer memory 41A stores the detected number (integer) or more of data. Since this actual data is delayed by the delay time defined by an integer, the actual data delay time in the buffer memory 41A has a value different from the section delay time T _A. Therefore, the buffer memory 41B in the subsequent stage further delays by the additional delay time T _B to calculate the total delay time as the average delay time T _V.
Is a constant value.

On the other hand, in parallel with the processing for setting these parameters to the predetermined values as described above, the comparators 44, 48, 53, etc. perform the processing shown in FIG. Run.

When the packet detector 42 detects that one packet of data has been stored in the buffer memory 41A, the counter 43 counts up the detection pulse output from the packet detector 42. Further, when the comparator 53 outputs a packet output pulse to the output rate control circuit 55 and commands reading (output) of data for one packet stored in the buffer memory 41A, the packet output by the comparator 53. Count down the output pulse. As a result, the counter 43 holds a value corresponding to the number of packets stored in the buffer memory 41A.

On the other hand, the comparator 48 compares the count value of the counter 47 with the sampling time ST set in the sampling time generator 49, and when the count value becomes equal to the sampling time ST, the comparator 44.
The enable signal is output to. The counter 47 is reset when the comparator 48 outputs the enable signal, and starts the counting operation of the clock output by the oscillator 50 again. As a result of repeating such operations, the comparator 48 of the timing signal generating circuit 46 generates the enable signal at a constant cycle (at a cycle corresponding to the sampling time ST set in the sampling time generator 49). become.

In step S21, the comparator 44
At the timing when the comparator 48 of the timing signal generation circuit 46 outputs the enable signal, the count value (BL) of the counter 43 is compared with the reference level (REF) set in the reference level generator 45.

When the comparator 44 determines that the count value BL of the counter 43 is equal to the reference level REF of the reference level generator 45, the process proceeds to step S22, and the conversion circuit 51 sets the output rate setting circuit 52. The output rate OR to be performed remains the current output rate OR. After that, the process returns to step S21, and the subsequent processes are repeatedly executed.

On the other hand, in step S21,
The count value BL of the counter 43 and the reference level generator 4
When it is determined that the reference levels REF of 5 are not equal, the process proceeds to step S23, and it is determined whether the count value BL is larger than the reference level REF.

When it is determined that the count value BL is higher than the reference level REF, the process proceeds to step S24, and the output rate OR set in the output rate setting circuit 52 is changed by the change width Δ set at that time. It is determined whether the added value (OR + Δ) is smaller than the maximum value MAXR of the output rate set at that time. When OR + Δ is smaller than MAXR,
In step S25, the value (OR + Δ) obtained by adding the change width Δ to the current output rate OR is used as the new output rate O.
Set as R. On the other hand, when it is determined in step S24 that OR + Δ is equal to or greater than MAXR, the process proceeds to step S26, and the maximum value MAXR is set as the output rate OR.

That is, the conversion circuit 51 determines that the value output from the comparator 44 is positive (the count value BL of the counter 43).
Is larger than the reference level REF), the output rate setting circuit 5 increases the output rate by an amount corresponding to the change width Δ.
Output to 2. As a result, in the output rate setting circuit 52, the output rate OR that has been set until then is changed to a value increased by the change width Δ.

On the other hand, when the value of OR + Δ is equal to or larger than MAXR, the conversion circuit 5
1 causes the output rate setting circuit 52 to set the maximum value MAXR as the output rate.

On the other hand, when it is determined in step S23 that the count value BL is equal to or smaller than the reference level REF, the process proceeds to step S27,
Value obtained by subtracting the change width Δ from the output rate OR (OR-Δ)
Is larger than the minimum value MINR of the output rate. When it is determined that OR-Δ is larger than MINR, the process proceeds to step S28, and the value OR-Δ obtained by subtracting the change width Δ from the current output rate OR is set as the new output rate OR.

On the other hand, in step S27,
When it is determined that OR-Δ is equal to or smaller than MINR, the process proceeds to step S29, and the minimum value MINR is set as a new output rate OR.

That is, when the count value BL is equal to or smaller than the reference level REF, the conversion circuit 51 determines whether the value obtained by subtracting the change width Δ from the current output rate OR is larger than MINR. judge. And
When OR-Δ is larger than MINR, the output rate setting circuit 52 sets a value obtained by subtracting the change width Δ from the current output rate OR as a new output rate OR. On the other hand, when OR-Δ is equal to or smaller than MINR, the output rate setting circuit 52 is caused to set the minimum value MINR as a new output rate OR.

The comparator 53 outputs the count value of the counter 54 counting the clock output from the oscillator 50,
The output rate OR set in the output rate setting circuit 52 is compared, and when both are equal, a packet output pulse is generated. When the packet output pulse is input, the output rate control circuit 55 controls the buffer memory 41A to read one packet of data and output it to the buffer memory 41B.

In this way, the data read (output) operation is performed from the buffer memory 41A in accordance with the output rate OR set in the output rate setting circuit 52.

As described above, the buffer memory 41A
The larger the number of packets stored in, the output rate OR is adjusted to a larger value. On the other hand, when the number of packets decreases, the output rate OR is adjusted to a small value.

Therefore, even if the packet arrival interval changes and delay fluctuations occur on the network 3, the adjustment circuit 31 can absorb them. As a result, the structure of the PLL circuit 12 can be simplified, and the demand for the network 3 to minimize delay fluctuations can be alleviated.

In the above embodiment, the data representing the packet interval is transmitted as the interval data, but the packet interval corresponds to the data rate (bit rate) at the time of transmitting the packet. Therefore, as the interval data, it is possible to transmit the data representing the data rate. In this case, the interval detector 61 of FIG. 4 is caused to detect interval data representing the data rate (hereinafter, appropriately referred to as data rate data), and to calculate the packet interval from the data rate recognized as a result. Just do it. That is, for example, when the interval at which the packet is transmitted at the data rate of x1 [Mbps] is y1 [seconds], the interval detector 61 receives the equation when x2 [Mbps] is received as the data rate data. The packet interval can be obtained according to y1 × x1 / x2.

Further, in the above-described embodiment, as shown in FIG. 2, the interval data is transmitted before each packet is transmitted. However, in addition to this, the interval data (or data rate data) is not transmitted. It is also possible to transmit only when it is different from the interval data (data rate data) transmitted immediately before.

That is, the encoding by the encoder 1 is performed at a fixed rate when it is considered by dividing it into predetermined intervals (time). Then, the data rate (bit rate) of each section is changed by the generated code amount in the encoder 1. In other words, the data rate is increased in the section where the generated code amount in the encoder 1 is large (therefore,
Since the number of packets to be transmitted increases, the packet interval is narrowed. In addition, the data rate is lowered in the section where the generated code amount is small (therefore, the number of packets to be transmitted is decreased, so the packet interval is reduced). Is widened) (the data rate is changed in each predetermined section in this manner, so that the variable rate is set as a whole).

Here, FIG. 7 shows how the encoding by the encoder 1 is performed at a fixed rate for each predetermined section. In the figure (a), 3M in the first section.
It shows that the encoding is performed at 2 bps, 2 Mbps in the next section, and 4 Mbps in the next section. As shown in (b) of the figure, in the section of high data rate, for example, 4 Mbps, the packet interval becomes narrow, and the data rate is low, for example, 2 M.
In the section of bps, the packet interval becomes wide.

In this case, since the data rate of each section is fixed, the data rate at the time of transmitting the data of that section is set only before the data of each section is transmitted, as shown in FIG. A packet in which the corresponding data rate data is placed (data rate value packet) (the shaded portion in the figure) is transmitted, and then the packetized data is created at intervals corresponding to the data rate. Can be transmitted.

When the transmission is performed in this way, the parameter setting circuit 62 is caused to perform the processing of steps S1 to S3 shown in the flowchart of FIG.
By performing the process of step 7 and performing the process of step S6 when the data rate data is not received, the decoding can be performed as described above.

In this case, before transmitting the packet,
The transmission efficiency can be improved as compared with the case of transmitting the data rate data (interval data).

The fixed rate section can be set, for example, according to the type of data. That is,
When transmitting both a video signal and an audio signal as in the above-described embodiment, the video signal is transmitted (encoded) at a fixed rate in units of 15 frames, and the audio signal is transmitted for 1 second, for example. It is possible to transmit (encode) as a fixed rate in units.

FIG. 8 shows an example of the configuration of an encoder system that outputs a packet as described with reference to FIG. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted as appropriate.

In the section bit rate value setting circuit 91, the encoder 1 extracts the data coding rate (data rate) set by the encoder 1 for each predetermined section as described above. It is output to the calculation setting circuit 93. In the interval calculation setting circuit 93,
When the data rate is received from the section bit rate value setting circuit 91, the packet transmission interval (packet interval) is calculated based on the data rate and output to the packet output circuit 92. When the packet output circuit 92 receives the packet intervals from the interval calculation setting circuit 93, it outputs the packets output by the packetizing circuit 82 at the intervals.
Output to the network 3 (the packet output speed is adjusted according to the interval).

The packetizing circuit 82, before converting the data output from the encoder 1 for each predetermined section into packets, sets the data rate data in that section as data rate data.
The data rate supplied from the interval bit rate value setting circuit 91 is converted into a packet and output to the packet output circuit 92. Therefore, the packet output circuit 92
7B, the data rate data (data rate value packet) is first transmitted for each section, and then the data (data rate value packet) is transmitted at intervals corresponding to the data rate. Then, a packet (data packet) of MPEG encoded data) is transmitted.

Also in this case, the data rate data can be included in the data packet for transmission in the same manner as the time stamp and the like.

Next, for example, it may be desired that the data output from the packet output circuit 92 be once recorded and stored in a recording medium and then transmitted instead of being transmitted in real time (directly). In this case, if the data output from the packet output circuit 92 is recorded as it is, there is an interval between a certain packet and the next packet, and therefore an extra recording capacity is required for the interval. .

Therefore, FIG. 9 shows the configuration of an embodiment of the encoded data recording apparatus of the present invention. Buffer 1
Reference numeral 11 stores the data output from the packet output circuit 92. The recording circuit 112 reads the data stored in the buffer 111 and records the data on a recording medium 101 such as a hard disk (magnetic disk), a magneto-optical disk, or a magnetic tape. Note that the buffer 111 is capable of storing and reading data at the same time.

In the encoded data recording apparatus configured as described above, the data output from the packet output circuit 92 is supplied to and stored in the buffer 111. The recording circuit 112 reads the data from the buffer 111 by skipping the portion of the interval between the packets and reading the data from the recording medium 101.
To record. As a result, on the recording medium 101, as shown in FIG. 10, the encoded data encoded at the variable bit rate is packetized with a time stamp and is recorded together with the data rate data without any interval. To be done.

FIG. 10A shows the recording format when the bit rate data is output from the packet output circuit 92 as a packet different from the data packet (in a format different from the data packet). 10B shows the recording format in the case where the bit rate data (bit rate value) is included in the data packet and is output from the packet output circuit 92.

In this case, the data can be recorded efficiently.

Next, FIG. 11 shows the configuration of an embodiment of an encoded data transmission apparatus for transmitting the data recorded on the recording medium 101 as described above via the network 3.

Under the control of the interval calculation setting circuit 105, the read control circuit 102 reads data from the recording medium 101 and supplies it to the buffer 103. The buffer 103 is a FIFO (First In First Out).
t) It is composed of a memory or the like, and is adapted to temporarily store the data from the read control circuit 102. The bit rate value detector 104 sequentially reads the data stored in the buffer 103 and detects the bit rate data from the data. Further, the bit rate value detector 104 outputs the detected bit rate data to the interval calculation setting circuit 105, and also outputs the data remaining as a result of detecting the bit rate data, that is, the data packet, to the interval calculation setting circuit 105. It is designed to do. The interval calculation setting circuit 105 is similar to the interval calculation setting circuit 93 of FIG.
The data packet transmission interval (packet interval) is calculated on the basis of the bit rate data from (1) and is output to the transmitter 106 together with the bit rate data (bit rate value packet) and the data packet. The transmitter 106 transmits the bit rate data from the interval calculation setting circuit 105, and then transmits the data packets at the intervals calculated by the interval calculation setting circuit 105.

In the encoded data transmission device configured as described above, a read request of data is issued by the read control circuit 1 by operating an operation unit (not shown).
When it is received by 02, the read circuit 102 reads the data from the recording medium 101 and supplies the data to the buffer 103 for storage. When the data is stored in the buffer 103, the bit rate value detector 104 sequentially reads the data, detects bit rate data (bit rate value packet) from the data, and remains as a result of the detection of the bit rate data. The data packet is output to the interval calculation setting circuit 105.

In the interval calculation setting circuit 105, the output of the bit rate value detector 104 is output to the transmitter 106 as it is, and further, the interval for transmitting the data packet (packet interval) based on the bit rate data. Is calculated and output to the read control circuit 102 and the transmitter 106.

Here, the read control circuit 102 controls the reading of data from the recording medium 101 based on the packet interval supplied from the interval calculation setting circuit 105. That is, if the packet interval is wide, it takes time to transmit the data, so that the reading rate from the recording medium 101 is low, and if the packet interval is narrow, the data transmission does not take time. Therefore, the reading rate from the recording medium 101 is increased.

In the transmitter 106, the bit rate data is transmitted first, and then the data packets are transmitted at the intervals calculated by the interval calculation setting circuit 105.

Therefore, since data is output from this encoded data transmission device in the same manner as when data is output from the packet output circuit 92, the adjustment circuit 31 shown in FIG. It is possible to absorb changes in packet arrival intervals and delay fluctuations on the network 3.

[0137]

According to the encoding system of the first aspect and the encoding method of the sixth aspect, the data is packetized and transmitted, and the packet interval is also transmitted together with the data. It is possible to realize an encoding system or an encoding method capable of accurately decoding data even if data is transmitted at a rate and delay fluctuations occur on the network.

According to the decoding system of the second aspect and the decoding method of the seventh aspect, the delay amount of the packet is appropriately controlled according to the interval data of the transmitted packet. Even in the case of a variable bit rate, the data can be read accurately regardless of the delay fluctuation of the data on the network.

According to the encoding system of the eighth aspect and the encoding method of the ninth aspect, the data is encoded at a variable bit rate, the encoded data is time-stamped and packetized, The data rate for transmitting the packet is set for each predetermined section, and the packet transmission interval is calculated in accordance with the data rate. Then, the packetized data is transmitted at the calculated transmission intervals together with the data rate data corresponding to the data rate. Therefore,
Even if delay fluctuations occur on the network, the data can be accurately decoded.

According to the encoded data recording apparatus of the tenth aspect and the encoded data recording method of the eleventh aspect, it is assumed that encoded data encoded at a variable bit rate is packetized by adding a time stamp. , And data rate data corresponding to the data rate at the time of transmitting the packet are stored, then read as appropriate and recorded in a recording medium. Therefore, the data can be efficiently recorded.

According to the encoded data transmission device of the twelfth aspect and the encoded data transmission method of the thirteenth aspect, encoded data encoded at a variable bit rate is packetized by adding a time stamp. The data is read from the recording medium recorded together with the data rate data corresponding to the data rate at the time of transmitting the packet, and the data rate data is detected from the data. Then, the packet transmission interval is calculated corresponding to the data rate data, and the packet is transmitted at the calculated transmission interval together with the data rate data. Therefore, even if delay fluctuations occur on the network, the data can be accurately decoded.

According to the recording medium of the thirteenth aspect, the encoded data encoded at the variable bit rate is packetized by adding a time stamp,
Since the data is recorded together with the data rate data corresponding to the data rate at the time of transmitting the packet, for example, when the data read from this recording medium is transmitted through the network, delay fluctuation occurs on the network. Even in this case, the data can be accurately decoded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a system encoder of the present invention.

FIG. 2 is a timing chart for explaining the relationship between packets output from a synthesizing circuit 84 in FIG. 1 and interval data.

FIG. 3 is a block diagram showing a configuration example of a system decoder of the present invention.

4 is a block diagram showing a configuration example of an adjustment circuit 31 in FIG.

5 is a flowchart illustrating the operation of the embodiment of FIG.

6 is a flowchart illustrating another operation of the embodiment of FIG.

[Fig. 7] Fig. 7 is a diagram illustrating a state in which encoding by the encoder 1 is performed at a fixed rate for each predetermined section.

FIG. 8 is a block diagram showing another configuration example of the system encoder of the present invention.

FIG. 9 is a block diagram showing a configuration example of an encoded data recording device of the present invention.

10 is a diagram showing a recording format of a recording medium 101. FIG.

FIG. 11 is a block diagram showing a configuration example of an encoded data transmission device of the present invention.

FIG. 12 is a diagram illustrating a configuration of a transmission path.

FIG. 13 is a block diagram showing a configuration example of a conventional system decoder.

14 is a block diagram showing a configuration example of a PLL circuit 12 of FIG.

[Explanation of symbols]

 1 Encoder 2 System Encoder 3 Network 4 System Decoder 5 Decoder 11 Time Stamp Extraction Circuit 12 PLL Circuit 13 System Decode Section 21 Subtractor 22 Low Pass Filter 23 DA Converter / VCO 24 Counter 31 Adjustment Circuit 41A, 41B Buffer Memory 42 Packet Detector 43 Counter 44 Comparator 45 Reference Level Generator 46 Timing Signal Generation Circuit 47 Counter 48 Comparator 49 Sampling Time Generator 50 Oscillator 51 Conversion Circuit 52 Output Rate Setting Circuit 53 Comparator 54 Counter 55 Output Rate Control Circuit 61 Interval Detection Circuit 62 Parameter Setting circuit 63 Delay time control circuit 81 Time stamp generating circuit 82 Packetizing circuit 83 Buffer memory 84 Combining circuit 85 Interval detector 86 Oscillator 87 Counter 91 Sectional bit rate value setting circuit 92 Packet output circuit 93 Interval calculation setting circuit 101 Recording medium 102 Read control circuit 103 Buffer 104 Bit rate value detector 105 Interval calculation setting circuit 106 Transmitter 111 Buffer 112 Recording circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04Q 3/00 (54) [Title of Invention] Encoding system and encoding method, decoding system and decoding method, encoding Data recording device, encoded data recording method, encoded data transmission device, encoded data transmission method, and recording medium

Claims (14)

[Claims] 1. Encoding means for encoding data at a variable bit rate, generating means for generating a time stamp to be added to the data, and packetizing means for packetizing the encoded data by adding the time stamp. And a calculation means for calculating an interval between the packets packetized by the packetization means, a packet packetized by the packetization means, and interval data corresponding to the interval calculated by the calculation means. An encoding system comprising: a transmission means. 2. Storage means for storing variable bit rate data transmitted in units of packets, and interval data detection means for detecting interval data corresponding to the intervals of the packets transmitted together with the data, A decoding system, comprising: delay time control means for controlling a delay time until the packet is read after being stored in the storage means, corresponding to a detection result of the interval data detection means. 3. The storage means comprises a first storage means for storing a plurality of the packets, and a second storage means for storing one of the packets read from the first storage means. The delay time control means stores the delay time in the first storage means and the delay time in the second storage means such that the total time of the delay times is equal to the preset predetermined time. The second storage means is controlled, and the second storage means is controlled.
Decoding system described in. 4. A storage amount detection means for detecting the amount of packets stored in the storage means, and an output for reading out and outputting the packet from the storage means in response to a detection result of the storage amount detection means. 3. The decoding system according to claim 2, further comprising output rate control means for controlling a rate. 5. A storage amount detecting means for detecting the amount of packets stored in the storage means, and an output for reading out and outputting the packet from the storage means in response to a detection result of the storage amount detecting means. 4. The decoding system according to claim 3, further comprising output rate control means for controlling a rate. 6. The data is encoded at a variable bit rate, the encoded data is packetized by adding a time stamp, an interval between packets of the encoded data is calculated, and interval data corresponding to the interval is calculated. And an encoding method characterized by transmitting the packet together with the packet. 7. The variable bit rate data transmitted in units of packets is stored in a memory, interval data corresponding to the interval of the packet is extracted from the data, and the interval data corresponding to the extracted interval data is extracted. Controlling the output rate of reading the data stored in the memory and outputting it, extracting a time stamp from the data output from the memory, generating a system clock using the extracted time stamp, A decoding method comprising decoding the data output from the memory by using the system clock. 8. An encoding means for encoding data at a variable bit rate, a generating means for generating a time stamp to be added to the data, and a packetizing means for adding the time stamp to the encoded data to form a packet. Setting means for setting a data rate for transmitting the packet for each predetermined section; calculating means for calculating a transmission interval of the packet corresponding to the data rate; and corresponding to the data rate. An encoding system comprising: a transmission unit configured to transmit the packet at a transmission interval calculated by the calculation unit together with data rate data. 9. The data is encoded at a variable bit rate, the encoded data is packetized by adding a time stamp, and a data rate for transmitting the packet is set for each predetermined section. An encoding method, wherein a transmission interval of the packet is calculated in accordance with a data rate, and the packet is transmitted at the calculated transmission interval together with data rate data corresponding to the data rate. 10. The input encoded data encoded at a variable bit rate is added with a time stamp to form a packet, and the data rate data corresponding to the data rate at the time of transmitting the packet is stored. An encoded data recording apparatus, comprising: a storage unit for storing the data, and a recording unit for reading the data stored in the storage unit and recording the data on a recording medium. 11. Stored is input encoded data encoded at a variable bit rate into a packet with a time stamp and data rate data corresponding to the data rate at the time of transmitting the packet. Then, the encoded data recording method is characterized in that the stored data is read out and recorded in a recording medium. 12. A recording medium in which encoded data encoded at a variable bit rate is packetized by adding a time stamp and is recorded together with data rate data corresponding to the data rate at the time of transmitting the packet. Read means for reading out data, a detecting means for detecting the data rate data from the data, a calculating means for calculating a transmission interval of the packet corresponding to the data rate data, and the data rate data together An encoding data transmission device comprising: a transmission unit configured to transmit the packet at a transmission interval calculated by the calculation unit. 13. A recording medium in which encoded data encoded at a variable bit rate is packetized by adding a time stamp and is recorded together with data rate data corresponding to the data rate at the time of transmitting the packet. Data is read from the data, the data rate data is detected from the data, the transmission interval of the packet is calculated corresponding to the data rate data, and the packet is calculated together with the data rate data. An encoded data transmission method characterized by transmitting at intervals. 14. A packet obtained by adding a time stamp to encoded data encoded at a variable bit rate and recorded together with the data rate data corresponding to the data rate at the time of transmitting the packet. Characteristic recording medium.