JPH0818796A - Encoding device for binary image - Google Patents

Abstract

PURPOSE:To shorten time required for normalizing processing at the appearance of an inferior symbol and to improve encoding processing speed by executing normalizing processing based upon the number of shifts at the time of normalizing the inferior symbol separatively from normalizing processing to be executed after the appearance of the inferior symbol. CONSTITUTION:A image referring means 1 refers to plural picture elements around a noticed element to be encoded by the use of a template 2 and calculates a context expressed by the combination of binary data corresponding to picture elements in the template 2. A status output means 4 outputs status from a memory 3 correspondingly to the context calculated by the means 1 and an estimation means 5 estimates the probability of inferior symbol appearance and a superior symbol based upon the status. A calculation means 6 calculates the number of shifts from the status at the time of normalizing the inferior symbol and an arithmetic code generating means 7 executes normalizing processing by using the number of shifts at the time of normalizing the inferior symbol separatively from normalizing processing after the appearance of the inferior symbol.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary image coding device, and more particularly to a binary image coding device used in a facsimile device, a soft copy facsimile device and an image filing device which are image communication devices.

[0002]

2. Description of the Related Art Conventionally, JB has been used as a binary image coding method.
The IG method has been proposed. The JBIG method performs predictive coding with reference to pixels called model templates. There are two types of model templates, one for lowest resolution layer encoding and one for difference layer encoding.
The model template for the lowest resolution layer encoding of the JBIG method may use 3 lines as shown in FIG. 6 (a) or 2 lines as shown in FIG. 6 (b). The pixel at the position of C is the coded pixel of interest for which the symbol appearance probability is estimated from the combination of "0" or "1". Pixels around it are model templates, and the symbol appearance probability is obtained from the combination of “0” and “1” of each pixel.

As shown in FIG. 7, the JBIG method differential layer encoding model template has four phases depending on the positional relationship of pixels in two layers. Each square in A in the figure represents a pixel in a layer in which the pixel of interest for encoding is present, a circle in B in the figure represents a pixel in the resolution layer one level below, and C in the figure represents an attention in encoding. Represents a pixel.

Next, the operation of the JBIG encoder will be described with reference to the flowchart of FIG.

First, initialization processing is performed (step S
1). Then, the context CX which is a combination of the pixel value PIX to be encoded and the pixel data around it is read (step S2). Then, ENCODE processing for encoding the pixel value PIX is performed (step S
3). Then, the processes of steps S2 and S3 are repeated until the stripe of the image data ends (step S
4). The stripe is a processing unit of JBIG image data. FLUSH processing for stripping all register contents after the stripe is finished (step S5)
Then, the encoding process ends.

The register used in the above flow is A
There are two types, register and C register, A register has a bit that represents the probability width, C register has x bits that contain an unfinished code and b bits that input a completed code in 8-bit units. There is.

Next, the ENCODE processing will be described with reference to the flowchart of FIG.

The value PIX of the coded pixel of interest and the value of the dominant symbol MPS are compared to determine that the coded pixel of interest is the dominant symbol M.
It is determined whether it is PS or recessive symbol LPS (step S
6). If it is determined that the coded pixel of interest is the recessive symbol LPS, CODELPS processing is performed (step S7), and if it is determined that it is the dominant symbol MPS, CODEMPS processing is performed (step S8).

Next, a CODE for coding the recessive symbol
The LPS process will be described with reference to the flowchart of FIG.

Recessive symbol appearance probability LS from A register
Z is subtracted (step S9). Then, the value of the A register is compared with the recessive symbol appearance probability LSZ (step S10), and when the value of the A register is equal to or larger than the value of LSZ,
The value of the A register is added to the C register, and the value of the A register is set to the value of LSZ (step S11). then,
The value of SWTCH indicating the inversion of the value of MPS is compared with 1 (step S12), and if the value of SWTCH is 1, MP
The value of S is inverted (step S13). Furthermore, an NLP indicating the next status when the status ST is LPS.
RENORME updated to the value of S and normalizing at the same time
Processing is performed (step S14).

Next, the CODE for encoding the dominant symbol
The MPS process will be described with reference to the flowchart of FIG.

Recessive symbol appearance probability LS from A register
Z is subtracted (step S15). Then, the value of the A register is compared with 0x8000 (step S16), and A
Is 0x8000 or more, the CODEMPS process ends. When A is smaller than 0x8000, A and L
SZ is compared (step S17), and if A is smaller than LSZ, the value of the A register is added to the C register, and A
The value of the register is set to LSZ (step S18). Then, when the status ST is MPS, the value is updated to the value of NMPS indicating the next status, and at the same time, the RENORME process is performed (step S19).

Next, the RENORME process for normalizing will be described with reference to the flowchart of FIG.

Both the A register and the C register are shifted one bit to the left. This corresponds to doubling the value of the A register and the value of the C register. At the same time, 1 is subtracted from the variable CT indicating the count value (step S2).
0). When CT is compared with 0 (step S21) and CT is 0, BYTEOUT processing is performed (step S2).
2). Then, the value of the A register is compared with 0x8000 (step S23), and the processing from step S20 to step S22 is repeated until A becomes 0x8000 or more.

Next, the BYTEOUT process will be described with reference to the flowchart of FIG.

The value of the variable TEMP is set to a value obtained by shifting the C register to the right by 19 bits (step S24). TE
MP and 0xff are compared (step S25). T
When EMP is larger than 0xff, BUFFER is incremented by 1 and BUFFER is output. Further, the number 0x00 of the variable SC is output and SC is set to 0. And
The value of BUFFER is set to the value obtained by ANDing TEMP and 0xff (step S26). On the other hand, TEMP is 0
If it is less than or equal to xff, TEMP is compared with 0xff (step S27). If TEMP = 0xff, SC
Is incremented by 1 (step S28). TEMP is 0xf
If smaller than f, BUFFER is output and SC times 0
After x00 is output, SC is set to 0. And B
The value of UFFER is set to the value of TEMP (step S2
9). After the processing classified according to the value of TEMP ends, the value of the C register is set to the value obtained by ANDing the C register and 0x7ffff, and CT is set to 8 (step S30).

Next, the initialization process will be described with reference to the flowchart of FIG.

Determine whether the current stripe is the first stripe in the hierarchy or has been reset (step S
31), if any of the conditions is met, ST corresponding to all CXs is set to 0, and the value of MPS is set to 0 (step S32). If neither condition is met, ST and MPS are set to the last value of the previous stripe (step S33). After performing step S32 or step S33, SC is set to 0, the value of the A register is set to 0x10000, the value of the C register is set to 0, and the value of CT is set to 11 (step S34).

Next, the FLUSH process will be described with reference to the flowchart of FIG.

CLEARBITS processing, FINALWR
ITES processing is performed and stripe encoded data SCD
The first byte of the SCD, and if necessary, all the last 0x00 bytes of the SCD (step S
35).

Next, the CLEARBITS process will be described with reference to the flowchart of FIG. The value of TEMP is A
The value obtained by subtracting 1 from the register and adding the value of the C register and the AND of 0xffff0000 are set (step S36). Then, TEMP is compared with the C register (step S37). When TEMP is smaller than the C register, the value of the C register is TEMP and 0x.
The sum is set to 8000 (step S38). Also, T
If EMP is greater than or equal to C register, the value of C register is TE
The value of MP is set (step S39).

Next, the FINALWRITES process is shown in FIG.
A description will be given according to the flowchart of FIG.

The value of the C register is shifted to the left by the value of CT (step S40). C register and 0x7fff
fff is compared (step S41), and if the value of the C register is larger than 0x7ffffff, BUFFER
1 is output, and 0x00 SC times is output (step S42). Value of C register is 0x7ff
When it is less than or equal to ffff, BUFFER is output and 0xff is output SC times (step S43). Step S
42 or step S43, the C register is set to 19
An AND of 0xff that is shifted to the right by the bit is output, and 0 when the C register is shifted to the right by 11 bits.
An AND with xff is output (step S44).

In the probability estimation table, as shown in FIGS. 18a and 18b, the next ST values NLPS and MPS appear when the recessive symbol appearance probabilities LSZ and LPS corresponding to the respective status ST values appear. It shows the value STMP of the next ST and the value of SWTCH indicating whether or not the MPS is inverted. The JBIG method and the QM coder are described in "International Standards for Multimedia Coding" P48 to P82 published by Maruzen Co., Ltd.

[0025]

Since the conventional encoding technique is configured as described above, the normalization process after the appearance of the recessive symbol takes a lot of shift time and therefore takes a long processing time.
There is a problem that the encoding process cannot be speeded up.

The present invention has been made in order to solve the above problems, and provides a binary image coding apparatus capable of shortening the time of the normalization process when a recessive symbol appears and speeding up the coding process. The purpose is to provide.

[0027]

According to the present invention, the above-mentioned object is a binary image coding apparatus for losslessly coding binary image data, wherein a plurality of pixels around a target pixel to be coded are encoded. Corresponding to an image reference unit for calculating a context represented by a combination of binarized data corresponding to each of a plurality of pixels in the template with reference to a predetermined template, and a context calculated by the image reference unit Status output means for outputting the status stored in the memory address, estimation means for estimating and outputting the recessive symbol appearance probability and dominant symbol from the status, and calculation for calculating the recessive symbol normalization shift number from the status Means and a recessive symbol when outputting a code sequence corresponding to binary image data using the recessive symbol appearance probability. The binarized image coding according to claim 1, further comprising: an arithmetic code generation unit that divides the normalization process after the appearance of the symbol from the normalization process after the appearance of the dominant symbol and uses the recessive symbol normalization shift number. Achieved by the device.

The estimating means may include a probability estimation table in which the recessive symbol appearance probability and dominant symbol estimation data corresponding to the status are described.

Further, the recessive symbol normalization shift number corresponding to the status is described in the probability estimation table, and the calculating means may use the probability estimation table.

[0030]

In the binary image coding apparatus according to the present invention, a plurality of pixels around the pixel of interest to be coded by the image reference means are referred to by using a template and correspond to each of the plurality of pixels in the template. The context represented by a combination of binarized data is calculated, the status output means outputs the status stored in the memory address corresponding to the context calculated by the image reference means, and the estimation means outputs the recessive symbol from the status. Probability and dominant symbols are estimated and output,
The calculating unit calculates the recessive symbol normalization shift number from the status, and when the arithmetic code generating unit outputs the code sequence corresponding to the binary image data using the recessive symbol appearance probability, normalization after the appearance of the recessive symbol is performed. The process is separated from the normalization process after the appearance of the dominant symbol, and the normalization process using the recessive symbol normalization shift number is performed. As a result, the time required for the normalization process when the recessive symbol appears can be shortened.

In the binarized image encoding device according to the second aspect of the present invention, the estimating means includes the probability estimation table in which the recessive symbol appearance probability and the dominant symbol estimation data corresponding to the status are described. The probability of symbol appearance and the dominant symbol can be easily estimated.

In the binarized image encoding device of the third aspect, the recessive symbol normalization shift number corresponding to the status is described in the probability estimation table, and the inferiority is inferior by the calculation means using the probability estimation table. The number of shifts at the time of symbol normalization can be easily obtained.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a binary image coding apparatus of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the binary image coding apparatus according to the present embodiment refers to a plurality of pixels around a pixel of interest to be coded in the binary image data by using the template 2 and refers to the inside of the template 2. An image reference unit 1 for calculating a context 100 represented by a combination of bits of a plurality of pixels, and a status 1 stored in a memory address 3 corresponding to the context 100 calculated by the image reference unit 1.
The status output means 4 for outputting 01, the estimation means 5 for estimating and outputting the recessive symbol appearance probability and the dominant symbol from the status 101 output from the status output means 4, and the recessive symbol normalization shift number from the status 101 When outputting the code sequence corresponding to the binary image data using the calculating means 6 for calculating and the recessive symbol appearance probability output from the estimating means 5, the normalization processing after the appearance of the recessive symbol is separated from the normal processing. And an arithmetic code generation means 7 for performing a normalization process using the recessive symbol normalization shift number output from the calculation means 6. The estimating means 5 has a probability estimation table.

Next, the operation of this embodiment will be described.

In this embodiment, the operation of the encoder and the EN
The CODE processing is the same as that of the conventional example described above, and therefore its explanation is omitted.

First, the CODELPS process will be described with reference to the flowchart of FIG.

First, the flag R is set to 0 (step S).
51). The recessive symbol appearance probability LSZ is subtracted from the A register (step S52). Then, the value of the A register and the recessive symbol appearance probability LSZ are compared (step S53), and if the value of the A register is LSZ or more, the value of the A register is added to the C register and the value of the A register is L.
SZ is set (step S54), and the flag R is set to 1 (step S55). Then, the value of SWTCH is compared with 1 (step S56), and if SWTCH is not 1, the value of MPS is inverted (step S57). Then, the value of the flag R is compared with 1 (step S58),
When the flag R is 1, the status ST is updated to the status when LPS appears, and at the same time LSZRE is set.
NORME processing is performed (step S59). If the flag R is 0, the status ST is updated to the status when the LPS appears, and at the same time RENORME
Processing is performed (step S60).

Next, the CODEMPS process will be described with reference to the flowchart of FIG.

The flag R is set to 0 (step S61),
The recessive symbol appearance probability LSZ is subtracted from the A register (step S62). The value of the A register is compared with 0x8000 (step S63), and the value of the A register is 0x.
If it is 8000 or more, the CODEMPS process ends.
When the value of register A is smaller than 0x8000,
A and LSZ are compared (step S64), and A is LS
If it is smaller than Z, the value of the A register is added to the C register, and the value of the A register is set to LSZ (step S6).
5), the flag R is set to 1 (step S66). Next, the flag R is compared with 1 (step S67), and when the flag R is not 1, the status appears in the symbol MP.
When the status is updated to S, RENOR
ME processing is performed (step S68). Flag R is 1
In the case of, the status is updated to the status when the appearance symbol is MPS, and at the same time, the LSZRENORME process is performed (step S69).

Next, the LSZRENORME process will be described with reference to the flowchart of FIG. First CT and SHF
T is compared (step S70). CT is SHF
If T or less, the A register is shifted CT bits to the left, the C register is shifted CT bits to the left, and SHF is set.
CT is subtracted from T, and CT is set to 0 (step S7
After 1), BYTEOUT processing is performed (step S).
72). Then, SHFT is subtracted from CT (step S73), the A register is shifted to the SHFT bit left and the C register is shifted to the SHFT bit left.

As shown in the probability estimation table of FIG. 5, the shift amount is smaller than that in the conventional example, and the time required for the normalization process can be shortened.

[0043]

According to the binary image coding apparatus of the first aspect, the normalization process after the appearance of the recessive symbol is separated from the normalization process after the appearance of the dominant symbol, and the recessive symbol normalization shift number is used. Since the normalization processing is performed, the time required for the normalization processing when the recessive symbol appears can be shortened and the encoding processing speed can be improved.

In the binarized image coding device according to the second aspect, the recessive symbol appearance probability and the dominant symbol can be easily estimated.

In the binarized image coding device according to the third aspect, the number of shifts at the time of recessive symbol normalization can be easily obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a binary image encoding device according to the present invention.

FIG. 2 is a flowchart showing a CODELPS process of this embodiment.

FIG. 3 is a flowchart showing a CODEMPS process of the present embodiment.

FIG. 4 is a flowchart showing LSZRENORME processing of the present embodiment.

FIG. 5a is a diagram showing a part of a probability estimation table according to the present embodiment.

FIG. 5b is a diagram showing another part of the probability estimation table according to the present embodiment.

FIG. 6 is a diagram showing a lowest resolution layer model template.

FIG. 7 is a diagram showing a difference layer model template.

FIG. 8 is a flowchart showing the operation of a JBIG encoder.

FIG. 9 is a flowchart showing ENCODE processing.

FIG. 10 is a flowchart showing a conventional CODELPS process.

FIG. 11 is a flowchart showing a conventional CODEMPS process.

FIG. 12 is a flowchart showing RENORME processing.

FIG. 13 is a flowchart showing BYTEOUT processing.

FIG. 14 is a flowchart showing INITENC processing.

FIG. 15 is a flowchart showing FLUSH processing.

FIG. 16 is a flowchart showing CLEARBITS processing.

FIG. 17 is a flowchart showing FINALWRITES processing.

FIG. 18a is a diagram showing a part of a conventional probability table.

FIG. 18b is a diagram showing another part of the conventional probability table.

[Explanation of symbols]

 1 Image reference means 2 Template 3 Status output means 4 Memory 5 Estimating means 6 Calculating means 7 Arithmetic code generating means

Claims (3)

[Claims] 1. A binary image coding apparatus for losslessly coding binary image data, wherein a plurality of pixels around a pixel of interest to be coded are referenced using a predetermined template, and a plurality of pixels in the template are Image reference means for calculating the context represented by a combination of binary data corresponding to each, and status output means for outputting the status stored in the memory address corresponding to the context calculated by the image reference means, , Estimating means for estimating and outputting a recessive symbol appearance probability and a dominant symbol from the status, calculating means for calculating a recessive symbol normalization shift number from the status, and binary image data using the recessive symbol appearance probability When outputting the code sequence corresponding to, the normalization process after the appearance of the recessive symbol is performed after the appearance of the dominant symbol. A binary image coding apparatus, which is provided separately from the normalization processing of 1. and an arithmetic code generating means for performing using the recessive symbol normalization shift number. 2. The estimation means comprises a probability estimation table in which the recessive symbol appearance probability and dominant symbol estimation data corresponding to the status are described.
2. The binary image encoding device according to. 3. The binary image code according to claim 2, wherein the recessive symbol normalization shift number corresponding to the status is described in the probability estimation table, and the calculating unit uses the probability estimation table. Device.