JP3124890B2 - Binary image coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary image encoding apparatus, and more particularly to a binary image encoding apparatus used for a facsimile apparatus, a soft copy facsimile apparatus, and an image filing apparatus as image communication equipment.

[0002]

2. Description of the Related Art Conventionally, JB has been used as a binary image encoding method.
The IG method has been proposed. The JBIG method performs predictive coding with reference to a pixel called a model template. There are two types of model templates, one for minimum resolution layer encoding and one for differential layer encoding.
The model template for the lowest resolution layer encoding of the JBIG system may use three lines as shown in FIG. 6A or may use two lines as shown in FIG. 6B. The pixel at position C is the pixel of interest to be coded for which the symbol appearance probability is estimated from a combination of “0” or “1”. The surrounding pixels are model templates, and the appearance probability of the symbol is obtained from the combination of “0” and “1” of each pixel.

As shown in FIG. 7, the JBIG-based differential layer encoding model template has four phases depending on the positional relationship between the pixels of the two layers. Each square of A in the figure represents a pixel of a certain layer having a pixel of interest to be coded, a circle of B in the figure represents a pixel of the next lower resolution layer, and C in the figure represents a pixel of the encoding target. Represents a pixel.

Next, the operation of the JBIG encoder will be described with reference to the flowchart of FIG.

First, an initialization process is performed (step S
1). Then, a context CX, which is a combination of the value PIX of the pixel to be coded and the surrounding pixel data, is read (step S2). Then, an ENCODE process for encoding the pixel value PIX is performed (Step S).
3). Then, the processing of steps S2 and S3 is repeated until the stripe of the image data ends (step S2).
4). Note that a stripe is a processing unit of JBIG image data. FLUSH processing for removing the entire contents of the register after the stripe ends (step S5)
Is performed, and the encoding process ends.

The registers used in the above flow include A
There are two types of registers, a register and a C register. The A register has a bit indicating the probability width. The C register has x bits for storing an unfinished code and b bits for inputting a completed code in 8-bit units. There is.

Next, the ENCODE process will be described with reference to the flowchart of FIG.

The value of the pixel of interest PIX and the value of the dominant symbol MPS are compared to determine that the pixel of interest to be encoded is the dominant symbol M
Or PS or poor posture symbol LPS is determined (step S
6). When the coding target pixel is judged to be poor posture symbol LPS is CODELPS processing is performed (step S7), CODEMPS processing is performed when it is determined that the probable symbol MPS (step S8).

[0009] Next, CODE to encode the degradation urging symbol
The LPS processing will be described with reference to the flowchart of FIG.

[0010] poor posture symbol from the A register occurrence probability LS
Z is subtracted (step S9). Then, the value and poor posture symbol occurrence probability LSZ the A register are compared (step S10), and if the value of A register is less than the value of LSZ,
The value of the A register is added to the C register, and the value of the A register is set to the value of LSZ (step S11). then,
The value of SWTCH indicating the inversion of the value of MPS is compared with 1 (step S12). If the value of SWTCH is 1, MPT
The value of S is inverted (step S13). Furthermore, NLP indicating the next status when the status ST is LPS
RENORME updated to the value of S and performing normalization at the same time
The process is performed (Step S14).

Next, a CODE for encoding a dominant symbol
The MPS process will be described with reference to the flowchart of FIG.

[0012] poor posture symbol from the A register occurrence probability LS
Z is subtracted (step S15). Then, the value of the A register is compared with 0x8000 (step S16), and A
Is greater than or equal to 0x8000, the CODEMPS process ends. When A is smaller than 0x8000, A and L
SZ is compared (step S17). If A is smaller than LSZ, the value of the A register is added to the C register, and A
The value of the register is set to LSZ (step S18). Then, the status ST is updated to the value of the NMPS indicating the next status when the status is the MPS, and at the same time, the RENOME process is performed (step S19).

Next, a RENOME process for performing normalization will be described with reference to the flowchart of FIG.

The A and C registers are both shifted one bit to the left. This corresponds to doubling the value of the A register and the value of the C register. At the same time, 1 is subtracted from the variable CT indicating the count value (step S2).
0). CT is compared with 0 (step S21). If CT is 0, BYTEOUT processing is performed (step S2).
2). Then, the value of the A register is compared with 0x8000 (step S23), and the processing from step S20 to step S22 is repeated until A becomes 0x8000 or more.

Next, the BYTEOUT processing will be described with reference to the flowchart of FIG.

The value of the variable TEMP is set to a value obtained by shifting the C register right by 19 bits (step S24). TE
MP is compared with 0xff (step S25). T
If EMP is greater than 0xff, 1 is added to BUFFER and BUFFER is output. In addition, the number 0x00 of the variable SC is output, and SC is set to 0. And
The value of BUFFER is set to a value obtained by ANDing TEMP and 0xff (step S26). On the other hand, TEMP is 0
If not greater than xff, TEMP is compared with 0xff (step S27). If TEMP = 0xff, SC
Is incremented by 1 (step S28). TEMP is 0xf
If less than f, BUFFER is output and SC times 0
After x00 is output, SC is set to 0. And B
The value of UFFER is set to the value of TEMP (step S2).
9). After the processing classified according to the value of TEMP is completed, the value of the C register is set to the value obtained by ANDing the C register and 0x7ffff, and CT is set to 8 (step S30).

Next, the initialization process will be described with reference to the flowchart of FIG.

It is determined whether the current stripe is the first stripe in the hierarchy or has been reset (step S).
31), if any of the conditions is met, the STs corresponding to all the CXs are set to 0, and the value of the MPS is set to 0 (step S32). If neither condition is satisfied, ST and MPS are set to the last values of the previous stripe (step S33). After performing step S32 or step S33, SC is set to 0, the value of the A register is set to 0x10000, the value of the C register is set to 0, and the value of CT is set to 11 (step S34).

Next, the FLUSH process will be described with reference to the flowchart of FIG.

CLEARBITS processing, FINALWR
The ITES process is performed, and the stripe encoded data SCD
Of the SCD and, if necessary, all the last 0x00 bytes of the SCD (step S
35).

Next, the CLEARBITS process will be described with reference to the flowchart of FIG. When the value of TEMP is A
A value obtained by ANDing 0xffff0000 with a value obtained by subtracting 1 from the register and adding the value of the C register (step S36). Then, TEMP is compared with the C register (step S37). If TEMP is smaller than the C register, the value of the C register is TEMP and 0x.
8000 (step S38). Also, T
If EMP is greater than or equal to C register, the value of C register is TE
The value of MP is set (step S39).

Next, the FINALWRITES process is shown in FIG.
7 will be described along the flowchart.

The value of the C register is shifted to the left by the value of CT (step S40). C register and 0x7fff
ffff (step S41), and when the value of the C register is larger than 0x7ffffff, BUFFER
Is output, and SC times 0x00 are output (step S42). The value of the C register is 0x7ff
If it is less than ffff, BUFFER is output and 0xff is output SC times (step S43). Step S
42 or after performing step S43, the C register is set to 19
The AND of 0xff and the bit shifted right are output, and the C register shifted to the right by 11 bits and 0 are output.
An AND with xff is output (step S44).

[0024] Incidentally, the probability estimation table, as shown in FIGS. 18a and FIG. 18b, poor posture symbol occurrence probability LSZ corresponding to the value of each status ST, the value of the next ST when LPS appeared NLPS, MPS is It shows the value NMPS of the next ST when it appears, and the value of SWTCH indicating whether the MPS is inverted. The JBIG system and the QM coder are described in “International Standards for Multimedia Coding” published by Maruzen Co., Ltd., P48 to P82.

[0025]

Since INVENTION Problems to be Solved conventional encoding technique is constructed as described above, the normalization process after the appearance poor posture symbol takes processing time for the shift amount is large,
There was a problem that the encoding process could not be speeded up.

[0026] The present invention has been made to solve the above problems, speed can binary image coding apparatus coding processing by shortening the normalization processing time at the time of poor posture symbol appearing The purpose is to provide.

[0027]

According to the present invention, an object of the present invention is to provide a binary image coding apparatus for losslessly coding binary image data, wherein a plurality of pixels around a pixel of interest to be coded are encoded. An image reference unit that refers to a predetermined template and calculates a context represented by a combination of binarized data corresponding to each of a plurality of pixels in the template, and a context corresponding to the context calculated by the image reference unit. Status output means for outputting the status stored in the memory address;
And estimation means for outputting the estimated energized symbol appearing probability and MPS, a calculating means for calculating the number of shifts during poor posture symbols normalized by said status, corresponding to the binary image data using the degradation biasing symbol appearance probability when outputting the code sequence, separately normalizing treatment after emergence inferior bias symbols and normalization process after superior symbol occurrence, and the arithmetic code generation means carried out using a number of time shift the poor posture symbols normalized It is accomplished by a two negative image encoding apparatus according to claim 1, comprising.

[0028] The estimation means may comprise a probability estimation table in which the poor posture symbol appearing probability and probable symbol estimation data have been described corresponding to the status.

Further, the inferiority corresponding to the status
The number of shifts at the time of the symbol symbol normalization is described in the probability estimation table, and the calculation means may use the probability estimation table.

[0030]

In the binary image coding apparatus according to the first aspect, a plurality of pixels around the target pixel to be coded by the image reference means are referenced using a template to correspond to each of the plurality of pixels in the template. binary context represented by a combination of data is calculated, the status is output stored in the memory address corresponding to a context that is calculated by the image reference unit by status output unit, poor posture thin from the status by the estimation means <br/> The bol appearance probability and the dominant symbol are estimated and output,
Status shift number when poor posture symbol normalization is calculated from the calculation means, when outputting code sequence corresponding to the binary image data using a poor posture symbol <br/> Le probability by arithmetic code generation means, the poor posture symbol appearing normalization process after separately from the normalization processing after MPS occurrence, normalization processing using the number of shifts during poor posture symbol normalization is performed. Thus, it is possible to shorten the time required for the normalization process when degradation biasing symbol appearing.

[0031] In the two negative image encoding apparatus according to claim 2, estimating means, by poor posture symbol appearing probability and MPS estimation data corresponding to the status is provided with a probability estimation table described, the poor posture symbol appearing probability and MPS readily estimated.

[0032] In the two negative image encoding apparatus according to claim 3, the number of shifts during poor posture symbols normalized corresponding to the status is described to defined estimation table, by the calculation means uses a probability estimation table, when poor posture symbol normalization may seek shift number easily.

[0033]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a binary image encoding apparatus according to the present invention.

As shown in FIG. 1, the binary image encoding apparatus according to the present embodiment refers to a plurality of pixels around a pixel of interest to be encoded of binary image data using the template 2, and Image reference means 1 for calculating context 100 represented by a combination of each bit of a plurality of pixels, and status 1 stored in memory address 3 corresponding to context 100 calculated by image reference means 1
01 and status output means 4 for outputting an estimation means 5 and outputting the estimated poor posture thin <br/> Bol probability and MPS from the status 101 to be output from the status output unit 4, poor posture from the status 101 a calculating means 6 for calculating the number of shifts at the symbol normalization, when outputting code sequence corresponding to the binary image data using a poor posture symbol occurrence probability output from estimation means 5, after the appearance poor posture symbol comprising the arithmetic code generating means 7 performs normalization processing using the number of shifts during poor posture symbols normalized output from the calculation means 6 is divided normalization processing to the normal processing. The estimating means 5 includes a probability estimating table.

Next, the operation of this embodiment will be described.

In this embodiment, the operation of the encoder and EN
The CODE processing is the same as in the above-described conventional example, and a description thereof will be omitted.

First, the CODELPS process will be described with reference to the flowchart of FIG.

First, the flag R is set to 0 (step S
51). Poor posture symbol appearance probability LSZ is subtracted from the A register (step S52). Then, the value and poor posture symbol occurrence probability LSZ the A register are compared (step S53), if the value of A register is more LSZ, the value of A register is added to the C register, the value of the A register is L
SZ is set (step S54), and the flag R is set to 1 (step S55). Then, the value of SWTCH is compared with 1 (step S56). If SWTCH is not 1, the value of MPS is inverted (step S57). Then, the value of the flag R is compared with 1 (step S58),
When the flag R is 1, the status ST is updated to the status when the LPS appears, and at the same time, the LSZRE is updated.
A NORME process is performed (Step S59). When the flag R is 0, the status ST is updated to the status when the LPS has appeared, and at the same time, the status ST is updated.
The processing is performed (Step S60).

Next, the CODEMPS process will be described with reference to the flowchart of FIG.

The flag R is set to 0 (step S61),
Poor posture symbol appearance probability LSZ is subtracted from the A register (step S62). The value of the A register is compared with 0x8000 (step S63), and the value of the A register is 0x
If it is 8000 or more, the CODEMPS process ends.
When the value of the A register is smaller than 0x8000,
A and LSZ are compared (step S64), and A
If it is smaller than Z, the value of the A register is added to the C register, and the value of the A register is set to LSZ (step S6).
5) The flag R is set to 1 (step S66). Next, the flag R is compared with 1 (step S67).
RENOOR at the same time as status is updated to S
An ME process is performed (Step S68). Flag R is 1
In the case of, the status is updated to the status when the appearance symbol is MPS, and at the same time, the LSZRENORME process is performed (step S69).

Next, the LSZRENORME process will be described with reference to the flowchart of FIG. First CT and SHF
T is compared (step S70). CT is SHF
If T or less, the A register is shifted left by the CT bit, the C register is shifted left by the CT bit, and SHF
CT is subtracted from T, and CT is set to 0 (step S7).
After 1), BYTEOUT processing is performed (step S).
72). Then, the SHFT is subtracted from CT (step S73), and the A register is shifted left by the SHFT bit and the C register is shifted left by the SHFT bit.

As shown in the probability estimation table of FIG. 5, the shift amount is smaller than in the conventional example, and the time required for the normalization processing can be reduced.

[0043]

Effects of the Invention According to the binary image encoding apparatus according to claim 1, separately normalizing treatment after emergence inferior bias symbols and normalization process after superior symbol occurrences, the number of time shifts poor posture symbols normalized since the normalization processing using is configured to be performed, thus reducing the time to normalization during poor posture symbol appearing, it is possible to improve the coding processing speed.

[0044] In the two negative image encoding apparatus according to claim 2 can readily estimate the degradation biasing symbol appearing probability and MPS.

[0045] In the two negative image encoding apparatus according to claim 3 can easily obtained the number of time shifts poor posture symbol normalization.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a binary image encoding device according to the present invention.

FIG. 2 is a flowchart illustrating a CODELPS process according to the present embodiment.

FIG. 3 is a flowchart illustrating CODEMPS processing of the present embodiment.

FIG. 4 is a flowchart illustrating an LSZRENORME process according to the present embodiment.

FIG. 5A is a diagram illustrating a part of a probability estimation table according to the present embodiment.

FIG. 5B is a diagram showing another part of the probability estimation table of the embodiment.

FIG. 6 is a diagram showing a lowest resolution layer model template.

FIG. 7 is a diagram showing a difference layer model template.

FIG. 8 is a flowchart showing the operation of a JBIG encoder.

FIG. 9 is a flowchart showing an ENCODE process.

FIG. 10 is a flowchart showing a conventional CODELPS process.

FIG. 11 is a flowchart showing a conventional CODEMPS process.

FIG. 12 is a flowchart illustrating a RENOMEME process.

FIG. 13 is a flowchart showing BYTEOUT processing.

FIG. 14 is a flowchart showing an INITENC process.

FIG. 15 is a flowchart showing FLUSH processing.

FIG. 16 is a flowchart showing CLEARBITS processing.

FIG. 17 is a flowchart showing a FINALWRITES process.

FIG. 18a is a diagram showing a part of a conventional probability table.

FIG. 18b is a diagram showing another part of the conventional probability table.

[Explanation of symbols]

 1 Image reference means 2 Template 3 Status output means 4 Memory 5 Estimation means 6 Calculation means 7 Arithmetic code generation means

Claims (3)

(57) [Claims] 1. A binary image coding apparatus for losslessly coding binary image data, wherein a plurality of pixels around a pixel of interest to be coded are referred to using a predetermined template, and a plurality of pixels in the template are referred to. Image reference means for calculating a context represented by a combination of binary data corresponding thereto, and status output means for outputting a status stored at a memory address corresponding to the context calculated by the image reference means; and estimation means for outputting the estimated degradation biasing symbol appearing probability and MPS from the status, and calculating means for calculating the number of shifts during poor posture symbols normalized by said status, the poor posture thin <br/> Bol appearance when outputting the code sequence corresponding to the binary image data using the probability, exits superior symbol normalization process after the appearance poor posture symbol After separately from normalization processing, the poor posture shea <br/> binary image encoding apparatus with an arithmetic code generation means for performing with symbol normalized when the number of shifts. Wherein said estimating means, according to claim 1 having a probability estimation table in which the poor posture symbol appearing probability and probable symbol estimation data have been described corresponding to the status
2. The binary image encoding device according to 1. Wherein the poor posture thin <br/> Bol normalized time shift numbers corresponding to the status is described in the probability estimation table, said calculating means to claim 2 using the probability estimation table A binary image encoding device according to claim 1.