JPH08186494A - Analog/digital converter - Google Patents

Abstract

PURPOSE: To suppress the increase of error even at the time of using an A/D converter for 10 bits as an A/D converter for 8 bits. CONSTITUTION: A 10-bit sequential approximation register 4 where the comparison result between an analog voltage and a comparison voltage is stored and an 8-bit incrementer 10 which takes conversion results of upper eight bits b9 , b8 ...b2 of the sequential approximation register 4 as the input and takes the conversion result of a second lower bit b1 as the input to a trigger terminal T are provided. The 8-bit conversion result and the 10-bit conversion result are read out from the 8-bit incrementer 10 and the sequential approximation register 4 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter.

[0002]

2. Description of the Related Art Single-chip microcomputers used by being incorporated in home electric appliances or industrial control equipment include analog / digital converters (hereinafter A) for converting analog voltages detected by various sensors into digital values. /
Some have a built-in D converter). As the sensor, for example, a temperature sensor, a humidity sensor, an atmospheric pressure sensor, or the like is used.

By the way, in recent years, with the increase in functionality and performance of such microcomputer application products, A /
Regarding the resolution of the D converter, 10-bit class is required. However, it is not necessary to convert all the output voltage of the sensor into a 10-bit digital value, and it is required only for some sensors that require high accuracy. For example, in the case of an 8-bit CPU, 8-bit data can be converted by analog / digital conversion at one time and processed, but in the case of 10-bit data, it is necessary to take in the data twice and the time to read the converted digital value Becomes longer. Therefore, only the sensor output that requires high accuracy is
Data is captured in bits and the sensor output that does not require high precision is processed with 8-bit A / D conversion results to improve overall performance.

As a method of obtaining an 8-bit conversion result using the 10-bit A / D converter, only the upper 8-bit conversion result is read and the lower 2-bit conversion result is ignored. Is a common conversion method.

FIG. 22 is a block diagram showing the configuration of a general successive approximation type A / D converter incorporated in a microcomputer. The analog voltage AN to be A / D converted is input to one input terminal of the comparator 1 and D / A to the other input terminal.
The comparison voltage output from the converter unit 2 is input.
The D / A converter unit 2 is composed of a ladder resistance circuit. A control signal from the control circuit 3 is input to the control terminal of the comparator 1. The comparison result of the comparator 1 is stored in the successive approximation register 4, and the conversion result of the successive approximation register 4 is input to the D / A converter unit 2. The address from the address decoder 5 is input to the successive approximation register 4, and the conversion result of the successive approximation register 4 is output to the data bus DB.

FIG. 23 is a schematic block diagram of the successive approximation register 4. Successive approximation register 4 is MSB (most significant bit) b
It is composed of 10 bits from ₉ to LSB (least significant bit) b _0, and is provided with a control unit 4 a for controlling the successive approximation register 4.

Next, the operation of this A / D converter will be described. When the control circuit 3 outputs a control signal for instructing the A / D conversion operation, the A / D conversion operation is started and MSB (b ₉ ) of the successive approximation register 4 is set to "1". Thereby D / A
Output from the converter unit 2 the comparison voltage (1/2) V _ref, the comparator 1 compares the comparison voltage (1/2) V _ref, and an analog voltage AN to be converted A / D. As a result of comparison,
When the analog voltage AN is lower, MSB (b ₉ ) is reset, and when the analog voltage AN is higher, MSB is kept set.

Next, "1" is set in the second bit b ₈ from the upper side.
If the MSB is set to “1”, the comparison voltage of (3/4) V _ref from the D / A converter unit 2 is set if the MSB is set to “1”. / 4) V _ref
The comparison voltage is output, and the comparator 1 compares the analog voltage AN with the comparison voltage for the second time. As a result of the comparison, when the analog voltage AN is smaller, the second bit b ₉ from the upper side is reset, and when the analog voltage AN is larger, the second bit b ₉ from the upper side is set. Hold on. This operation is repeated 10 times to convert the analog voltage into a 10-bit digital value and complete the A / D conversion operation. Then, the address is input from the address decoder 5 to the successive approximation register 4, and the successive approximation register 4
The conversion result of is output to the data bus DB.

In this way, the successive approximation register 4 is operated by the A / D.
During the conversion operation, the tap selection control of the ladder resistance circuit of the D / A converter unit 2 is performed, and finally the A / D converted conversion result is stored. In this way, a 10-bit A / D converter
The conversion characteristics when converted are as shown in FIG. In FIG. 24, the horizontal axis represents the analog voltage, and only the lower 4 bits are shown in digital value conversion. The vertical axis is the A / D conversion result, and the lower 4
Shows a bit. The thin solid line that has a step shape shows the ideal conversion characteristic when A / D conversion is performed to 10 bits, and the broken line shows the reasonable conversion characteristic when A / D conversion is performed to 8 bits. . In addition, the thick solid line that has a step shape is
The 8-bit conversion characteristics when A / D conversion to 10 bits and the lower 2 bits are discarded are shown.

Some A / D converters have one or more storage registers for storing the A / D conversion result, which is a successive approximation register at the end of A / D conversion. Therefore, only the conversion result is transferred to the storage register, and the function of the successive approximation register is similar.

[0011]

By the way, as described above, when A / D conversion is performed by the 10-bit A / D converter and the lower 2 bits are discarded, a thick solid line is formed as shown in FIG. The conversion characteristics are as shown below and the 8-bit A / D converter
The conversion characteristics shown by the D-converted broken line are not obtained. That is,
There is a problem that a conversion error of (3/8) LSB (error as an 8-bit A / D converter) occurs as compared with the 8-bit ideal conversion characteristic. The present invention has been A / D converted in view of such a problem.
It is an object of the present invention to provide an A / D converter that can reduce the conversion error even if the lower 2 bits of 10 bits are discarded.

[0012]

An A / D converter according to a first aspect of the invention is provided with a conversion result of a successive approximation register and is provided with an incrementer having a bit number smaller than that of the successive approximation register. The incrementer conversion result is incremented by the conversion result of the second bit from the lower side of.

According to the first aspect of the present invention, the analog voltage and the comparison voltage are compared, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the second bit from the lower side of the successive approximation register becomes "1", the conversion result of the incrementer is corrected by adding "1" to the conversion result of the incrementer to reduce the conversion error. As a result, the accuracy of the conversion result having the number of bits smaller than that of the successive approximation register can be improved.

The A / D converter according to the second aspect of the present invention receives the conversion result of the successive approximation register, increments the number of bits smaller than the number of bits of the successive approximation register, and the conversion result of the upper 2 bits of the successive approximation register. The successive approximation circuit, further comprising: a selection circuit to which the conversion result of the remaining bits excluding the upper 2 bits and the conversion result of the incrementer are input, and a determination circuit that determines the upper side bit and the lower side bit from which the conversion result is read. The conversion result of the incrementer is incremented according to the conversion result of the second bit from the lower side of the register, and the selection circuit is controlled by the discrimination circuit.

In the second aspect of the invention, the analog voltage is compared with the comparison voltage, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the second bit from the lower side of the successive approximation register becomes "1", the conversion result of the incrementer is corrected by adding "1" to the conversion result of the incrementer, and the conversion error is reduced. The conversion result of the upper 2 bits of the successive approximation register, the conversion result of the remaining bits except the upper 2 bits, and the conversion result of the incrementer are input to the selection circuit. When the discriminating circuit controls the selection circuit and the discriminating circuit discriminates that the upper bit is read, the incrementer conversion result is discriminated, and when the lower bit is discriminated, the remaining bits except the upper 2 bits of the successive approximation register are converted. If the result is determined to be a word read, the conversion result of all bits of the successive approximation register is read. As a result, the conversion result of the incrementer, the conversion result of the remaining bits other than the upper 2 bits of the successive approximation register, and the conversion result of all the bits of the successive approximation register can be selectively selected and read.

The A / D converter according to the third aspect of the present invention is a selection circuit to which the conversion result of the upper 2 bits of the successive approximation register, the conversion result of the remaining bits excluding the upper 2 bits and the conversion result of the incrementer are input. And a discriminating circuit for discriminating the high-order bit, the low-order bit, and the word, which are the reading units of the conversion result, and incrementing the conversion result of the incrementer according to the conversion result of the second bit from the low-order side of the successive approximation register. When reading the conversion result of the lower bit, the conversion result of the remaining bits except the upper 2 bits of the successive approximation register is read, and when the conversion result of the upper bit is read, the conversion result of the incrementer is written as a word. When the conversion result is read, the conversion result of the successive approximation register is selected.

In the third aspect of the invention, the analog voltage and the comparison voltage are compared, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the second bit from the lower side of the successive approximation register becomes "1", the conversion result of the incrementer is corrected by adding "1" to the conversion result of the incrementer, and the conversion error is reduced. The conversion result of the upper 2 bits of the successive approximation register, the conversion result of the remaining bits except the upper 2 bits, and the conversion result of the incrementer are input to the selection circuit. The selection circuit is controlled by the discriminating circuit, and when the discriminating circuit discriminates that the upper bit is read, the incrementer conversion result is read, and when the word is discriminated, the successive approximation register conversion result is read. This allows
It is possible to improve the accuracy of the conversion result having a bit number smaller than that of the successive approximation register. Further, the conversion result of the incrementer and the conversion result of the successive approximation register can be selectively selected and read.

An A / D converter according to a fourth aspect of the invention is supplied with the conversion result of the successive approximation register, has an incrementer with a bit number smaller than the bit number of the successive approximation register, and converts the lower 2 bits of the successive approximation register. The configuration is such that the incrementer conversion result is incremented by the logical product of the results.

In the fourth invention, the analog voltage is compared with the comparison voltage, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the lower 2 bits of the successive approximation register become "1", the logic of the AND circuit is established. The selection circuit selects the output of the AND circuit or the conversion result of the second bit from the lower side of the successive approximation register. The selected conversion result is input to the incrementer, “1” is added to the incrementer conversion result to correct the incrementer conversion result, and the correction error is reduced. As a result, the accuracy of the conversion result having the number of bits smaller than that of the successive approximation register can be improved.

An A / D converter according to a fifth aspect of the invention is supplied with the conversion result of the successive approximation register, has an incrementer with a number of bits larger than the number of bits of the successive approximation register, and converts the least significant bit of the successive approximation register. According to the result, the incrementer conversion result is incremented.

According to the fifth aspect of the invention, the analog voltage and the comparison voltage are compared, and each time the comparison is performed, the comparison result is stored in the successive approximation register and the incrementer having the number of bits smaller than the number of bits of the successive approximation register. When the least significant bit of the successive approximation register becomes "1", "1" is added to the conversion result of the incrementer. Of the conversion results corrected by the incrementer, the conversion result of the upper 8 bits is read. As a result, the accuracy of the conversion result having the number of bits smaller than that of the successive approximation register can be improved.

In the A / D converter according to the sixth aspect of the present invention, the conversion result of the successive approximation register is input, and the logical product of the incrementer having a bit number smaller than the bit number of the successive approximation register and the lower 2 bits of the successive approximation register. AND circuit that obtains
A selection circuit for selectively selecting the output of the AND circuit and the conversion result of the second bit from the lower side of the successive approximation register is provided, and the selection result of the selection circuit is input to the incrementer.

In the sixth aspect of the invention, the analog voltage and the comparison voltage are compared, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the lower 2 bits of the successive approximation register become "1", the logic of the AND circuit is established. The selection circuit selects the output of the AND circuit or the conversion result of the second bit from the lower side of the successive approximation register. The selected output or conversion result is input to the incrementer, and "1" is added to the incrementer conversion result to correct the incrementer conversion result. The incrementer conversion result or the successive approximation register conversion result is selected according to the register data. When the conversion result of the incrementer is selected, the (1/2) LSB correction by the digital / analog converter that converts the conversion result of the successive approximation register to the comparison voltage is stopped. As a result, the accuracy of the conversion result having the number of bits smaller than that of the successive approximation register can be further improved.

In the A / D converter according to the seventh aspect of the present invention, the conversion result of the successive approximation register is input, and the incrementer having a bit number smaller than that of the successive approximation register, the conversion result of the successive approximation register, and the incrementer of the successive approximation register. The conversion circuit includes a selection circuit that selectively selects the conversion result, and a register that stores data for controlling the selection circuit to read the conversion result with the number of bits of the incrementer and the successive approximation register. The conversion result of the second bit from the lower side is input to the incrementer, and the data of the register is input to the digital / analog conversion unit that converts the conversion result of the successive approximation register into the comparison voltage.

In the seventh invention, the analog voltage is compared with the comparison voltage, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the second bit from the lower side of the successive approximation register becomes "1", "1" is added to the conversion result of the incrementer to correct the conversion result of the incrementer. The incrementer conversion result or the successive approximation register conversion result is selected according to the register data. When the incrementer conversion result is selected, the (1/2) LSB correction by the digital / analog converter that converts the conversion result of the successive approximation register to the comparison voltage is stopped. As a result, the accuracy of the conversion result having the number of bits smaller than that of the successive approximation register can be further improved.

In the A / D converter according to the eighth aspect of the present invention, the conversion result of the successive approximation register is input, and the incrementer having a bit number smaller than that of the successive approximation register and the conversion result of the successive approximation register and the incrementer A selection circuit that selectively selects the conversion result; and a register that stores data for controlling the selection circuit to read the conversion result with the number of bits of the incrementer or the number of bits of the successive approximation register. The register data is input to the second bit from the lower side of the successive approximation register and to the digital / analog conversion unit that converts the conversion result of the successive approximation register into a comparison voltage.

In the eighth aspect of the invention, the analog voltage and the comparison voltage are compared, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When the second bit from the lower side of the successive approximation register becomes "1", "1" is added to the incrementer conversion result to correct the incrementer conversion result. When the incrementer conversion result is selected by the selection circuit, (1/2) LSB correction by the digital / analog converter is stopped. When the conversion of the second bit from the lower side of the successive approximation register is completed, the analog / digital conversion operation is completed. As a result, the accuracy of the conversion result with the number of bits smaller than the number of bits of the successive approximation register can be improved, and the same effect can be obtained by setting the end flag or generating an interrupt.

An A / D converter according to a ninth aspect of the present invention includes a plurality of terminals to which analog voltage is input, data of a successive approximation register, and an incrementer having a bit number smaller than that of the successive approximation register. A selection circuit for selectively selecting the conversion result of the successive approximation register and the conversion result of the incrementer, and data for controlling the selection circuit to read the conversion result by the number of bits of the incrementer or the number of bits of the successive approximation register. A plurality of registers that are stored are provided, and the conversion result of the second bit from the lower side of the successive approximation register is input to the incrementer.

In the ninth invention, the analog voltage input to the plurality of terminals is selected, the selected analog voltage is compared with the comparison voltage, and the comparison result is stored in the successive approximation register and the incrementer each time the comparison is performed. When 2 bits from the lower side of the successive approximation register become "1", "1" is added to the incrementer conversion result to correct the incrementer conversion result and reduce the conversion error. When the conversion result of the incrementer is selected, the (1/2) LSB correction in the digital / analog converter is stopped. The register controlling the selection circuit controls the selection circuit corresponding to the selected analog voltage terminal, and selects the incrementer conversion result or the successive approximation register conversion result. As a result, the conversion result of the incrementer or the conversion result of the successive approximation register can be selected before conversion corresponding to the selected analog voltage terminal.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings showing an embodiment of the present invention. 1 is a block diagram showing the configuration of a first embodiment of an A / D converter according to the present invention. The analog voltage AN to be A / D converted is input to one input terminal of the comparator 1, and the comparison voltage output from the D / A converter unit 2 is input to the other input terminal. The D / A converter unit 2 is composed of a ladder resistance circuit. The comparison result of the comparator 1 is input to the successive approximation register 4, and the conversion result which is the content of the successive approximation register 4 is input to the D / A converter unit 2.

The conversion result of the upper 8 bits of the successive approximation register 4 is input to an 8-bit incrementer (hereinafter referred to as an incrementer) 10. The result of conversion of the second bit b ₁ from the lower side of the successive approximation register 4 is the incrementer 10
Is input to the trigger terminal T of. The conversion result, which is the content of the incrementer 10, is output to the data bus DB. Control circuit 3
The control signal output by is input to the control terminal of the comparator 1. Incrementer output by the address decoder 5
The address corresponding to 10 and the address corresponding to the successive approximation register 4 are input to the address terminals of the incrementer 10 and the successive approximation register 4. The conversion result, which is the content of the successive approximation register 4, is output to the data bus.

FIG. 2 is a block diagram showing the configuration of the incrementer 10 shown together with the successive approximation register 4. The incrementer 10 is composed of 7 AND circuits and 8 EXOR circuits. The conversion result of the second bit b ₁ from the lower side of the successive approximation register 4 is input to each one input terminal of the EXOR circuit EO ₁ and the AND circuit A ₁ , and the other input terminal thereof receives the third bit from the lower side. The conversion result of bit b ₂ is input. AN
The output of the D circuit A ₁ is input to each one input terminal of the EXOR circuit EO ₂ and the AND circuit A ₂ , and the conversion result of the fourth bit b ₃ from the lower side is input to each of these other input terminals.

The output of the AND circuit A ₂ is the EXOR circuits EO ₃ and AN.
The contents of the fifth bit b ₄ are inputted to the respective one input terminals of the D circuit A ₃ . The output of the AND circuit A ₃ is input to each one input terminal of the EXOR circuit EO ₄ and the AND circuit A ₄ , and the conversion result of the sixth bit b ₅ from the lower side is input to each of these other input terminals.

The output of the AND circuit A ₄ is the EXOR circuits EO ₅ and AN.
It is inputted to each one input terminal of the D circuit A ₅ , and the conversion result of the seventh bit b ₆ from the lower side is inputted to each of those other input terminals. The output of AND circuit A ₅ is EXOR circuit EO ₆ and AND
It is input to each one input terminal of the circuit A ₆ , and the conversion result of the eighth bit b ₇ from the lower side is input to each of these other input terminals. The output of AND circuit A ₆ is EXOR circuit EO ₇ and AND
It is input to each one input terminal of the circuit A ₇ , and the conversion result of the ninth bit b ₈ from the lower side is input to the other input terminals thereof. The output of the AND circuit A ₇ is input to one input terminal of the EXOR circuit EO ₈ , and the conversion result of the 10th bit b ₉ from the lower side is input to the other input terminals. EXOR circuit EO ₁ , E
The outputs of O ₂ , EO ₃ , EO ₄ , EO ₅ , EO ₆ , EO ₇ , EO ₈ , and EO ₉ are bus buffers BB ₁ , BB ₂ , BB ₃ , BB ₄ , BB ₅ , B.
Data buses DB ₀ , DB ₁ , DB ₂ , via B ₆ , BB ₇ , and BB ₈
DB _3, is outputted to _{DB 4, DB 5, DB 6} , DB 7. In the bus buffers BB ₁ , BB ₂ , BB ₃ , BB ₄ , BB ₅ , BB ₆ , BB ₇ ,
The read signal RD common to them is input.

Next, the operation of the A / D converter configured as described above will be described. When the control circuit 3 outputs a control signal instructing A / D conversion, the A / D conversion operation starts. Then, first, the MSB (b ₉ ) of the successive approximation register 4 is set to "1". As a result, the D / A converter unit 2 outputs the comparison voltage of (1/2) V _ref , and the comparator 1 outputs the comparison voltage (1/2)
V _ref is compared with the analog voltage AN to be A / D converted. As a result of comparison, if the analog voltage AN is smaller, MS
B (b ₉ ) is reset, and conversely, when the analog voltage AN is higher, MSB (b ₉ ) is held in the set state.

Next, "1" is set in the second bit b ₈ from the upper side.
If the MSB (b ₉ ) is set to "1" by setting, the comparison voltage of (3/4) V _ref from the D / A converter unit 2 is not set to "1". Is (1/4) V _ref
The comparison voltage is output, and the comparator 1 compares the analog voltage AN with the comparison voltage for the second time. As a result of the comparison, when the analog voltage AN is smaller, the second bit b ₈ from the upper side is reset, and when the analog voltage AN is larger, the second bit b ₈ from the upper side is set. Hold on. In the case of a 10-bit A / D converter, such a comparison operation is repeated 10 times to obtain the final 10-bit A / D conversion result. In this way, when the A / D conversion operation is completed and the second bit b ₁ from the lower side is set to “1”, the incrementer 10 starts from the third bit b ₂ from the lower side. the operation of adding "1" to 8 bits from the 10th bit b _9. As a result, the conversion result of the incrementer 10 changes as shown in Table 1.

[0037]

[Table 1]

The 8-bit conversion characteristic obtained by the addition by the incrementer 10 is as shown in FIG. FIG.
Shows the analog voltage on the horizontal axis and the A / D conversion result on the vertical axis. As is clear from FIG. 3, the 8-bit conversion characteristic corrected by adding "1" by the 8-bit incrementer 10 is shown by a thick solid line, and approaches the 8-bit ideal conversion characteristic shown by the broken line. become.

As a result, the conversion error of the conventional A / D converter was + (3/8) LSB (see FIG. 24), but it was-(1/8) LSB.
Can be reduced to That is, by adding the small-scale incrementer 10, the accuracy of (1/4) LSB can be improved as compared with the conventional A / D converter.

FIG. 4 is a block diagram showing another embodiment of the incrementer 10. The output of the AND circuit A ₇ is input to the full scale flag 10a, and the content of the full scale flag 10a is output to the data bus DB _i . The other configuration is similar to that shown in FIG. 2, and the same components are designated by the same reference numerals. In this incrementer 10, when all the upper 9 bits from bit b ₉ to bit b ₁ are "1", "1" is set in the full scale flag 10a. Therefore, by reading both the conversion result of the incrementer 10 and the contents of the full scale flag 10a, bit b ₉
It is possible to discriminate between the case where the upper 9 bits from to b ₁ are all “1” and the conversion result of the incrementer 10 is “00 _H ”, and the case where it exceeds “FF _H ”. .

FIG. 5 is a block diagram showing still another embodiment of the incrementer 10. EXOR circuit EO ₁ , EO ₂ , EO ₃ ,
The outputs of EO ₄ , EO ₅ , EO ₆ , EO ₇ , and EO ₈ are OR circuits separately.
_{OR 1, OR 2, OR 3} , OR 4, OR 5, are input to OR _6, OR _7, one of the input terminals of the OR _8. OR circuit OR ₁ , OR ₂ , OR ₃ , O
The output of the AND circuit A ₇ is commonly input to the other input terminals of R ₄ , OR ₅ , OR ₆ , OR ₇ , and OR ₈ . OR circuit OR ₁ , OR ₂ ,
The outputs of OR ₃ , OR ₄ , OR ₅ , OR ₆ , OR ₇ , and OR ₈ are bus buffers BB ₁ , BB ₂ , BB ₃ , BB ₄ , BB ₅ , BB ₆ , and BB, respectively.
Input to ₇ and BB ₈ . The other configuration is similar to that shown in FIG. 2, and the same components are designated by the same reference numerals.

In this incrementer 10, even if the conversion result of the incrementer is "FF _H " or more, the conversion result of the incrementer 10 can be fixed to "FF _H ". It should be noted that the above-mentioned respective incrementers are merely examples, and the present invention is not limited to these. In addition, by combining the configurations of FIG. 4 and FIG. 5, it is possible to fix the conversion result of the incrementer in the case of "FF _H " or more to FF _H ", and to indicate by the flag that the full scale is exceeded. Although the successive approximation register and the incrementer are independent in these embodiments, the circuit scale can be reduced by incorporating the function of the incrementer into the successive approximation register and integrating them. As shown in FIG. 2, the circuit that outputs the conversion result of the incrementer 10 is generally output to the data bus via a buffer.

FIG. 6 is a block diagram showing the configuration of the second embodiment of the A / D converter according to the present invention. The same address is input from the address decoder 5 to the 8-bit incrementer 10 and the successive approximation register 4. Incrementer 10
And each output of the successive approximation register 4 is output to the data bus DB through a selection circuit SEL that selectively selects them. The selection circuit SEL is supplied with the data of the 8/10 switching register 11 which stores the data for outputting the 8-bit conversion result or the 10-bit conversion result to the data bus DB.
Otherwise, the configuration is similar to that shown in FIG.
The same components are designated by the same reference numerals.

This A / D converter performs the same A / D conversion operation as the A / D converter shown in FIG. And the incrementer
It is possible to input the same address to 10 and the successive approximation register 4 and output the conversion result of the incrementer 10 and the successive approximation register 4. Then, the data for selecting the 8-bit conversion result from the 8/10 switching register 11 is selected by the selection circuit SE.
When applied to L, the selection circuit SEL selects the conversion result of the incrementer 10 and outputs the 8-bit conversion result to the data bus DB.
Output to. On the other hand, when data for selecting the 10-bit conversion result is given to the selection circuit SEL, the successive approximation register 4
Select the conversion result of and select the 10-bit conversion result from the data bus.
Output to DB.

Since the same address is input to the incrementer 10 and the successive approximation register 4,
The user can create a program without paying attention to the read address.

FIG. 7 is a block diagram showing the configuration of the third embodiment of the A / D converter according to the present invention. The conversion result of the incrementer 10 and the successive approximation register 4 is input to the byte / word determination circuit 12, and the conversion result output from the byte / word determination circuit 12 is output to the data bus DB. Part-Time Job/
A byte signal and a read signal RD are given to the word discrimination circuit 12. The other configuration is the same as that shown in FIG. 1 or FIG. 6, and the same components are designated by the same reference numerals.

Table 2 shows the relationship between the register structure of a general 16-bit CPU and the address signal for accessing the 8-bit register for 4 bytes of address. The lower 8 bits of the register are placed at even addresses, and the upper 8
Bits are located at odd addresses. A0 and A1 indicate the lower 2 bits of the address signal. The byte is a byte signal which becomes “1” when the byte is accessed by the instruction of the CPU. At the time of word access, the byte signal becomes "0", and the even address and the odd address of the address are simultaneously output.

[0048]

[Table 2]

In the case of such a 16-bit CPU, the byte / word discrimination circuit 12 shown in FIG. 7 can be realized by the circuit shown in FIG. FIG. 8 is a block diagram showing the configuration of the byte / word discrimination circuit. Byte signal is AND circuit 12a
Is input to the inverter 12b and the output of the inverter 12b is input to the input terminal of the AND circuit 12c. The conversion result of the incrementer 10 is input to the other input terminal of the AND circuit 12a, and the conversion result of the successive approximation register 4 is AN.
Input to other input terminal of D circuit 12c. AND circuit 12a, 12
The output of c is separately input to one input terminal and the other input terminal of the OR circuit 12d. The output of the OR circuit 12d is output to the data bus DB via the buffer 12e. The read signal RD is input to the buffer 12e.

Next, the operation of the byte / word discrimination circuit 12 will be described. When outputting the lower address in byte units, the conversion result of the incrementer 10 is output to the data bus DB. When outputting in word units, the conversion result of the successive approximation register 4 is output to the data bus DB. This eliminates the need for the user to set the data for selecting in 8-bit units or 10-bit units in the register, and the data can be automatically processed by changing the output method of the conversion result.

FIG. 9 is a block diagram showing the configuration of the fourth embodiment of the A / D converter according to the present invention. The conversion result of the incrementer 10, the high-order 2 bits b ₉ , b of the successive approximation register 4
₈ conversion result and lower 8 bits b of successive approximation register 4
The conversion results of _{7 to} b ₀ are input to the selection circuit 13. The selection circuit 13 has an L / H that discriminates between the lower bit side and the upper bit side.
The determination result of the word determination circuit 14 is input, and the read signal RD is also input. The lowest address signal A0 and byte signal are input to the L / H word discrimination circuit 14. The output of the selection circuit 13 is separately output to the data bus DB on the lower bit side and the data bus DB on the higher bit side. The other configuration is the same as the configuration in FIG.

This A / D converter automatically discriminates the byte access on the lower bit side, the byte access on the higher bit side, and the word access respectively. When the lower bit side is accessed on a byte basis, the successive approximation register 4 The conversion result of the lower 8 bits of is output, the conversion result of the incrementer 10 is output when the upper bit side is accessed in bytes, and the conversion result of all bits of the successive approximation register 4 is output when the word is accessed. I am trying to output.

FIG. 10 shows an L / H word discrimination circuit 14 and a selection circuit.
FIG. 13 is a block diagram showing the configuration of 13. Lowest address signal
A0 is input to one input terminal of the AND circuit 14a and the inverter 14b. The output of the inverter 14b is input to one input terminal of the AND circuit 14c. The byte signal is the other input terminal of the AND circuit 14a, the other input terminal of the AND circuit 14c and the inverter 14d.
Is input to. The output of the AND circuit 14a is input to one input terminal of the AND circuit 14e. The output of the AND circuit 14c is the OR circuit 14
Input to one input terminal of f. The output of the inverter 14d is A
It is input to one input terminal of the ND circuit 14g and the other input terminal of the OR circuit 14f. The conversion result of the upper 2 bits of the successive approximation register 4 is input to the other input terminal of the AND circuit 14g. The 8-bit conversion result of the incrementer 10 is input to the other input terminal of the AND circuit 14e. The outputs of the AND circuits 14g and 14e are separately input to one input terminal and the other input terminal of the OR circuit 14h, and the output is output to the data bus DB on the upper bit side via the buffer 14i to which the read signal RD is given. . OR circuit
The output of 14f is input to one input terminal of the AND circuit 14j, and the read signal RD is input to the other input terminals. The output of the AND circuit 14j is given to the buffer 14k. The conversion result of the lower 8 bits of the successive approximation register 4 is output to the data bus DB on the lower bit side via the buffer 14k.

Next, the operation of the A / D converter thus configured will be described. When byte-accessing the lower bit side,
The lowest address signal A0 is "0" and the byte signal is "1"
And the output of the AND circuit 14c becomes "1". As a result, when the read signal RD is generated, the conversion result of the lower 8 bits of the successive approximation register 4 is output to the data bus on the lower bit side.

When the upper bit side is byte-accessed,
The lowest address signal A0 is "1" and the byte signal is "1"
And the output of the AND circuit 14a becomes "1". As a result, the 8-bit conversion result of the incrementer 10 is output to the data bus DB on the upper bit side.

In the case of word access, the inverter 14
The output of d becomes "1", and the higher 2 of successive approximation register 4
The bit conversion result is output to the data bus DB on the upper bit side. In this way, by changing the output method of the 1-word register, the conversion result of the lower 8 bits of the successive approximation register 4, the 8 bits of the incrementer 10, and all the bits of the successive approximation register 4 are automatically output. can do.

Depending on the application, A / D
The output voltage of the sensor that is input to the converter does not change significantly and may fluctuate little by little. In this case, the upper 2 bits are ignored, and only the lower 8 bit conversion result is normally output, and when the sensor output voltage exceeds the predetermined range, the upper 2 bit conversion result is also output. obtain.

In this embodiment, the lower 8 bits of the successive approximation register 4 are output when the conversion result on the lower bit side is output, and the 8-bit conversion result of the incrementer 10 is output when the conversion result on the higher bit side is output. Is output in word units, the conversion result of all bits of the successive approximation register 4 is output, but the present invention is not limited to this. In other words, when outputting the conversion result of the lower bit side, the incrementer 10
Of the 8-bit conversion result, the lower 8-bit conversion result of the successive approximation register 4 is output when the upper-bit conversion result is output, and the conversion result of all bits of the successive approximation register 4 is output in word units. It can also be output.

When outputting the conversion result on the lower bit side, the 8-bit conversion result of the incrementer 10 is output, and when outputting the conversion result on the higher bit side, the upper 2-bit conversion result of the successive approximation register 4 is output. When outputting the result in word units, the conversion result of all bits of the successive approximation register 4 can be output.

FIG. 11 is a block diagram showing the configuration of the fifth embodiment of the A / D converter according to the present invention. Successive approximation register 4
LSB (b ₀ ), the conversion result of the second bit b ₁ from the lower side is separately input to one input terminal and the other input terminal of the AND circuit AD ₁₀ . The output of the AND circuit AD ₁₀ is input to the trigger terminal T of the incrementer 10. The other configurations are similar to those shown in FIG. 1, and the same components are designated by the same reference numerals.

The A / D converter configured as described above adds "1" to the 8-bit conversion result of the incrementer 10 when the conversion results of the lower 2 bits b ₁ and b ₀ are both "1". As a result, the conversion result changes as shown in Table 3.

[0062]

[Table 3]

FIG. 12 shows the 8-bit conversion characteristic corrected by adding "1" to the 8-bit conversion result of the incrementer.
As shown in. In FIG. 12, the horizontal axis is the analog voltage, and the vertical axis is the conversion result. The corrected 8-bit conversion result is shown by a thick staircase solid line. The conversion accuracy is the same as that of the A / D converter shown in FIG. 1, but the conversion error can be changed from the negative (−) side (see FIG. 3) to the positive (+) side. The full scale flag provided in the A / D converter of FIG. 1 can be applied to this embodiment as well. Further, the control method of the output system of the A / D converter shown in FIGS. 6, 7 and 9 can be similarly applied to this embodiment.

FIG. 13 is a block diagram showing the configuration of the sixth embodiment of the A / D converter according to the present invention. Successive approximation register 4
The conversion result of the upper 9 bits of is the 9-bit incrementer 30
Is input to. The conversion result of LSB (b ₀ ) of the successive approximation register 4 is input to the trigger terminal T of the incrementer 30.
8-bit conversion result from incrementer 30 is data bus
Output to DB. The other configurations are similar to those in FIG. 1, and the same components are designated by the same reference numerals.

This A / D converter adds "1" to the 9-bit conversion result of the incrementer 30 when LSB (b ₀ ) is "1". When outputting the conversion result corrected by the incrementer 30, only the conversion result of the upper 8 bits is output to the data bus.
Output to DB. As a result, the conversion result can be output like the A / D converter shown in FIG. Then, the full-scale flag provided in the A / D converter shown in FIG. 1 can be applied to this embodiment. Further, the control method of the output system of the A / D converter shown in FIGS. 6, 7 and 9 can be similarly applied to this embodiment.

FIG. 14 is a block diagram showing the configuration of the seventh embodiment of the A / D converter according to the present invention. Successive approximation register 4
The lower 2 bits b ₁ and b ₀ of the conversion result are AND circuit separately
Input to one input terminal of AD ₁₁ , the other input terminal. AND circuit
The output of AD ₁₁ is input to the trigger terminal T of the 8-bit incrementer 10 via the selection circuit SEL. The conversion result of the second bit b ₁ from the lower side of the successive approximation register 4 is input to the trigger terminal T of the incrementer 10 via the selection circuit SEL. The data of the +/- error switching register 15 storing the data for switching the selection circuit SEL to make the error positive or negative is given to the selection circuit SEL.

That is, this A / D converter is the same as the A / D converter shown in FIG.
It is a combination of the configurations of the converter and the A / D converter shown in FIG. As a result, the error of + (1/8) LSB and the error of − (1/8) LSB can be changed by the data of the +/− error switching register 15. Thereby, one A / D converter can appropriately select the error on the positive side and the error on the negative side. The full scale flag provided in the A / D converter shown in FIG. 1 can also be applied to this embodiment. Further, the control method of the output system of the A / D converter shown in FIGS. 6, 7 and 9 can be similarly applied to this embodiment.

FIG. 15 is a block diagram showing the configuration of the eighth embodiment of the A / D converter according to the present invention. The data of the 8/10 switching register 16 storing the data for selecting the data for outputting the conversion result to be 8 bits or 10 bits is given to the selection circuit SEL and the D / A converter unit 2. The other configurations are similar to those shown in FIG. 6, and the same components are designated by the same reference numerals.

The above-mentioned A / D converters up to this point are + (1 /
8) LSB or − (1/8) LSB conversion error occurred, but 10-bit A / D conversion is performed to eliminate this error (1/2) L
It is realized by stopping the operation of the SB correction circuit. While the A / D conversion itself so far described above has always operated as a 10-bit A / D converter, in the present embodiment, A / D conversion is performed.
Before starting conversion, it is necessary to set in advance whether 8-bit A / D conversion or 10-bit A / D conversion is performed by the 8/10 switching register 16. Therefore, when performing 10-bit A / D conversion as a 10-bit A / D converter, the same operation as before is performed, but when performing 8-bit A / D conversion, 10-bit A / D conversion is performed. Disable (1/2) LSB correction by the converter (1/2) LSB correction circuit.

A method without such (1/2) LSB correction will be described by taking a 2-bit A / D converter as an example. FIG. 16 is a configuration diagram of the ladder resistance circuit of the D / A converter section in the 2-bit A / D converter. Reference voltage V _ref and ground voltage V
Eight resistors R ₁ , R ₂ ... R having the same resistance value with _SS
8 is interposed. The tap voltage 3/4 V _{ref at} the connection between the resistors R ₂ and R ₃ is passed through the switching circuit S ₁ , and the tap voltage 2/4 V _{ref at} the connection between the resistors R ₄ and R ₅ is at the switching circuit S ₂
1/4 tap voltage at the connection between resistors R ₆ and R ₇ via
V _ref is input to a comparator (not shown) via the switching circuit S ₃ .

[0071] The tap voltage 5/8 V _ref at the connection of the resistor R ₃ and R ₄ via an on-off circuit S _4, resistor R ₅ and R ₆
The tap voltage 3/8 V _ref of the connection part with is connected to the tap voltage 1/8 V of the connection part of the resistors R ₇ and R ₈ via the switching circuit S _5.
ref is input to the comparator via the switching circuit S ₆ . The ladder resistor circuit is normally input (1/2) in order to perform the LSB corrected tap voltage of _{1/8 V ref, 3 / 8V ref} , 5 / 8V ref to the comparator. The conversion result obtained by the D / A conversion in this way is as shown in FIG. 17. When the (1/2) LSB correction is performed, the conversion result closest to the straight line showing the ideal conversion characteristic can be obtained.

By the way, 1/4 V _ref , _2/4 shown in FIG.
When A / D conversion by using the tap voltage V _ref, 3 / 4V _ref as shown in FIG. 18. And the A / D converter of the present embodiment, as shown in FIG. 16, (1/2) LSB corrected voltage,
(1/2) It is designed to be able to take out both the voltage without LSB correction. Therefore, the conversion result when actually operating as an 8-bit A / D converter without (1/2) LSB correction is shown in Fig. 19
It becomes as shown in. In FIG. 16, the case of a 2-bit A / D converter has been described, but the method and concept are the same even with an actual 10-bit A / D converter, only the number of ladder resistors increases.

Therefore, in the D / A converter shown in FIG. 15, the tap voltage at which (1/2) LSB correction is not performed in the 8-bit mode
The _{1/4 V ref, 2 / 4V ref} , 3 / 4V ref may be input to the comparator 1 removed. In this embodiment, the implementation method in the case where (1/2) LSB correction is performed in the D / A converter unit 2 has been described. However, depending on the A / D converter, the
/ 2) LSB correction may be performed. Even in this case, it can be realized by adding a circuit that does not perform (1/2) LSB correction in the 8-bit mode based on the same idea. Further, the full scale flag provided in the A / D converter shown in FIG. 1 can be applied to this embodiment.

FIG. 20 is a block diagram showing the configuration of the ninth embodiment of the A / D converter according to the present invention. 8/10 switching register 11
The data for selecting the 8-bit or 10-bit conversion result, which is stored in, is input to the second bit b ₁ from the lower side of the D / A converter unit 2 and the successive approximation register 4. The other configuration is the same as the configuration shown in FIG. 6, and the same components are designated by the same reference numerals.

As described above, the A / D converter shown in FIG.
When used in the mode that outputs the bit conversion result, unlike the A / D converter shown in FIGS. 6, 7, 9, 11, 13, and 14, the 10-bit conversion result cannot be obtained. . That is, the upper 9 bits b _{9 to} b ₁ are used to obtain the 8-bit conversion result, and the LSB (b ₀ ) is not used at all.

Therefore, in this embodiment, in order to speed up the A / D conversion operation, the A / D conversion operation is terminated when the comparison operation of the second bit b ₁ from the lower side is completed. Therefore, this A / D converter outputs the data DT from the 8/10 switching register 11 when outputting the 8-bit conversion result.
Becomes active, the (1/2) LSB correction is stopped, and the data is input to the successive approximation register 4 and also to the successive approximation register 4, and the successive approximation register 4 receives the bit b.
_{When the} conversion operation is completed up to ₁ , the A / D conversion operation is completed. The end of such A / D conversion operation is notified to the CPU by setting the end flag or generating an interrupt signal.
Therefore, without actually ending the A / D conversion operation,
By setting the end flag or generating the interrupt signal when the conversion of the bit b ₁ of the successive approximation register 4 is completed,
Similarly, it is possible to shorten the A / D conversion time.

FIG. 21 is a block diagram showing the configuration of the tenth embodiment of the A / D converter according to the present invention. First analog voltage
AN ₁ is connected to the second analog voltage AN ₂ via the switching circuit S _10.
Is input to one input terminal of the comparator 1 via the switching circuit S ₁₁ . The data for the analog voltage AN ₁ stored in the 8/10 switching register 16 is passed through the switching circuit S ₁₂ , the data for the analog voltage AN ₂ is passed through the switching circuit S ₁₃ , and the selection circuits SEL and D / A. It is input to the converter unit 2. The data of the analog input selection register 17 storing the data for selecting the analog voltage is given to the switching circuits S ₁₀ , S ₁₁ and the switching circuits S ₁₂ , S ₁₃ as a switching signal. Other configurations are the same as the configurations shown in FIG. 15, and the same components are designated by the same reference numerals.

Depending on the A / D converter, there are a plurality of activation methods. For example, activation by software by access from the CPU, activation by timer timing termination, activation by an external trigger due to a signal change at an external terminal, etc. is there.
In such an A / D converter having a plurality of activation factors, since it is triggered asynchronously, it is difficult to switch in advance to select an 8-bit or 10-bit conversion result.
Therefore, in order to solve this, an 8-bit / 10-bit switching register corresponding to each analog voltage is provided,
It is possible to automatically select the 8-bit conversion result or the 10-bit conversion result in accordance with the analog voltage selected when the activation factor occurs.

Although FIG. 21 describes the case where there are two types of analog voltage, since it can be provided by providing an 8 / 10-bit switching register corresponding to the number of types of analog voltage,
The type of analog voltage is not limited in any way. In certain applications, the analog voltage AN
It is also possible to fix ₁ as the 8-bit conversion result and the analog voltage AN ₂ as the 10-bit conversion result.

The block diagram showing the configuration of each embodiment of the A / D converter described above is an example used for comparing the present invention with the prior art, and is not limited to this.
Also, the case where the 10-bit A / D converter is used as the 8-bit A / D converter has been described, but the number of bits is not limited, and for example, an 11-bit A / D converter is used. 8-bit A / D converter, or 6-bit
Use the A / D converter as a 4-bit A / D converter, etc.
Even if the number of bits is changed, the same effect can be obtained.
Further, FIGS. 9, 15, 20, either in the trigger terminal T of the analog / digital converter shown in either the lower bits b _0, the logical product of the signal b _1, as shown in FIG. 11 in FIG. 21, FIG. 13, the signal of the least significant bit b ₀ , or the signal of the logical product of the lower bits b ₀ and b ₁ and the lower bit b as shown in FIG.
₁ of signals alternatively selecting signals, the same effect can be obtained by entering any of them.

[0081]

As described above, according to the present invention, the number of bits is smaller than the number of bits of the successive approximation register that stores the comparison result obtained by comparing the analog voltage and the comparison voltage. Equipped with an incrementer to be input, "1" is added to the conversion result of the incrementer according to the conversion result of a predetermined bit from the lower side of the successive approximation register.
Is added to correct the incrementer conversion result, and the incrementer obtains the conversion result with the number of bits smaller than the number of bits of the successive approximation register, so the conversion result of the successive approximation register and the number of bits of the successive approximation register A conversion result with a smaller number of bits can be obtained with high accuracy.

Further, according to the first aspect of the invention, the circuit can be constructed by a simple circuit to which an incrementer is added. According to the second aspect of the present invention, the conversion result of the high-order side bit and the conversion result of the low-order side bit can be read by the determination by the determination circuit.

According to the third aspect of the present invention, the conversion result of the remaining bits except the upper 2 bits of the successive approximation register, the conversion result of the incrementer, and the conversion result of all the bits of the successive approximation register are selectively selected and read. obtain.

According to the fourth invention, the error in the conversion result of the incrementer can be changed from the negative side to the positive side.

According to the fifth invention, it is possible to improve the accuracy of the conversion result of the bit number smaller than the bit number of the successive approximation register by using the incrementer having the bit number smaller than the bit number of the successive approximation register by one bit.

According to the sixth aspect of the invention, the incrementer conversion error can be changed into a positive error or a negative error.

According to the seventh aspect of the invention, when selecting the incrementer conversion result, (1/2) LSB of the successive approximation register is used.
The correction may be stopped and the accuracy of the conversion result may be improved.

According to the eighth invention, when the incrementer conversion result is selected, (1/2) LSB by the successive approximation register is selected.
The correction can be stopped to improve the accuracy of the conversion result, and the analog / digital conversion operation can be ended when the conversion of the second bit from the lower side of the successive approximation register is completed.

According to the ninth aspect, the analog voltage input to the plurality of terminals to which the analog voltage is input is selected, and the conversion result of the incrementer or the successive approximation register of the incremental approximation register is selected according to the selected analog voltage terminal. The present invention has excellent effects such as selection of a conversion result.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an analog / digital converter according to the present invention.

FIG. 2 is a block diagram showing a configuration of an 8-bit incrementer.

FIG. 3 is a characteristic diagram showing analog / digital conversion characteristics.

FIG. 4 is a block diagram showing the configuration of another embodiment of the 8-bit incrementer.

FIG. 5 is a block diagram showing the configuration of still another embodiment of the 8-bit incrementer.

FIG. 6 is a block diagram showing a configuration of a second exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 7 is a block diagram showing a configuration of a third exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 8 is a block diagram showing a configuration of a byte / word discrimination circuit.

FIG. 9 is a block diagram showing a configuration of a fourth exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 10 is a block diagram showing configurations of an L / H word discrimination circuit and a selector.

FIG. 11 is a block diagram showing a configuration of a fifth exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 12 is a characteristic diagram of analog / digital conversion characteristics.

FIG. 13 is a block diagram showing a configuration of a sixth exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 14 is a block diagram showing the configuration of a seventh exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 15 is a block diagram showing the configuration of an eighth exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 16 is a circuit diagram of a ladder resistance circuit of a D / A converter unit.

FIG. 17 is a 2-bit analog / digital converter (1
/ 2) It is a characteristic diagram of an analog / digital conversion characteristic after LSB correction.

FIG. 18 shows a 2-bit analog / digital converter (1
/ 2) It is a characteristic diagram of an analog / digital conversion characteristic without LSB correction.

FIG. 19 is a characteristic diagram of 8-bit conversion characteristics without (1/2) LSB correction.

FIG. 20 is a block diagram showing the configuration of a ninth exemplary embodiment of an analog / digital converter according to the present invention.

FIG. 21 is a block diagram showing the configuration of a tenth embodiment of the analog / digital converter according to the present invention.

FIG. 22 is a block diagram showing a configuration of a conventional successive approximation type analog / digital converter.

FIG. 23 is a schematic configuration diagram of a successive approximation register.

FIG. 24 is a characteristic diagram of analog / digital conversion characteristics.

[Explanation of symbols]

1 comparator, 2 D / A converter, 4 successive approximation register, 10 8 bit incrementer, 10a full scale flag, 11 8/10 switching register, 12 bytes /
Word discrimination circuit, 14 L / H word discrimination circuit, 309 9-bit incrementer, A _{1 to} A ₇ AND circuit, EO _{1 to} EO ₈
EXOR circuit, SEL selection circuit, AD ₁₀ AND circuit.

Claims (18)

[Claims] 1. An analog / digital converter that compares a comparison voltage obtained by dividing a reference voltage with an analog voltage, converts the analog voltage into a digital value, and stores the conversion result in a successive approximation register. The conversion result of the successive approximation register is input, and an incrementer having a bit number smaller than that of the successive approximation register is provided, and the conversion result of the incrementer is incremented by the conversion result of the second bit from the lower side of the successive approximation register. An analog / digital converter characterized by being configured. 2. An analog / digital converter for comparing a comparison voltage obtained by dividing a reference voltage with an analog voltage, converting the analog voltage into a digital value, and storing the conversion result in a successive approximation register, The conversion result of the successive approximation register is input, the incrementer having the number of bits smaller than the number of bits of the successive approximation register, the conversion result of the upper 2 bits of the successive approximation register, the conversion result of the remaining bits excluding the upper 2 bits, and the incrementer. A conversion circuit for inputting the conversion result of the data, and a discrimination circuit for discriminating the high-order side bit and the low-order side bit from which the conversion result is read, and the incrementer according to the conversion result of the second bit from the low-order side of the successive approximation register. Is configured to increment the conversion result of, and the discrimination circuit is configured to selectively control the selection circuit. Analog / digital converter according to claim. 3. An analog / digital converter that compares a comparison voltage obtained by dividing a reference voltage with an analog voltage, converts the analog voltage into a digital value, and stores the conversion result in a successive approximation register. An incrementer having a bit number smaller than that of the successive approximation register, a conversion result of the upper 2 bits of the successive approximation register, a conversion result of the remaining bits excluding the upper 2 bits, and a conversion result of the incrementer are input. And a discriminating circuit for discriminating the high-order bit, the low-order bit, and the word, which are the reading units of the conversion result, and incrementing the conversion result of the incrementer according to the conversion result of the second bit from the low-order side of the successive approximation register. When reading the conversion result of the lower bit, the upper 2 bits of the successive approximation register
The conversion result of the remaining bits except the bit, the conversion result of the incrementer when reading the conversion result of the upper bit,
Analog / characterized in that the conversion result of the successive approximation register is selected when reading the word conversion result.
Digital converter. 4. An analog / digital converter for comparing a comparison voltage obtained by dividing a reference voltage with an analog voltage, converting the analog voltage into a digital value, and storing the conversion result in a successive approximation register. A conversion result of the successive approximation register is input, an incrementer having a bit number smaller than that of the successive approximation register is provided, and the conversion result of the incrementer is incremented by logical product of the conversion results of the lower two bits of the successive approximation register. An analog / digital converter characterized in that 5. An analog / digital converter for comparing a comparison voltage obtained by dividing a reference voltage with an analog voltage, converting the analog voltage into a digital value, and storing the conversion result in a successive approximation register, The conversion result of the successive approximation register is input, the incremental number of bits is smaller than the number of bits of the successive approximation register, and it is configured to increment the conversion result of the incrementer by the conversion result of the least significant bit of the successive approximation register. An analog / digital converter characterized by. 6. A comparison voltage obtained by dividing a reference voltage and an analog voltage are compared to convert the analog voltage to digital,
Analog that stores the conversion result in the successive approximation register
In the digital converter, the conversion result of the successive approximation register is input, an incrementer having a bit number smaller than that of the successive approximation register, a logical product circuit for obtaining a logical product of the lower 2 bits of the successive approximation register, and the logical A selection circuit for selectively selecting the output of the product circuit and the conversion result of the second bit from the lower side of the successive approximation register, and inputting the selection result of the selection circuit to the incrementer, the conversion result of the incrementer An analog / digital converter characterized by being configured to increment. 7. An analog / digital converter for comparing a comparison voltage obtained by dividing a reference voltage with an analog voltage, converting the analog voltage into a digital value, and storing the conversion result in a successive approximation register, An incrementer having the number of bits less than the number of bits of the successive approximation register, the selection circuit that selectively selects the conversion result of the successive approximation register and the conversion result of the incrementer, and the incrementer. And a register that stores data for controlling the selection circuit to read the conversion result by the number of bits of the successive approximation register, and inputs the conversion result of the second bit from the lower side of the successive approximation register to the incrementer. Then, the data of the register is converted into a comparison voltage by converting the conversion result of the successive approximation register into a digital / analog conversion. Analog / digital converters, characterized by being configured so as to input to. 8. An analog / digital converter for comparing a comparison voltage obtained by dividing a reference voltage with an analog voltage, converting the analog voltage into a digital value, and storing the conversion result in a successive approximation register, An incrementer having the number of bits less than the number of bits of the successive approximation register, the selection circuit that selectively selects the conversion result of the successive approximation register and the conversion result of the incrementer, and the incrementer. And a register storing data for controlling the selection circuit to read the conversion result with the number of bits of the successive approximation register or the number of bits of the successive approximation register. It is configured to input the conversion result of the bit and the successive approximation register to a digital / analog conversion unit which converts the conversion result into a comparison voltage. Analog / digital converter, wherein the door. 9. The analog / digital converter according to claim 8, wherein the end flag is set when the conversion of the second bit from the lower side of the successive approximation register is completed. 10. The analog / digital converter according to claim 8, wherein an interrupt signal is output when the conversion of the second bit from the lower side of the successive approximation register is completed. 11. A plurality of terminals to which an analog voltage is input are provided, a comparison voltage obtained by dividing a reference voltage is compared with the analog voltage, the analog voltage is converted into a digital value, and the conversion result is sequentially obtained. In an analog / digital converter for storing in an approximation register, the data of the successive approximation register is input, and an incrementer having a bit number smaller than that of the successive approximation register, a conversion result of the successive approximation register, and a conversion result of the incrementer. It is provided with a selection circuit that selectively selects and a plurality of registers that store data for controlling the selection circuit to read the conversion result with the number of bits of the incrementer or the number of bits of the successive approximation register. Input the conversion result of the second bit from the lower side of the register to the incrementer and increment the conversion result of the incrementer. Analog / digital converter, characterized in that the configuration in which cement. 12. The analog / digital converter according to claim 11, wherein the number of registers for controlling the selection circuit is equal to the number of terminals to which an analog voltage is to be input. 13. The claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, claim 8 wherein the incrementer is provided with a full scale flag.
The analog / digital converter described in any one of 11. 14. The claim 1, claim 2, claim 3, claim 4, claim 5, claim 5, and claim 5 configured to output 1 to all bits when the value of the incrementer is full scale. 6. An analog / digital converter according to claim 6, claim 7, claim 8 or claim 11. 15. The incrementer is provided with a full-scale flag, and when the incrementer is full-scale,
Any one of claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, and claim 11 configured to output 1 to all bits thereof. The described analog / digital converter. 16. The analog / signal according to claim 1, further comprising a selection circuit for selectively selecting the conversion result of the successive approximation register and the incrementer. Digital converter. 17. The method according to claim 1, further comprising a selection circuit for selectively selecting the conversion result of the successive approximation register and the incrementer, and a register for controlling the selection circuit. 6. The analog / digital converter described in any one of 6. 18. A successive approximation register and a byte / word discrimination circuit to which the conversion result of the incrementer is input, and the conversion result of the successive approximation register or the incrementer conversion result is selected according to the discrimination result of the byte / word discrimination circuit. The analog / digital converter according to any one of claims 1, 4, 5, and 6, which is configured to be read out.